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Electrical Power and Energy Systems 47 (2013) 157–167

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Electrical Power and Energy Systems

journal homepage: www.elsevier .com/locate / i jepes

An experimental investigation on a multilevel inverter for solar energy applications

Venkatachalam Kumar Chinnaiyan a,⇑, Jovitha Jerome b, J. Karpagam c

a Department of Electrical and Electronics Engineering, Dr. NGP Institute of Technology, Coimbatore 641 048, Indiab Department of Instrumentation & Control Systems Engineering, PSG College of Technology, Coimbatore 641 004, Indiac Department of Electronics and Communication Engineering, Dr. NGP Institute of Technology, Coimbatore 641 048, India

a r t i c l e i n f o a b s t r a c t

Article history:Received 10 December 2011Received in revised form 17 October 2012Accepted 20 October 2012Available online 5 December 2012

Keywords:InvertersPower electronicsSolar energyDrivesPower convertersMulti level inverterField programmable gate array

0142-0615/$ - see front matter � 2012 Elsevier Ltd. Ahttp://dx.doi.org/10.1016/j.ijepes.2012.10.025

⇑ Corresponding author. Tel.: +91 9942999111.E-mail addresses: [email protected] (V. K

yahoo.com (Jovitha Jerome), [email protected]

The main objective of the proposed work is to design, develop and test a three phase multilevel inverterwith the modern power electronic switches to reduce the power quality issues in solar power conversionsystem. Due to the increased usage of power electronic converters for processing the power in all walks ofour life, the power quality problem become the hot research topic in the recent years. As the power levelincreases, the voltage level is increased accordingly to obtain satisfactory efficiency. The multilevel powerconverter has shown growing popularity. The fundamental advantages of multilevel converter topologiesare low distorted output waveforms and limited voltage stress on the switching devices and hence thereduced electromagnetic interferences. The main disadvantages are higher complexity and more difficultcontrol; it can be overcome by using modern digital controllers. In this paper, the performance parame-ters are analyzed with the developed prototype of the three phase cascaded multilevel inverter for solarenergy conversion designed with digital controller for reduced power quality issues with three phase ACmotor drive. The main objective is to obtain the better quality of output waveform on the inverter outputwith suitable control strategy on the experimental hardware setup.

� 2012 Elsevier Ltd. All rights reserved.

1. Introduction continue without the any degradation on the environment,

Consumption of energy has become a daily necessity in moderncivilization for the comfort and convenience of humanity, and theamount of energy consumption has served as an indicator for thestandard of living and the degree of industrialization. It has longbeen recognized that associated with this excessive daily energyconsumption is an adverse impact on the environment we livein, resulting in deterioration of the local and global environment.However, utilization of energy from different sources tends to havedifferent kinds and different degrees of impact on the environ-ment. The energy from renewable sources may be considered tohave minimal or neutral impact on the environment.

An energy system is like a double-edged sword; its use wouldnormally bring about economic growth and social advancementas a whole, and comfort and convenience for individuals. On theother hand, a persistent and large-scale use of a particular energysystem will also bring about inevitable negative environmental, so-cial and economic impact, and when this negative impact is accu-mulated beyond a tolerance limit, permanent damage orcatastrophe would occur. Since the Industrial Revolution, increasedenergy use has brought about economic prosperity and an im-proved standard of living. It is fully expected that this trend would

ll rights reserved.

umar Chinnaiyan), jjovitha@(J. Karpagam).

economic and social growth. The target or objective is then to de-velop a magic energy system or systems that have no negativeenvironmental, economic and societal impacts, which we refer toas ‘‘green energy’’. Any energy system that has reduced or minimaladverse impact might be considered as ‘‘greener’’ energy. This def-inition of green energy implies that green energy, as the eventuallong-term objective, will provide an important attribute for sus-tainable development. This is because attaining sustainable devel-opment requires the use of energy resources and technologies thatdo not have adverse environmental, economic and societal impact.Clearly, single energy resources such as fossil fuels are finite andthus lack the characteristics needed for sustainability, while others,such as renewable energy sources, are sustainable over the rela-tively longer term. Green energy sources are solar, wind, biomass,hydro, nuclear, geothermal, etc. Energy economics in the presentera refers to energy market, electricity market, Carbon di-oxide(CO2) credit trading, clean development mechanism, Emissioncredit/trading, investment and payback time. With the advent ofmodern materials and the reduction of the cost, the solar energybased power system; it becomes the most preferred eco friendlypower generation concept in the recent past [13].

2. Solar radiation and daylight measurement

Systematic measurements of diffuse solar energy and the global(total) irradiation incident on a horizontal surface are usually

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158 V. Kumar Chinnaiyan et al. / Electrical Power and Energy Systems 47 (2013) 157–167

undertaken by a national agency, which is the national meteoro-logical office in many countries. The measurement network in-cludes pyranometers, solarimeters, or actinography instrumentsfor this purpose. In practice, it is very important to appreciatethe order of measurements prior to any modeling. The presentstate of solar radiation and daylight models is such that they areapproaching the accuracy limits set out by the measuring equip-ment [20]. Radiation in the visible region of the spectrum is oftenevaluated with respect to its visual sensation effect on the humaneye. In many countries, diurnal bright sunshine duration is mea-sured at a wide number of places. The hours of bright sunshineare the time during which the sun’s disk is visible. On a clear daywith a cloudless sky the burn does not start until 15–30 min aftersunrise and usually ceases about the same period before sunset.This period varies with the season. On the other hand, under peri-ods of intermittent bright sunshine the burn spreads.

Irradiation, which is defined as the solar power per unit area,solar radiation is radiant energy per unit area. Solar radiation isdetermined by summing solar irradiance over time and it is ex-pressed usually in units of kW/m2 per day. Solar energy has anadvantage over other renewable energy sources. It is more efficientin terms of the power that can be produced from a given area ofland [12]. According to one estimate, solar power plants can pro-duce about six times more power than bio fuels or wind. Solarpower’s advantage over water power is even greater.

3. Inverters

Inverters accept an electrical current in one form and output thecurrent in another form. An inverter converts Direct Current (DC)into Alternating Current (AC), whereas a rectifier converts AC intoDC. There are also DC–DC converters, which step up or step downthe voltage of a DC current. Inverters convert DC power from thebatteries or solar array into 60 or 50 Hz AC power. Inverters canbe transformer based or high-frequency switching types. Inverterscan stand alone, be utility interconnected, or be a combination ofboth [14]. As with all power system components, the use of invert-ers results in energy losses due to inefficiencies. Inverters are aninteresting option due to the great variety of low-cost appliancesthat run on AC.

Inverters are a key component to most Photo Voltaic (PV) sys-tems installed in grid connected or distributed applications. Asidefrom the modules themselves, inverters are often the most expen-sive component of an installed PV system, and frequently are thecritical factor in terms of overall system reliability and operation.Utility interactive PV systems installed in residences and commer-cial buildings will become a small, but important, source of electricgeneration over the next 50 years. This is a new concept in utilitypower production, a change from large-scale central generationto small-scale dispersed generation [16]. The basic system is sim-ple; utilizing a PV array producing DC power that is converted toAC power via an inverter to the grid is very simple, yet elegant.

The AC produced by inverters can have square, modified sine, orquasi sine waves and pure sine wave outputs. The pure sine waveis high cost, high efficiency, and has the best power quality. Mod-ified sine wave is mid-range cost, quality, and efficiency. Squarewave is low cost and low efficiency, and it has poor power qualitythat is useful for some applications. Square wave signals can beharmful to some electronic appliances due to the high voltage har-monic distortion. All inverters emit electromagnetic noise.

The harmonic frequencies and their magnitudes that appear ona system are governed by the shape of the distorted wave. The out-put capacity of an inverter is expressed in Volt Amperes (VA). Dur-ing start up, devices such as motors require a VA power inputseveral times greater than continuous power. This demand exists

for only a brief period of time. Most motors use 20% more powerand run hotter with modified sine wave than with pure sine wave.

Maximum output power is the maximum number of Watts theinverter can produce continuously. Harmonic distortion is distor-tion of the output waveform (2–35%). The solar energy is harnessedwith the use of Bosch Solar Cell M 3BB C3 1200 which has higherefficiency compared to the other solar panels available in the mar-ket and the other notable features are High annual yields, evenwith sub optimal levels of sunlight, thanks to excellent perfor-mance in weak light conditions, Pioneering three bus bar technol-ogy reduces the series resistance and helps to boost the poweroutput in the module. Fig. 1A and B shows the current voltagecharacteristics and spectral response of the PV cells respectively.

3.1. Grid tied inverters

Grid-tied inverters are widely used in Europe, Japan, and theUnited States to inter tie PV systems with the electric utility grid.These inverters convert the DC power to AC power in synchroniza-tion with the electric grid (UL 1741). When the grid goes down, theinverters go off by design. PV system utility interconnection con-siderations include safety, anti islanding, and power quality. Theinverter should be correctly wired and have proper wire sizes, fus-ing, and breaker sizes and types. PV system anti islanding protec-tion methods include grid shorted, grid open, anti islandinginversion synchronization, over or under frequency, and over orunder voltage. The typical solar power generation with grid tied in-verter system is shown in Fig. 2.

3.2. Multi level inverters

The multilevel inverters perform power conversion in multi-level voltage steps to obtain improved power quality, lowerswitching losses, better electromagnetic compatibility, and highervoltage capability [2]. Considering these advantages, multilevelinverters have been gaining considerable popularity in recentyears.

In the recent past, the multilevel inverters have drawn tremen-dous interest in the field of high voltage and high power applica-tions. In the researches of multilevel inverters, its correspondingcontrol strategies are one of the research hot areas. One of the mostimportant problems in controlling a multilevel voltage source in-verter is to obtain a variable amplitude and frequency sinusoidaloutput by employing simple control techniques [15]. Indeed, involtage source inverters, non fundamental current harmonicscause power losses, electromagnetic interference and pulsatingtorques in AC motor drives.

Harmonic reduction can then be strictly related to the perfor-mance of an inverter with any switching strategy. Multilevelinverters can increase the power by (m � 1) times than that oftwo-level inverter through the series and parallel connection ofpower semiconductor devices [10]. Comparing with two level in-verter system having the same power, multilevel inverters hasthe advantages that the lower harmonic components on the outputvoltages, Electro Magnetic Interference (EMI) problem could be de-creased much. Due to these merits, many studies about multilevelinverters have been performed at simulation level and very fewwith hardware implementations [1].

3.3. Types of multilevel inverters

The multilevel inverter is best suited for the application whichdemands the finest quality of the AC supply waveforms. The mul-tilevel inverters have many advantages when compared with con-ventional two level inverters as listed in Table 1.

Fig. 1. (A) I–V characteristic of Bosch Solar Cell M C31200. (B) Spectral response.

Fig. 2. Typical utility interactive PV system components.

V. Kumar Chinnaiyan et al. / Electrical Power and Energy Systems 47 (2013) 157–167 159

This work proposes a different control scheme, which is fullypertained to cascaded multilevel inverters. Multilevel invertertopologies are classified into three categories diode clampedinverters, flying capacitor inverters and cascaded inverters. The de-tailed comparison among these is tabulated in Table 2. Cascadedinverters by Casadei et al. [21] have structurally not any problemof DC link voltage unbalancing or the requirement of the largercapacitors but it requires many separated DC sources which is con-sidered as a major advantage with the present day rechargeablebatteries.

The batteries are usually rated for 12 V/24 V, in order to buildan inverter system for high voltage motor drive applications forcritical loads they are connected in series to obtain the higher volt-age ratings. The batteries can be replaced with the array of solar PVcells provided the voltage ratings are matched with the inverter in-put requirements. The cascaded inverter has been largely studiedand used in the fields of Static Volt Ampere Reactive Compensators(SVCs), voltage stabilizers, solar PV systems and so on [18]. It maybe noted that due to other advantages of the modularized circuitlayout and package, the cascaded inverter could be selected as a

Table 1Comparison of conventional two level inverters and multilevel inverters.

S. no. Conventional inverter M

1 Higher THD in output voltage L2 More switching stresses on devices R3 Not applicable for high voltage applications A4 Higher voltage levels are not produced H5 Since dv/dt is high, the EMI from system is high S6 Higher switching frequency is used hence switching losses is high L7 Power bus structure, control schemes are simple C8 Reliability is high R

Table 2Comparison of different multilevel inverter topologies.

S. no. Topology Diode clamped Flyin

1 Power semi conductor switches 2(m � 1) 2(m2 Clamping diodes per phase (m � 1)(m � 2) 03 DC bus capacitors (m � 1) (m �4 Balancing capacitors per phase 0 (m �5 Voltage unbalancing Average High6 Applications Motor drive system, STATCOM Moto

good choice in high voltage motor drive and grid interconnectionapplications [19].

When compared to diode clamped and flying capacitor invert-ers, cascaded inverter requires the least number of componentsto achieve the same number of voltage levels.

3.4. Three phase five level CMLI

For low and medium power application single phase invertermay cater the power requirements, for larger power and grid con-nected application three phase inverters are preferable one [3]. Thethree phase five level cascaded multilevel inverter is constructedby combining the H bridges of (n � 1) numbers. The three phaseoutput is obtained by combining the H bridges for individualphases as shown in Fig. 3. The individual H bridges are poweredby separate PV panels or by DC sources.

The phase output voltage is synthesized by the sum of four Hbridge inverter’s outputs, i.e., Van = V1 + V2 + V3 + V4. Each single-phase full bridge inverter can generate three level outputs, +VDC,0, and �VDC. This is made possible by connecting the DC sources

ultilevel inverter

ow THD in output voltageeduced switching stresses on devicespplicable for high voltage applicationsigher voltage levels are producedince dv/dt is low, the EMI from system is lowower switching frequency can be used and hence reduction in switching lossesontrol scheme becomes complex as number of levels increaseseliability can be improved, rack swapping of levels is possible

g capacitor Cascaded

� 1) 2(m � 1)0

1) (m � 1)/21)(m � 2)/2 0

Very smallr drive system, STATCOM Motor drive system, PV, fuel cells, battery system

Fig. 3. Structure of three phase five level cascaded multilevel inverter.


sequentially to the AC side via four power semiconductor powerdevices. Each level of the full bridge inverter consists of fourswitches, S1, S2, S3 and S4. Using the top level as the example,turning ON S1 and S4, yields V1 = +VDC. Turing ON S2 and S3, yieldsV1 = �VDC. Turning OFF all power switches yields VDC = 0. Similarly,the AC output voltage at each level can be obtained in the samemanner. Minimum harmonic distortion is obtained by controllingthe conducting angles by adopting correct control scheme at differ-ent inverter levels [4].

4. Multicarrier PWM techniques

Multicarrier Pulse Width Modulation (PWM) techniques entailthe natural sampling of a single modulating or reference waveformtypically being sinusoidal same as that of output frequency of theinversion system, through several carrier signals typically being

Sinusoidal Pulse Width Modu

Modulating Signal

Other techniques

Dead Band

Third Harmonic Injection

Pure Sinusoidal

Fig. 4. Classificati

triangular waveforms of higher frequencies of several kilo Hertz.They can be categorized as shown in Fig. 4.

4.1. Proposed SVPWM for multilevel inverter

The Sinusoidal Pulse Width Modulation (SPWM) technique,when applied to multilevel inverters, uses a number of level-shifted carrier waves to compare with the reference phase voltagesignals [8]. The Space Vector Pulse Width Modulation (SVPWM) formultilevel inverters involves mapping of the outer sectors to an in-ner sub hexagon sector, to determine the switching time duration,for various inverter vectors. Then the switching inverter vectorscorresponding to the actual sector are switched, for the time dura-tions calculated from the mapped inner sectors [6,7]. It is obviousthat such a scheme, in multilevel inverters, will be very complex,as a large number of sectors and inverter vectors are involved. This

lation

Carrier Signal

Phase Disposition (PD)

Super Imposed Carrier (SIC)

Phase Opposition Disposition (POD)

Alternate POD (APOD)

Hybrid (H)

Phase Shift (PS)

on of SPWM.


will also considerably increase the computation time for real timeimplementation.

A modulation scheme is developed, where a fixed commonmode voltage is added to the reference phase voltage throughoutthe modulation range. It has been shown that this common modeaddition will not result in a SVPWM like performance, as it will notcenter the middle inverter vectors in a sampling interval. The com-mon mode voltage to be added in the reference phase voltages, toachieve SVPWM like performance, is a function of the modulationindex for multilevel inverters. A carrier based PWM scheme hasbeen presented, where sinusoidal references are added with aproper offset voltage before being compared with carriers, toachieve the performance of a SVPWM [4]. The offset voltage com-putation is based on a modulus function depending on the DC linkvoltage, number of levels and the phase voltage amplitudes.

A novel method is developed to obtain an equivalent SVPWMpulses for the proposed multilevel inverter from the conventionalSinusoidal Pulse Width Modulation.

To obtain the maximum possible peak amplitude of the funda-mental phase voltage in linear modulation, a common mode volt-age obtained from the circuit shown in Fig. 5, where V�a, V�b and V�care the reference phase voltages and, V�a SFO, V�b SFO and V�c SFO are thesampled reference voltages. Voffset1, is added to the reference phasevoltages where the magnitude of Voffset1 is given by,

Voffset1 ¼ �ðVmax þ VminÞ=2 ð1Þ

where Vmax is the maximum magnitude of the three sampled refer-ence phase voltages, in a sampling interval, Vmin is the minimummagnitude of the three sampled reference phase voltages, in a sam-pling interval.

i:e:Vmax ¼MaxðVan;Vbn;V cnÞ

Vmin ¼MinðVan;Vbn;V cnÞ

The addition of the common mode voltage, Voffset1, results in theactive inverter switching vectors being centered in a samplinginterval. It makes the SPWM technique equivalent to the SVPWMtechnique. Eq. (1) is based on the fact that, in a sampling interval,the reference phase which has lowest magnitude (termed the minphase) crosses the triangular carrier first and causes the first tran-sition in the inverter switching state. While the reference phase,

Fig. 5. Calculation of Voffset1 from phase voltage samples.

Fig. 6. Reference voltages and triangular c

which has the maximum magnitude (termed the max phase),crosses the carrier last and causes the last switching transition inthe inverter switching states in a two level SVPWM scheme.

Thus the switching periods of the active vectors can be deter-mined from the (max phase and min phase) sampled referencephase voltage amplitudes in a two level inverter scheme. TheSPWM technique for multilevel inverters, involves comparing thereference phase voltage signals with a number of symmetrical levelshifted carrier waves for PWM generation. It has been shown thatfor an n-level inverter, n � 1 level shifted carrier waves are re-quired for comparison with the sinusoidal references. Because ofthe level shifted multi carriers as shown in Fig. 6, the first crossing(termed the first cross) of the reference phase voltage cannot al-ways be the min phase. Similarly, the last crossing (termed thethird cross) of the reference phase voltage cannot always be themax phase. Thus the offset voltage computation, based on Eq. (1)is not sufficient to center the middle inverter switching vectors,in a multilevel PWM scheme during a sampling period Ts shownin Fig. 7. In this, a simple technique to determine the offset voltage(to be added to the reference phase voltage for PWM generation forthe entire modulation range) is presented, based only on the sam-pled amplitudes of the reference phase voltages.

The proposed scheme is to determine the sampled referencephase, from the three sampled reference phases, which crossesthe triangular first (first cross) and the reference phase whichcrosses the triangular carrier last (third cross). Once the first crossphase and third cross phase are identified, the principles of offsetcalculation by Eq. (1), for the two level inverters, can easily beadapted for the multilevel SVPWM generation scheme. The pro-posed SVPWM technique presents a simple way to determine thetime instants at which the three reference phases cross the trian-gular carriers.

These time instants are sorted to find the offset voltage to beadded to the reference phase voltages for SVPWM generation formultilevel inverters for the entire linear modulation range, so thatthe middle inverter switching vectors are centered (during a sam-pling interval), as in the case of the conventional two level SPWMscheme.

4.2. Determination of inverter leg switching times

Fig. 6 shows a reference voltage and four triangular carriersused for PWM generation for a five-level inverter. The modifiedreference phase voltages are given by,

V�XN ¼ VXN þ Voffset;1 X ¼ A;B;C; ð2Þ

where VAN, VBN, VCN are sampled amplitudes of three referencephase voltages during the current sampling interval.

The reference phase voltages are equally spaced between thefour carriers, for five level inverter. For modulation indices lessthan 0.433 (half of the maximum modulation index in the linearrange of modulation for a five level inverter), the reference phase

arriers for a five level PWM scheme.

Fig. 7. Determination of the Ta_cross, Tb_cross and Tc_cross during switching interval TS (MI = 0.433).


voltage spans inner two carriers. For modulation index higher than0.433, the reference phase voltages expand into the outer carrierregions. The addition of Voffset1, obtained from Eq. (1), to the refer-ence phase voltage ensures that the modified reference voltages al-ways remain within the carrier regions through the linearmodulation range.

The reference phase voltages cross the triangular carriers at dif-ferent instants in a sampling period Ts shown in Fig. 7. Each time areference phase voltage crosses the triangular carrier, it causes achange in the inverter state. The sampling time interval Ts, canbe divided into four time intervals T01, T1, T2 and T03. T01 and T03

are defined as the time durations for the start and end inverterswitching vectors respectively in a sampling time interval Ts, T1

and T2 are defined as the time durations for the middle inverterswitching vectors, in a sampling time interval Ts. It should be notedfrom Fig. 8 that the middle switching vectors are not centered in asampling interval Ts. So an additional offset (offset2) needs to beadded to the reference phase voltages, so that the middle inverterswitching vectors can be centered in a sampling interval, similar toa two level SVPWM.

The time duration, at which the A phase crosses the triangularcarrier, is defined as Ta_cross. Similarly, the time durations, whenthe B phase and C phase cross the triangular carrier, are definedas Tb_cross and Tc_cross, respectively. When A phase is in the carrierregion C1 while the B phase and C phase are in carrier region C2,the time duration, Ta_cross, (measured from the start of the samplinginterval) at which the A phase crosses the triangular carrier is di-rectly proportional to the phase voltage amplitudes, VAN. The timeduration Tb_cross at which the B phase crosses the triangular carrieris proportional to V�BN þ

VDC4

� �and the time duration, Tc_cross, at

which the C phase crosses the triangular carrier and it is propor-tional to V�CN þ

VDC4

� �. Therefore

Ta cross ¼ V�AN þVDC

4¼ T�as ð3Þ

Tc cross ¼ V�CN þVDC

4

� �� Ts

VDC4

¼ T�cs þ Ts ð4Þ

Fig. 8. Determination of the Ta_cross, Tb_cross a

Tb cross ¼ V�BN þVDC

4

� �� Ts

VDC4

¼ T�bs þ Ts ð5Þ

where T�as;T�bs, T�cs are the time equivalents of the phase voltage

magnitudes.The proportionality between the time equivalents and corre-

sponding voltage magnitudes is defined as follows:

VDC4

Ts¼ V�AN

T�as

VDC4

Ts¼ V�BN

T�as

VDC4

Ts¼ V�CN

T�cs

In Fig. 8, where the reference phase voltages span the entire car-rier region for a five level inverter scheme. The time durations, atwhich the reference phase voltages cross the carrier can be simi-larly determined.

Reference voltages span the entire carrier region,0.433 < MI < 0.866.

Ta_cross is proportional to ðV�AN �VDC

4 Þ whereas Tb_cross is propor-tional to ðV�BN þ

VDC2 Þ and Tc_cross is proportional to ðV�CN þ

VDC4 Þ There-

fore, from Eq. (4)

T first cross ¼minðTx crossÞ;Tsecond cross ¼midðTx crossÞ;Tthird cross ¼maxðTx crossÞ; X ¼ a; b; c

ð6Þ

In the present work, the Ta_cross, Tb_cross and Tc_cross time dura-tions obtained above are used to center the middle switching vec-tors, as in the case of two level inverters, in the sampling intervalTs. The time duration, at which the reference phases cross the tri-angular carriers for the first time, is defined as Tfirst cross. Similarly,the time durations, at which the reference phases cross thetriangular carriers for the second and third time, are defined as,Tsecond cross and Tthird cross, respectively, in a sampling interval Ts.

nd Tc_cross during switching interval TS.


The time durations, Tfirst cross, Tsecond cross and Tthird cross, directlydecide the switching times for the different inverter voltage vec-tors, forming a triangular sector, during one sampling interval Ts.The time durations for the start and end vectors are T01 = Tfirst cross,T03 = Ts � Tthird cross, respectively. The middle vectors are centeredby adding a time offset, Toffset2 to Tfirst cross, Tsecond cross and Tthird cross.The time offset, Toffset2 is determined as follows. The time durationfor the middle inverter switching vectors, Tmiddle, is given by,

Tmiddle ¼ Tthird cross � T first cross ð7Þ

The time duration of the start and end vector is,

T0 ¼ Ts � Tmiddle ð8Þ

Thus the time duration of the start vector is given by,

T0=2 ¼ T first cross þ Toffset2

Therefore,

Toffset2 ¼ T0=2� T first cross ð9Þ

The addition of the time, Toffset2 to Ta_cross, Tb_cross and Tc_cross

gives the inverter leg switching times Tga, Tgb and Tgc for phasesA, B and C, respectively.

Tga ¼ Ta cross þ Toffset2

Tgb ¼ Tb cross þ Toffset2

Tgc ¼ Tc cross þ Toffset2

ð10Þ

The traces of different timing signals, for the proposed PWMscheme were captured for five level PWM generation.

4.3. Steps involved in the proposed SVPWM

The following are the steps involved to find out the switchingperiods of inverter legs for n level inverter scheme,

Step 1: Read the sampled amplitudes of VAN, VBN and VCN fromthe current sampling interval.Step 2: Determine the time equivalents of phase voltages, i.e.Tas, Tbs and Tcs.Step 3: Find Toffset1 using Tmax and Tmin, Tmax, Tmin are the max-imum and minimum of Tas, Tbs and Tcs.

Fig. 9. Offset volta

Fig. 10. Effective vol

Step 4: Determine Teffective.Step 5: Determine Ta_cross, Tb_cross and Tc_cross.Step 6: Sort Ta_cross, Tb_cross and Tc_cross to determine Tfirst cross,Tsecond cross and Tthird cross.(i) The maximum of Ta_cross, Tb_cross and Tc_cross is Tthird cross.(ii) The minimum of Ta_cross, Tb_cross and Tc_cross is Tfirst cross and

the remaining one is Tsecond cross.Step 7: Assign first_cross_phase, second_cross_phase andthird_cross_phase according to the phase which determines

T first cross; Tsecond cross and Tthird cross

Step 8: Determine Tga, Tgb and Tgc.

4.4. Modeling of proposed SVPWM

The SVPWM is implemented in the MATLAB/SIMULINK environ-ment based on the equations from Eqs. (1)–(10). The individualblocks are modeled with the corresponding equations and arelinked together to obtain the simulation results [11]. The blocksfor individual phases are interconnected and the SVPWM for threephase cascaded multilevel inverter is obtained.

The offset voltage waveforms are derived based on the equa-tions for offset voltage and from the sampled intervals of phasevoltages. The offset voltages are obtained for individual crosses likefirst_cross, second_cross etc., The obtained offset voltage wave-form for three phase five level cascaded multilevel inverter are asshown in Fig. 9. This offset voltage waveform is for the first_crossin similar way the other offset voltages are obtained for everycross.

After obtaining the offset voltages for individual crosses thetime equivalents are obtained with the addition of the time, Toffset2

to Ta_cross, Tb_cross and Tc_cross gives the inverter leg switching timesTga, Tgb and Tgc for phases A, B and C, respectively which is shown inFig. 10. This switching time intervals are given to the respectivephase power switches and the effective voltages for all the phasesare obtained and the same is captured with the aid of scope blockin the MATLAB/SIMULINK editor. The phase sequence for the out-put effective voltage waveform is A, B and C. The output waveformcoincides with the desired pattern which confirms that the respec-tive switches are turned ON and OFF at correct instances without

ge waveform.

tage waveform.

Fig. 11. Line voltage waveforms.


any crossovers. Fig. 11 shows the line voltage waveforms for themodeled system with the proposed technique for three phase fivelevel.

The output waveforms were analyzed in terms of percentage ofoutput Total Harmonic Distortion (THD) by varying the modulationindex for the different techniques adopted for simulation of themultilevel inverter configuration. The Modulation Index (MI) isvaried from 0.1 to 1 and the output THD levels are captured. Thepercent THD is very higher for lower MI and it is almost seventypercent when the MI = 0.1 and slightly differs for different control

Out

put V

olta

ge T

HD

in %

Output Voltage THD Vs MI

Modulation Index

Fig. 12. Output phase voltage %THD vs modulation index with different controltechnique.

Fig. 13. Block diagram for generation of firing

techniques. As MI is increased progressively the output THD levelsreduced considerably for the specific technique. As far as the out-put THD levels are concerned the SVPWM technique is showcasingthe better performance when compared to the other control tech-niques adopted for simulation as shown in Fig. 12.

When the modulation index is 0.8, all the control techniques al-most draws the same load current but for higher MI the few con-trol strategies gives the better results in terms of the magnitudeof the current.

5. System generator simulation blocks

The proposed algorithm is generated in front end with the aid ofsystem generator editor, the SVM blocks with the necessary sup-porting blocks and the associated blocks for individual phases areinterconnected and the sampling frequency is set to 5 kHz. The en-tire control algorithm based on SVPWM in the system generatorenvironment is as shown in Fig. 13. For simulation of the systemthe output supply frequency is varied from 10 Hz to 60 Hz whichis decided by the user input value. The wide range of frequencyis considered to analysis the output variations with respect tothe input and the pulse patterns for all the desired frequencies.The pulse generation process is initiated with the aid of the inputfrequency value through the switch and the analog to digital con-verter’s input to the controller.

pulses for CMLI using system generator.

Table 3Technical parameters of the AC motor used as load for the developed multilevelinverter.

S. no. Parameters Values

1 Motor type Induction motor2 No. of phases Three phase3 Connection Star4 Rated power 1.5 kW5 Rated voltage 415 V6 Rated current 3.35 A7 Rated Frequency 50 Hz8 Duty cycle S19 Rated speed 1400RPM

10 No. of poles 411 Rs, Ls 3.69 X, 0.26H12 Make Kirlosakar


The complete system is designed on the Xilinx system generatorenvironment using the blocks for the proposed Field Programma-ble Gate Array (FPGA) based three phase five level cascaded multi-level inverter for analysis purpose at simulation level [9].

5.1. System generator simulation for FPGA implementation

The obtained pulses are linked to the individual H bridges ofvarious phases of different levels with the aid of linker block. Fromthe linker block the gate pulses are linked to the individual Insu-lated Gate Bipolar Transistors (IGBTs) gate terminal to trigger.Once the power switches at different levels are supplied with thetriggering pulses it will get turned ON and OFF according to thesupplied pulse patterns. The output voltage starts to build upacross the bridges corresponding to the phase sequence of thepulse patterns [5].

6. Hardware specifications

The complete hardware specification of the proposed system isas follows

Multilevel inverter input and output supply specifications:

� Storage batteries with the combination of producing 72 V out-put DC.� Isolated photovoltaic panels (Bosch Solar Cell M3BBC31200)

with 72 V (3 � 24 V) output DC.� The input DC is 432 V (6 � 72 V).� Desired output: 5 kVA, output voltage 415 V, output current

10 A (Max).� Output frequency 40–60 Hz, Three phase AC supply confined to

IEEE standards.

6.1. Hardware implementation and results

The proposed control algorithm is generated in front end withthe aid of system generator editor, the SVPWM blocks with thenecessary transformation equations and the associated blocks forindividual phases are interconnected and the sampling frequencyis set to 5 kHz. The entire control algorithm with sampling rateof 5 kHz which is based on modified SVPWM algorithm is imple-mented in the system generator environment and correspondingcode for FPGA controller is generated. The generated code is down-loaded into the digital processor Xilinx Spartan 3A XC3S400 andthe hardware settings are enabled such that the output SVPWMpulses are available at the output ports.

6.2. Over load protection

In order to protect the power circuit components from the overloading and short circuit, current sensors are used to continuouslymonitor the load current supplied by the Cascaded Multi Level In-

Fig. 14. Photograph of the experimental hardware

verter (CMLI). Here four numbers of current transducers are em-ployed to monitor the line and neutral currents. The four currenttransducers are used to protect the power switches.

The current transducer LTS-25NP is used. This transducer iscapable of operating in three different ranges from 8 A to 25 Adepending on the pin connections. It operates on 5 V DC supplyand gives the maximum output voltage of 2.5 V depending onthe current flowing through the transducer. Here it is used to mea-sure the current from 0 A to 8 A and the pins are connected accord-ingly. The specifications of the AC motor used for testing are aslisted in Table 3. The rated current of the motor is 3.35 A, consid-ering the overshoot and starting current the protective circuit isdesigned for 8 A maximum. Pin 1 is used as input and the pin 4is used as output. For 8 A measurement pins 3 and 5, 2 and 6 areshort circuited. This gives the complete protection for power cir-cuit and protects the power devices against overload.

After the testing and commissioning of the hardware unit it issubjected to the various experimentations under different loadingconditions on its output side with the power harmonic analyzer. Inorder to load the three phase induction motor in a uniform mannera DC machine is operated as a self excited shunt generator and it ismechanically coupled to it. The DC generator is loaded with theresistive load and this setup constitutes the loading arrangements.The complete hardware setup is as shown in Fig. 14. This set upprovides a linear load variation on the inverter side and the perfor-mance parameters such as terminal voltage, voltage and currentharmonics levels and symmetry of three phase voltages for fre-quencies 40 Hz, 45 Hz, 50 Hz and 60 Hz are captured with the aidof Fluke make three phase power quality analyzer. Here the Fluke434 model is used, it is a three phase power quality analyzer, and itcomplies with the international standards. The power quality ana-lyzer is configured suitably for the testing [17].

The limits for the various power quality issues are set in accor-dance with the standard EN50160. The developed system isconnected to the AC motor i.e. loading arrangements and the read-ings are captured with the aid of power quality analyzer in thescope mode and the three phase output voltage waveform is as

setup with loading and measuring equipment.

Fig. 16. Output current and voltage harmonics of the developed system for 50 Hzoutput under loading condition.

Fig. 17. Phase displacements for three phase voltages at 45 Hz.

% T

HD

, Neu

tral

Vol

tage

Load Current (A)

% THD Vs Load Current for 50Hz

% Slip

%THDv

%THDi

Neutral Voltage in V

Fig. 18. Load current vs %THD for 50 Hz output.

Fig. 19. Output voltage waveform for R phase at rated condition.

Fig. 15. Three phase output voltage waveforms for 50 Hz output.


shown in Fig. 15 for the set frequency of 50 Hz on the digital pro-cessor. The output voltages in all the phases i.e. RYB are 396 V andthe phases are 120� apart from each other. The neutral potential iswithin the prescribed limits. The harmonics of the output voltageand the current harmonics are also listed in the harmonics tableof the analyzer as shown in Fig. 16. The table shows that the har-monics are very well within the limits prescribed by power qualitystandards.

The same is tested for 40 Hz, 45 Hz and 60 Hz. The phase dis-placements are captured and the same is shown in Fig. 17.

The observations on the output of developed hardware systemshow that the total harmonics distortions of the system are lessthan the five percent, which is the desired outcome.

From the obtained values the graph was plotted for differentoutput frequency of 40 Hz, 45 Hz and 60 Hz, Fig. 18 shows the plotfor 50 Hz. Fig. 19 shows the waveform obtained across the outputwith the aid of digital storage oscilloscope. On experimentation theoutput percentage THD for voltage, current and neutral potential iscollected continuously for various load currents and the valueswere tabulated.

7. Conclusion

The implementation and testing of a low cost FPGA based cas-caded multilevel inverter with solar energy conversion applicationfor induction motor drive was implemented. The main advantageof this system is the ability to generate SVPWM waveform genera-tion in real time using control algorithm implemented in the Xilinxprocessor. This reduces the computation time required to deter-mine the switching times for inverter legs, making the system suit-able for real-time implementation for larger drives where as thepower quality problems are the major considerations. Comparedto other control techniques the proposed SVPWM technique showsthe better quality of output waveforms. Furthermore during thetesting of output of the developed experimental setup with theFluke 434 model three phase power quality analyzer shows thatthe results exhibits the good quality of output waveforms withhigher fundamental component and also power quality issues arevery well within the limits. The %THD on voltage and currentwaveforms are always less than that of the five percent. The higherfundamental component on output results in reduced switchinglosses in semiconductor switches and induction motor. With theseresults it is concluded that the conventional drives with two levelinverters can be replaced with multilevel inverter where ever it ispossible in order to maintain the good quality of the power.

Acknowledgment

The authors are very much grateful to the officials of theDepartment of Science and Technology for their financial supportand their valuable suggestions, help at the critical times of this pro-ject. This research work is funded by the Department of Scienceand Technology (DST), Government of India, New Delhi, underthe title of ‘‘Design Analysis and Experimentation of Low CostDSP Based Multilevel Inverter for Industrial Applications with Re-duced EMI and Other Power Quality Issues’’ Grant order No.: SR/FTP/ETA-33/2006.

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