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20142016
Linearity Enhancement for GaN HEMT
Amplifier using Parallel Transistors with
Independent Gate Bias Control
Kanika Saini1, Amin K Ezzeddine2, Ho C Huang2, Sanjay Raman1
1Virginia Tech, Arlington, VA2AMCOM Communications, Gaithersburg, MD
20122016
Outline
• Introduction and Motivation.
• Linearity Discussion and Simulation.
• Amplifier Prototype design and Measurement Results.
• Conclusion and Future Works.
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20122016
Outline
• Introduction and Motivation.
• Linearity Discussion and Simulation.
• Amplifier Prototype design and Measurement Results.
• Conclusion and Future Works.
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20122016
Introduction and Motivation
• GaN HEMT’s have
– high output power density
– high efficiency
– poor intermodulation performance.
• Linearization techniques like feedforward, digital pre
distortion and Cartesian feedback are quite complex to
implement.
• We present a simple method to linearize GaN HEMT at
device and MMIC level, that has minimum impact on output
power and efficiency.
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20122016
Outline
• Introduction and Motivation.
• Linearity Discussion and Simulation.
• Amplifier Prototype design and Measurement Results.
• Conclusion and Future Works.
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20122016
Linearity Discussion
• Expression for the drain current is given for a common
source transistor is given as [1]
• IMD3 can be expressed as
• plays an important role in the non-linearity .
6
2 3' ".........
2! 3!
mDS dc gs gs gs
mm
g gi I g v v v
2"33
4
mgs
m
gIMD v
g
"mg
4/12/2016[1] B. Kim, J.-S. Ko, and K. Lee, “A new linearization technique for MOSFET RF amplifier using multiple gated transistors,” IEEE Microw. Guid. Wave Lett., vol. 10, no. 9, pp. 371–373, Sep. 2000.
20122016
Linearity Discussion Contd.
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• WiN Semiconductor devices (0.25 μm process) are biased
in the region (-3 V to -2 V ), closer to pinch off.
• I-V characteristics of 0.5 mm WiN Semiconductor GaN
HEMT were measured and was computed.
• has a negative peak which exacerbates the non-
linearity (pink curve).
"mg
, ', "m m m
g g g
20122016
Prior Work
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[1] B. Kim, J.-S. Ko, and K. Lee, “A new linearization technique for MOSFET RF amplifier using multiple gated transistors,” IEEE Microwave and Guided Wave Letters, vol. 10, no. 9, pp. 371–373, Sep. 2000.
CMOS 0.5 μm process, Frequency = 900 MHz, Improvement in IMD3 = 6 dBm @ Pout = -4.7 dBm [1]
20122016
MATLAB Simulation
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• A program was written in Matlab to shift in the
target range of second device w.r.t first one.
• Optimum solution is reached when least value for minimization function (Mf) is obtained in the target range.
• This step is tried for increasing the number of devices
(4 max).
2
"
1
1 N
mi
i
fM gN
"( )m gsg V
20122016
• The gate bias voltage of two transistors is varied w.r.t each other with
drain bias kept constant.
• Vgs bias of transistor B shifted by +1 V.
• Improvement in the minimization function is 60% if the Vgs1 = -2.5 V
and Vgs2 = -1.5 V.
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MATLAB Simulation (0.5 mm parallel transistors)
AB
A+B
B A
20122016
• The gate bias voltage of two transistors is varied w.r.t each other with
drain bias kept constant.
• Vgs bias of transistor B shifted by +1 V.
• Improvement in the minimization function is 60% if the Vgs1 = -2.5 V
and Vgs2 = -1.5 V.
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MATLAB Simulation (0.5 mm parallel transistors)
A+B
B A
1mm GaN HEMT
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MATLAB Simulation ( 4 parallel transistors)
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B A C D
A+B+C+D
•Simulation was performed with four devices in parallel (Shifted in Vgs values of each).
20122016
MATLAB Simulation ( 4 parallel transistors)
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B A C D
A+B+C+D
•Simulation was performed with four devices in parallel (Shifted in Vgs values of each).
2mm GaN HEMT
20122016
Comparison Table for simulation
14
Values of Vgs and Error computed
# of TxMf W/O
Shift
Mf with
Shift
Vgs
Value
Percentage
Improvement
1 0.187 N/A -2.5 V N/A
2 0.374 0.1396 -1.54 V 62.72%
3 0.5609 0.1356 -3.43 V 75.82%
4 0.7479 0.0628 -4.37 V 91.60%
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Comparison table for the percentage improvement with Vgs bias values of various devices. 90% improvement .
20122016
Outline
• Introduction and Motivation.
• Linearity Discussion and Simulation.
• Amplifier Prototype design and Measurement Results.
• Conclusion and Future Works .
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20122016
Amplifier Prototype Design (2 parallel transistors)
• 0.8 – 1.0 GHz, Pout = 40 dBm ,
PAE = 40%
• WiN Semiconductor 1.25 mm
GaN HEMT devices.
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A
B
20122016
Measurement Results (Two Tone linearity)
17
• Vgs1 = -2.5 V, Varying Vgs bias of the second transistor by +/-1 V.
• If the second device is biased at Vgs2 = -2.0 V, the IMD3 improves by 4 dBc up to Pout of 30 dBm.
• If the Tx2 is biased at Vgs2= -3.0 V, the IMD3 improves by 2 dBcfor higher output power level.
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4 dB
2 dB
20122016
Measurement Results Contd.
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• PAE improves with Vgs bias = -3.0 V at output power > 30 dBm.
• Comparison of PAE with IMD3.
20122016
Comparison of IMD3 and PAE
Gate Bias of 2nd
Tx (Vgs2)Pout (range)
IMD3
improvementPAE change
-3.5 V N/A None None
-3.0 V 30 – 34 dBm 2 dBc 5 %
-2.5 V Baseline -- --
-2.0 V 18 - 31 dBm ~ 3.5 dBc -1.5 %
-1.5 V 20 - 32 dBm ~ 3.5 to 4.3 dBc -1.5 to -2%
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Comparison of IMD3 and PAE for different Vgs values.
20122016
Outline
• Introduction and Motivation.
• Linearity Discussion and simulation.
• Amplifier Prototype design and Measurement Results.
• Conclusion and Future Works.
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20122016
Conclusion
• We demonstrated a method of improving linearity by
applying different gate bias voltages.
• The method breaks the transistor into multiple parallel
gates and apply different gate voltages to minimize the
gm” over the desired region of operation
• Improvement in IMD3 by 4 dBc with 2% loss in PAE up
to Pout of 30 dbm and 2 dBc with 5 % improvement in
PAE at Pout > 30dbm with two parallel gate transistors.
• Simple technique and widely applicable.
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20122016
Future Work
• Experimental demonstrations with 4 transistors in parallel
will be done.
• Design of GaN PA MMIC using this technique at higher
frequencies will be investigated.
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20122016
Questions?
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