SIMULATION EXPERIMENTS

EXPERIMENT : 1

D / A CONVERTOR with R /2R

AIM: To construct a 8 – bit digital to analog converter using R – 2R ladder type.

THEORY: A DAC accepts an n – bit input word b1, b2, ……, bn in binary and produces an analog signal that is proportional to the input. In this type of DAC, reference voltage is applied to one switch and the other switches are grounded. It is easier to build and number of bits can be expanded by adding more R – 2R sections. The circuit slows down due to stray capacitance.

OBSERVATION:

Decimal Equivalent of

binary number

InputOutput voltage

Vo(volts)Output voltage

Vo(volts)

J4 J3 J2 J1 Theoretical practical

0 0 0 0 0 01 0 0 0 1 -0.6252 0 0 1 0 -1.2503 0 0 1 1 -1.8754 0 1 0 0 -2.5005 0 1 0 1 -3.1256 0 1 1 0 -3.7507 0 1 1 1 -4.3758 1 0 0 0 -5.0009 1 0 0 1 -5.62510 1 0 1 0 -6.25011 1 0 1 1 -6.87512 1 1 0 0 -7.50013 1 1 0 1 -8.12514 1 1 1 0 -8.87515 1 1 1 1 -9.375

U1

741

3 2

47

6

51

V1

12 V

01

0

V2

12 V

20 R1

10kΩ

XMM1

3

0R

210kΩ

R3

10kΩR

410kΩ

R5

10kΩ

R7

5kΩ

R8

5kΩ

R9

5kΩ

R10

10kΩ0

67

8

V3

5 V

0

J1Key = A

9

J2Key = B

10

J3Key = C

11

J4Key = D

12

013

4

CIRCUIT DIAGRAM:

FORMULA USED:

Vo= -R1 (J 42R

+ J 34 R

+ J 28R

+ J 116 R)

OUTPUT:

J1=1, J2=1, J3=1, J4=1

RESULT: Thus R – 2R ladder type digital to analog converter is designed and implemented using PSPICE.

A / D CONVERTOR

AIM: To design and implement an analog to digital converter using PSPICE.

THEORY: An electronic integrated circuit whichtransforms a signal from analog (continuous) to digital (discrete) form. Analog signals are directly measurable quantities. Digital signals only have two states. For digital computer, we refer to binary states, 0 and 1.

ADC are used virtually everywhere where an analog signal has to be processed, stored, or transported in digital form. Some examples of ADC usage are digital volt meters, cell phone, thermocouples, and digital oscilloscope. Microcontrollers commonly use 8, 10, 12, or 16 bit ADCs, our micro controller uses an 8 or 10 bit ADC.

OBSERVATION:

Sl.No Analog I/P Vin C3 C2 C1 D1 D0

1 0 to v/4 0 0 0 0 0

2 V/4 to V/2 0 0 1 0 1

3 V/2 to 3V/4 0 1 1 1 0

4 3V/4 to V 1 1 1 1 1

VC

C5V

R1

100kΩK

ey=A50 %

R2

10kΩ

R3

10kΩ

R4

10kΩ

R5

10kΩ

U1A

7400N

U1B

7400NU

1C

7400N

U1D

7400N

U2A

LM324N

32

11 4

1U2B

LM324N

56

11 4

7U2C

LM324N

109

11 4

8

X1

2.5 V

X2

2.5 V

31

5

6

0 11 8910

X3

2.5 V

X4

2.5 V

X5

2.5 V

7

2

4

D0

D1

C3

C2

C1

VC

C

CIRCUIT DIAGRAM:

RESULT: Thus a analog to digital converter circuit is designed and implemented using PSPICE.

EXPERIMENT : 2

ANALOG MULTIPLIER

AIM: To design and implement a Analog Multiplierr using PSPICE.

THEORY: A basic amplier is an active circuit in which the output voltage is proportional to the

product of the two input signals. The terminals V+ and V- are supply terminals for the IC

where dual supply is to be connected. The X and Y are the two input terminals where the

the two inputs V1 and V2 are connected.

CIRCUIT DIAGRAM:

A1

1 V/V 0 V

Y

X

XMM1

V14 V V2

2 V

V3

2 Vrms 100 Hz 0°

V4

4 Vrms 100 Hz 0°

A2

1 V/V 0 V

Y

X

XMM2

V5

2 Vrms 100 Hz 0°

A3

1 V/V 0 V

Y

X

XMM3

V64 V

RESULT: Thus a Analog Multiplier is designed and implemented using PSPICE.

EXPERIMENT : 3

CMOS Inverter, NAND and NOR using PSPICE

AIM: To design and implement CMOS inverter, NAND and NOR using PSPICE.

THEORY: CMOS Inverter (or) CMOS NOT: CMOS is widely used in digital IC’s because of their high speed, low power dissipation

and it can be operated at high voltages resulting in improved noise immunity. The

inverter consists of two MOSFETs. The source of p-channel device is connected to

+VDD and that of n-channel device is connected to ground. The gates of two devices are

connected as common input.

CIRCUIT DIAGRAM:

Q1

2N7000

Q2

BST100

VDD5V

J1

Key = A

X1

2.5 V

TRUTH TABLE:

INPUT (J1) OUTPUT (X1)0 11 0

CMOS NAND:

It consists of two p-channel MOSFETs connected in parallel and two n- channel

MOSFETs connected in series. P-channel MOSFET is ON when gate is negative and N-

channel MOSFET is ON when gate is positive.Thus when both input is low and when

either of input is low, the output is high.

CIRCUIT DIAGRAM:

Q2

BST100

Q1

BST100

Q3

2N7000

Q4

2N7000

J1

Key = A

J2

Key = B

V15 V

V25 V

VDD5V

X1

2.5 V

TRUTH TABLE:

INPUT OUTPUTJ1 J2 X10 0 10 1 11 0 11 1 0

CMOS NOR:

(iii) CMOS NOR

It consists of two p-channel MOSFETs connected in series and two n-

channel MOSFETs connected in parallel. P-channel MOSFET is ON when

gate is negative and N-channel MOSFET is ON when gate is positive.

Thus when both inputs are high and when either of input is high, the

output is low. When both the inputs are low, the output is high.

CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUT OUTPUTJ1 J2 X10 0 10 1 01 0 0

Q1

BST100

Q2

BST100

Q3

2N7000

Q4

2N7000

V15 V

V25 V

J1

Key = A

J2

Key = B

VDD5V

X1

2.5 V

1 1 0

MODEL GRAPH:CMOS Inverter (or) CMOS NOT:

CMOS NAND:

CMOS NAND:

RESULT: Thus CMOS inverter, NAND and NOR is designed and implemented using PSPICE.

EXPERIMENT : 4

ACTIVE FILTERS

BUTTERWORTH 2nd ORDER LPF

(MAGNITUDE & PHASE RESPONSE)

AIM:

To design and implement the second order butterworth Low pass filter using PSPICE.

THEORY:

A low-pass filter is an electronic filter that passes low-frequency signals but attenuates

(reduces the amplitude of) signals with frequencies higher than the cutoff frequency. The

actual amount of attenuation for each frequency varies from filter to filter. It is sometimes

called a high-cut filter, or treble cut filter when used in audio applications. A low-pass

filter is the opposite of a high-pass filter.

CIRCUIT DIAGRAM:

U1

741

3

2

4

7

6

51

R1

33kΩ

R2

33kΩ

C14.7nF

C24.7nF

R4

15.8kΩ

R5

15kΩ

V112 V

V212 V

V3

5 Vrms 100MHz 0°

MODEL GRAPH:

OUTPUT:

RESULT: Thus Low pass filter is designed and implemented using PSPICE

BUTTERWORTH 2 nd ORDER HPF

(MAGNITUDE & PHASE RESPONSE)

AIM:

To design and implement the second order butterworth High pass filter using PSPICE.

THEORY:

A high-pass filter (HPF) is an electronic filter that passes high-frequency signals but

attenuates (reduces the amplitude of) signals with frequencies lower than the cutoff

frequency. The actual amount of attenuation for each frequency varies from filter to filter.

A high-pass filter is usually modeled as a linear time-invariant system. It is sometimes

called a low-cut filter or bass-cut filter. High-pass filters have many uses, such as

blocking DC from circuitry sensitive to non-zero average voltages or RF devices.

CIRCUIT DIAGRAM:

U1

741

3

2

4

7

6

51

R133kΩ

R233kΩ

C1

4.7nF

C2

4.7nF

R4

15.8kΩ

R5

15kΩ

V112 V

V212 V

V3

5 Vrms 100MHz 0°

MODEL GRAPH:

OUTPUT:

RESULT: Thus High pass filter is designed and implemented using PSPICE.

EXPERIMENT : 5

DIFFERENTIAL AMPLIFIER

AIM: To design and implement the differential amplifier using PSPICE.

THEORY: A differential amplifier amplifies the difference between two voltages V1 and V2. The output of the differential amplifier is dependent on the difference between two signals and the common mode signal since it finds the difference between two inputs it can be used as a subtractor.

The differential amplifier amplifies the difference between the two input voltage signals.Hence it is also called difference amplifier. In an ideal amplifer, the output voltage Vo is proportional to the difference between the two input signals. Hence we can write,

Vo = Ad(V1 – V2)

Where Ad referes to differential gain, which amplifies the difference between two input signals.

Vo=Ad/Vd

Ad=Vo/Vd

Generally the differntial amplifier is expressed in its decibel (db) valu as,

Ad=20 log10(Ad) in db

An average level of the two input signals is called common mode signal denoted as Vc.

Vc=( V1 + V2)/2

The gain with which it amplifies the common mode signal to produce the output is called common modesignal to produce the output is common mode gain of the differential amplifier denoted as Ac.

Vo=AcVc

Ac =Vo/VcTherefore the total output of any differential amplifier can be expressed as,

Vo= Ad Vd+ AcVcHigher the value of C.M.R.R, better the performance of the differential amplifier. To improve C.M.R.R we have to increase differential mode gain and decrease common mode gainCOMMON MODE:

Q1

BC

548BP

Q2

BC

548BP

R1

10kΩR

210kΩ

R3

1kΩ

R4

1kΩ

V1

10 V

V2

10 V

R5

8.2kΩ

XFG1

XSC1

AB

Ext Trig+

+

_

_+

_

DIFFERENTIAL MODE:

Q1

BC

548BP

Q2

BC

548BP

R1

10kΩR

210kΩ

R3

1kΩ

R4

1kΩ

56

V1

10 V

V2

10 V

R5

8.2kΩ

1

7

4

0

0

0

XFG1

XSC1

AB

Ex

t Trig+

+

_

_+

_

0

9

0

32

OUTPUT:

COMMON MODE:

DIFFERENTIAL MODE:

RESULT: Thus a differential amplifier is designed and implemented using PSPICE.

EXPERIMENT : 6

ASTABLE, MONOSTABLE AND BISTABLE MULTIVIBRATOR - TRANSISTOR BIAS

ASTABLE MULTIVIBRATOR:

AIM:

To plot the transient response of voltages at collector terminals of the two transistors Q1

and Q2. Initial node voltages at collector and base are zero.

THEORY:

It has two quasi stable states. The transition between the two states occurs automatically

due to charging and discharging of the capacitors and not due to any external trigger.

Thus none of the transistor is allowed to remain in ON or OFF state.

CIRCUIT DIAGRAM:

MODEL GRAPH:

OUTPUT:

Result: Thus astable multivibrator is designed and implemented using PSPICE.

MONOSTABLE MULTIVIBRATOR

AIM:

To design and implement a Monostable multivibrator using PSPICE

THEORY:

Monostable multivibrator has two states (i) quasistable state and (ii) stable state. When a

trigger input is given to the monostable multivibrator, it switches between two states. It

has resistor coupling with one transistor. The other transistor has capacitive coupling. The

capacitor is used to increase the speed of switching. The resistor R2 is used to provide

negative voltage to the base so that Q1 is OFF and Q2 is ON. Thus an output square wave

is obtained from monostable multivibrator.

CIRCUIT DIAGRAM:

MODEL GRAPH:

OUTPUT:

RESULT: Thus monostable multivibrator is designed and implemented using PSPICE.

BI-STABLE MULTIVIBRATOR

AIM:

To design and implement a bistable multivibrator using PSPICE

THEORY:

The bistable multivibrator has two stable states. The multivibrator can exist indefinitely

in either of the twostable states. It requires an external trigger pulse to change from one

stable state to another. The circuit remains in one stable state until an external trigger

pulse is applied. The bistable multivibrator is used for the performance of many digital

operations such as counting and storing of binary information. The multivibrator also

finds an applications in generation and pulse type waveform.

CIRCUIT DIAGRAM:

Q1

BC547A

Q2

BC547A

R1

68kΩ

R2

68kΩ

R32.2kΩ

R42.2kΩ

R568kΩ

R668kΩ

R7470Ω

C1

1nF

C2

1nF

C347uF

VCC5V

VCC

5

J1

Key = A

J2

Key = A

0

6

4

XSC1

A B

Ext Trig+

+

_

_ + _

0

12

MODEL GRAPH:

OUTPUT:

RESULT: Thus bistable multivibrator is designed and implemented using PSPICE.