Palatino 48 Arial 24

• Presentation to XXX Arial 16• 00 Month 2006

Solid partners. Flexible solutions.

Electrical Connector Failure Investigation

Peter Arrowsmith, Ops A La Carte LLC, TorontoPrakash Kapadia, Performance Innovation Lab., CelesticaMustafa Al-Salman, Colt WorleyParsons, TorontoRana Sodhi, Surface Interface Ontario, University of Toronto

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Background and Objectives• PCs experienced intermittent failure at customer sites• Failure could be reproduced by manually pushing down

the fan-CPU-socket stack during BIOS boot• The “flex test” was adopted as a screen. Fail rate was

20% in the worst period. • The repair corrective action was to rework and replace the

ZIF (Zero Insertion Force) socket• The objectives of this failure analysis are to:

– develop a method to identify the fail location(s)– determine the cause of electrical failure

3

Failure Mode History (1)

• The flex test was implemented after final assembly and functional test, zero fails occur

• Failure occurs during the BIOS boot, involving the CPU• Failure is typically not repeatable or reproducible• Swap back to original combination may not fail, indicates

removing/replacing the CPU can change the socket-CPU pin interaction.

• No known CPU component-level problems, no obvious evidence of physical damage, e.g. cracked solder joints

• ~300 pin-to-socket interconnects

4

Failure Mode History (2)

• Boot hangs are probably caused by CPU Vcc/data/address bit error(s), possibly caused by intermittent electrical opens or increased resistance

• Root cause is unknown, suspect causes of electrical open include:– mechanical: low contact force, misalignment, contact

opens– surface condition: wear, oxidation of socket contact

and/or CPU pin– contamination on the contacts: e.g. flux residues from

the connector wave solder attach process

• Conclusion: the flex test causes functional failure of susceptible cards due to mechanical stress applied to the CPU-socket interconnect assembly. The reason for the weakness is unknown.

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ZIF Socket Construction• Contact: phosphor bronze alloy, 0.4 µm (min) Au plating

over 1.3 µm (min) Ni• The closing action of the connector moves the CPU pins (L

to R in schematic) and pushes against the spring contacts• Since the contact surface is curved and the CPU pin is

cylindrical the nominal contact area is very small. The contact points comprise one or more asperities, d~10 µm.

• Contact resistance for clean Au surfaces with typical roughness and 20 g load is specified at 1-5 mΩ

Side view of spring contact (removed). Scale in mm. The location of cylindrical CPU pin is indicated.The end of the contact is tinned for PTH assembly.

Schematic of spring contact and CPU pin (planar section view)

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Failure Analysis Methodology: PC level• Top-down strategy, identify: (1) failing units and CPU-

socket assemblies, (2) specific failing pins within the socket, (3) the cause of failure on those pins

• To obtain a large contrast, FA was performed using best-of-best (BoB) and worst-of-worst (WoW) returns

• WoW cards consistently fail the power-on boot BIOS test:– pass BIOS boot, without mechanical load– fail two consecutive manual press-flex tests, and– fail press-flex with a static 2 kg load on the CPU fan

housing. WoWs are 4% of ~200 units tested. • BoB cards pass BIOS boot

under all conditions

Note: the number of flex tests per unit was kept small to minimize the risk of wear or other change to the socket-CPU interconnect

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Failure Analysis Methodology: socket & pin level• A new approach was developed to work around the

difficulty of electrical probe testing the card assembly• A WoW CPU-socket assembly under static mechanical

load was potted in epoxy (vacuum, 8 hour cure) – verified the WoW cards also fail BIOS boot after

potting and cure, with the static load removed– a BoB card remains functional through the same

preparation. Hence, potting does not cause good interconnects to fail

• This approach allows the electrical resistance of the CPU pin to socket contacts to be measured and mapped (see following slides)

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CPU-socket stack showing two-step sections• The potted socket was cut out from the assembly

(diamond saw) and sequential sections prepared:– Step 1: flat section to expose the tops of the CPU pins

above the connector, for electrical probing – Step 2: vertical section to release the socket spring

contact and CPU pin lengthways, for surface analysis– Step 1++: progressive flat sections to examine the

contact point between the spring contact and CPU pin

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C57 (WoW): electrical resistance probe pin map

Pins/contacts pulled for chemical analysis

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Failure Analysis Results: Electrical Mapping• Probed the signal pins, between top of CPU and socket

PTH contacts using a multimeter (probe 0.4 Ω)• BoB card: all pins <1 Ω. Hence, sample prep method does

not cause contacts to open• WoW card C44 (example):

– several high resistance pins (1-10 Ω) – highest E35, 10-50 Ω, is signal data line– verified a known good card fails boot if E35 is disabled– curve tracer shows linear V-I, resistive

• WoW C57: – several pins >10 Ω, 2 @ kΩ (data lines), 1 @ MΩ– SEM-EDX, FTIR, surface analysis performed on

selected contacts • Conclusion: flex test failure is caused by high

resistance contacts

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WoW C60, AL1 (MΩ) Progressive Flat Sections 1-5

• Section #1 is top (CPU side), #5 is lower (PCB side)

• Section #3 closest to contact point

• Note physical proximity of spring contact & CPU pin

CPU pin

Section #3, indicates deformation of CPU pin at the contact point

Conclusion: mechanical misalignment and physical opens are not the cause of high resistance contacts

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Vertical sections (step 2), CPU pins removed and contacts lifted from epoxy, to reveal contact surfaces

CPU pin Y35, likely contact pointsY33 contact surface (MΩ)

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SEM Analysis of CPU Pin Surfaces• FTIR did not show presence of organic contaminants• SEM imaging and SEM-EDX analysis of CPU pins:

– observe wear marks on Au surface, contact points?– found presence of Ni, F, as well as C,O, Au– exposed Ni is a concern because NiO is insulating and

will cause contact failure

C57, pin Y35 (84Ω), 5keVC57, pin Y33 (2MΩ)

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SEM-EDX of Socket Spring Surfaces, at CPU Pin Locations• Less evidence of wear, less exposed Ni, actual contact

point(s) could not be located• Presence of F on all contacts, as well as C, O • Evidence of correlation between C:Au, F:Au ratios vs. R,

indicates thicker / more uniform layer of contamination• No known source of F in the assembly process; possible

contamination or coating on the socket

C57, contact Y31 (0.4Ω), 5keV(typical spectrum, probably not the contact spot)

C57, contact Y33 (2MΩ), 5keV(typical spectrum, probably not the contact spot)

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XPS Analysis of Socket Surface• Probable presence of fluorocarbon, from high resolution

spectra peak assignments (match to PTFE). Not a perfluoroether lube (lack of –C–O–C– peak)

• Similar amounts of F on high and low resistance contacts (C57, Y33 & Y31). Thickness not determined.

• Possible flux residues. No obvious evidence of potting epoxy

3.00E+03

4.00E+03

5.00E+03

6.00E+03

7.00E+03

8.00E+03

9.00E+03

1.00E+04

1.10E+04

280281282283284285286287288289290291292293294295296297298

Cou

nts

/ s

Binding Energy (eV)

C1s Scan10 Scans, 200µm, CAE 50.0, 0.10 eV

C1s

C1s Scan A

C1s Scan B

C1s Scan CC1s Scan D

C1s Scan E

C1s Scan F

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Socket Contact Surface Analysis by TOF-SIMS• CFn fragments, confirm presence of fluorinated

hydrocarbon on contact surfaces (C57, Q31-37) Same conclusion from three independent methods.

• Fluorocarbon film thickness is 100-200 nm, est. from comparison of sputter time to PTFE (thickness varies with coverage)

Sample Parameter:Sample:Origin:

Q37 on heel

File: Q37_7P.dat

Spectrum Parameter:Polarity:Area / µm²:Time / s:PI dose:

Comments:

positive

TOF-SIMS IV100x10060.00E+000

ROI (brightest part);;

CF

CF3

CF2CF3

CCF2CF3

(CF2)2CF3

C(CF2)2CF3

mass / u20 40 60 80 100 120 140 160 180

4x10

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Inte

nsity

Analysis Parameters:

Energy:Current:Area:

Sample Parameters:Sample:Origin:

Polarity:

Q31

negativeFile: Q31_2N1.tfd PIDD: Unknow

99.6x99.6 µm²Unknow25 keV

Sputter Parameters:PI:Energy:Current:Area:PIDD: 1.90E+017 Ions/cm²

300.0x300.0 µm²15.10 nA3 keV

Comments:

Ga+ Ar+PI:

Note: Experimentally determined PTFE sputter parameters used. This is probably valid upto about 200 - 300 nm on this plot

TOF-SIMS IV

Depth / nm200 400 600 800 1000 1200 1400 1600 1800 2000

110

210

310

410

510

Inte

nsity

Substance Mass ColorC 12.00O 15.99OH 17.00F 19.00C2H 25.01CN 26.01Cl 34.97PO2 62.96Au 196.93Au(CN)2 248.99

F

Au

CN

Au(CN)2

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Connector Supplier info: contacts coated with “Anti-flux”• Active constituent is a “fluorinated polymer with perfluoroalkyl

groups” dispersed in solvent (b.pt. 116°C)• Inhibits wetting by solder flux (decreases surface energy)• Coating is not electrically conductive. The resistivity is

unknown (bulk or film)• The coating is soft and displaced by the contacts• The coating will melt at temperature >80°C and is “removed”

by solder(vendor info)

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Implications of coating on contact surfaces• Coating thickness is not directly controlled, or measured in

the application process• The coating resistance and condition following the assembly

process depend on the properties and chemistry (unknown to us). We now know the coating is present after wave.

• If the coating has the same resistivity as Cu2O (ρ = 104 Ω.m) is 100 nm thick, and present over a 10 µm contact spot, the contact resistance, CR = ρd /A = 13 MΩ

• Hence, presence of insulating coating on contact spots will cause failure

Now known to be false!

(vendor info; after coating)

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Conclusions (1)• Presence of electrically insulating contamination on socket

contacts results in high contact resistance on the CPU signal lines (esp. data, address and clock) causing functional failure

• The most likely source of contamination is anti-flux coating. However, contribution from other contaminants, such as NiO and flux, cannot be rejected, based on evidence

• Factors that may cause failure (not proven at this point):– the anti-flux coating hardens/polymerizes/becomes

more uniform and/or the film resistance increases, during exposure to temperature and flux during solder wave

– subsequent exposure to T&H, mechanical motion during shipping and installation, cause the contact resistance to increase

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Conclusions (2)• Why failure occurs during the flex test? (speculative):

– micro relative movement between the two contact surfaces break existing Au-Au microcontact(s)

– for ~0.1% pins (~10% of sockets), contamination is present at the new point of contact

– insulating particulates produced by wear of the contact surfaces may be trapped at contact points

• Corrective actions:– reseat the CPU in the socket - experienced high

subsequent failure rate– request the socket supplier use a coating with abrasive

metal particulates, to penetrate the insulating film– change the socket to a type without anti-flux coating

• The flex test fail rate was found to be significantly lower for sockets which do not have anti-flux

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Acknowledgements, Celestica personnel

• Al Hawley, Dan Beresford, Design Services• Toronto, Performance Innovation Lab: Zohreh Bagheri,

Prakash Kapadia, Jie Qian, Andrea Rawana• Charlotte Chang, Toronto CAMS• Robin Guyatt, customer business unit• Alan Gauthier, Global Commodity Engineer• Kulim team: Selvi Krishnan, Nazmi Noor, Seng Hwe Ong,

Kum Woh Toh, Wen Chong Yeow, CC Yong• Asia Regional support: TC Chong, George Lim