ELEC3509_Lab3

ELEC 3509 LAB 3

741 OPERATIONAL AMPLIFIER

Authors:Dean SHEPHERDSON

Zachary DUNNIGAN

Student Number:100829563100892725

Submitted: Friday November 21, 2014

Amplifier Project - Dean Shepherdson 100829563, Zach Dunnigan 100892725 - Final Copy 1

Contents1 Introduction 3

2 DC Calculations 3

3 AC Calculations 103.1 Stage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Stage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Stage 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.4 DC Open Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5 Common Mode Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.6 Output Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.7 Design Value for C1 and Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.8 Theory Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Simulation 224.1 Vo − Vd Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.2 Common Mode Range Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3 Comparison of DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.4 Revised Gain Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Results and Analysis 295.1 Frequency Response and Bode Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2 Calculated fu vs Simulated fu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.3 Slew Rate Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Conclusion 31


1 IntroductionThe topic of this report will highlight a simplified three-stage operational amplifier. The circuit was ana-lyzed manually and the results were compared with the results found using the circuit simulation softwareSPICE. The main operational amplifier (op-amp) that is of interest in this report is the 741 op-amp. Afull 741 op-amp circuit is complex, so a more simple version will be used to allow for a more manageableanalysis.

The main simplifications include removing a large portion of biasing circuitry and replacing them withideal equivalents. The 741’s output short circuit protection segment was also removed. These changesprovide a much more simple circuit to evaluate while still producing a simulation that represents real lifebehaviour well.

This report will cover the theory and design of the simplified op-amp using analysis techniques to de-termine the AC and DC characteristics. The same circuit was simulated electronically to observe if thetheoretical calculations could be compared within a reasonable margin of error considering all of the sim-plifications and assumptions made throughout the analysis. The simulation results will be compared andsummarized with all of the preliminary calculations to show the contrast between both methods used. Fi-nally, using the data from the electronic simulation, some characteristic plots will be exploited to show thebehaviour of the device which will also be compared to the theoretical counterparts.

A summary will be provided after the bulk of the report has been examined - to help confirm and comparethe important results determined in the analysis portion of the laboratory.

2 DC CalculationsThis section covers the preliminary DC calculations for the op-amp: extracting all the relevant character-istics of each transistor to further analyze the behaviour of the circuit.

Some assumptions were made to facilitate the analysis:• gm = IC

VT

• ro = VAIC

• β = 100

• VCC = 5V

• VBE = 0.6V

• IC = ISeVBEVT

• ISnpn = 6.735fA

• ISpnp = 1.41fA

• VAnpn = 80V

• VApnp = 20VFigure 1 illustrates the equivalent circuit that will be used for the DC analysis. The approach used will startfrom the output and work back to the input. All VBE’s were assumed except for the VBE’s of transistorsQ14 and Q20. A KVL loop was used around the loop containing V2 and the two transistors Q14 and Q20.


Figure 1: Full DC Op-Amp Circuit [1] [Zach]

KVL:

1.4V = VBE20 +R7IE20 +R6(IE20 + IR10) + VBE14

IC = ISeVBEVT → VBE = VT ln

(ICIS

)1.4V = VT ln

(IC20

IS20

)+R7IE20+R6(IE20 + IR10) + VT ln

(IC14

IS14

)IC =

β

β + 1IE

1.4V = VT ln

(ββ+1

IE20

IS20

)+R7IE20+R6(IE20 + IR10) + VT ln

(ββ+1

IE14

IS14

)1.4V = 0.0259 ln(7.022× 1014IE20) + 30IE20 + 30IE20 + 0.0259 ln(1.472× 1014IE20)

1.4V = 0.85463 + 0.0259 ln(IE20) + 60IE20 + 0.81556 + 0.0259 ln(IE20)

0 = 0.270187 + 60IE20 + 0.05 ln(IE20)

Solving numerically it was found that:IE20 = 1.1424mA

Therefore, the collector currents can be solved:

IC14 = αIE20 = 1.1311mA

IC20 = αIE20 = 1.1311mA

Now that the current in each collector has been found the VBE values can be determined:

VBE14 = VT ln

(IC14

IS14

)= 0.6462V

VBE20 = VT ln

(IC20

IS20

)= 0.6853V


The current through R10 → IR10 was assumed to be 0 for the analysis to solve for the current in theemitters explicitly.

IR10 =VoutR10

=VCC2R10

= 2.5µA

This current is much smaller than the current in the emitter so the assumption that it was to be 0 in theanalysis was reasonable.

Through symmetry the voltage across R6 and R7 are equal. To produce a voltage of 2.5V at the out-put the voltage across each resistor - using the same KVL loop:

1.4V = (0.6853V ) + VR6 + VR7 + (0.6462V )

VR6 + VR7 = 68.5mV

∴ VR6 = VR7 =68.5mV

2= 34.25mV


Figure 2: Q14 and Q20 segment of Op-Amp [1] [Zach]

As seen in figure 2 the voltages at the emitters ofQ14 andQ20 are found by simply applying the correctvoltage drop above/below the output node.

The next step is to determine the current flowing through Q23 (figure 3).

Figure 3: Q23 Segment of Op-Amp

IR13 =VCC − VB14

R13

= 20.2µA

The current in the emitter and collector of Q23 are then:

IE23 = 180µA+ IR13

IE23 = 200.2µA

∴ IC23 = αIE23 = 198µA

Repeating the same process to find the current through R12 - will lead to finding the total current throughQ17 as shown in figure 4.


Figure 4: Q17 segment of Op-Amp [1] [Zach]

IR12 =VCC − 1.18V

R12

= 127µA

∴ IC17 = 550µA+ IR12 + 2µA = 679µA

IE17 =IC17

α= 686µA

IB17 =IC17

β= 6.8µA

The node voltages were then determined by:

VE17 = IE17R8 = 0.0686V

VB17 = VE17 + 0.6V = 0.669V

Once again the same process was repeated for Q16 (figure 5).

Figure 5: Q16 segment of Op-Amp [1] [Zach]


IR9 =0.669V

50kΩ= 13.4µA

∴ IE16 = 13.4µA+ 6.8µA = 20.2µA

IC17 = αIE = 20µA

IB17 =IC16

β= 0.2µA

The remaining circuit to consider is the input stage. The common mode voltage is V5 = 2.5V . With anassumed VBE2 = 0.6V the shared emitter voltage is known and the current through R11 can be foundwhich will allow the completion of the analysis on the input stage (figure 6).

Figure 6: Input Stage of Op-Amp [1] [Zach]

IR11 =VCC − 3.1V

1MΩ= 1.9µA

Through symmetry:

IE1 = IE2 =19µA+ IR1

2= 10.45µA

IC1 = IC2 = 10.35µA

The current through the collector of Q6 is:

IC6 = IC2 − 0.2µA = 10.33µA

IE6 =IC6

α= 10.43µA


The corresponding node voltages are then:

VE6 = R2IE6 = 0.01V

VB6 = VE6 + 0.6V = 0.61V

∴ VE5 = VB6 − 0.6V = 0.01V → IE5 =0.1V

1kΩ= 10.43µA

IC5 = αIE5 = 10.33µA

This gives:

IB7 = IC1 − IC5 = 0.2µA

IC7 = βIB7 = 20µA

This value of IC7 was found to be too high since it violates KCL on Q7. Therefore the value was taken tobe the average of the collector current using IC = βIB and IC = αIE . The final value determined was:

IC7 = 16.5µA

This is likely due to the assumptions made and rounding errors that propagated throughout the entireanalysis. Table 1 shows a summary of all relevant DC characteristics found in the preliminary calculations.

Table 1: DC Calculation Results

Transistor IE(µA) IB(µA) IC(µA) gm(mA/V ) ro(Ω) rπ(Ω) β

Q1 (PNP) 10.4535 0.1035 10.35 0.414 1932367 241545.9 100Q2 (PNP) 10.4535 0.1035 10.35 0.414 1932367 241545.9 100Q5 (NPN) 10.4333 0.1033 10.33 0.4132 7744434 242013.6 100Q6 (NPN) 10.4333 0.1033 10.33 0.4132 7744434 242013.6 100Q7 (NPN) 16.3115 0.1615 16.15 0.646 4953560 154798.8 100Q16 (NPN) 20.2 0.2 20 0.8 4000000 125000 100Q17 (NPN) 685.79 6.79 679 27.16 117820.3 3681.885 100Q14 (NPN) 1142.31 11.31 1131 45.24 70733.86 2210.433 100Q20 (PNP) 1142.31 11.31 1131 45.24 17683.47 2210.433 100Q23 (PNP) 199.98 1.98 198 7.92 101010.1 12626.26 100


3 AC CalculationsThis section outlines all the required calculations for the AC characteristics of the 741 op-amp.

3.1 Stage 1The gain of the first stage is defined as the input to the base of Q16, including the impedance seen lookinginto the base of Q16 as a load to the first stage. Figure 7 represents the first stage segment of the op-amp.

Figure 7: Op-Amp Stage 1 [1]

This circuit can be modeled with its small signal equivalent shown in figure 8.

Figure 8: Op-Amp Stage 1 Equivalent Small Signal Model [1]

However this small signal is quite convoluted. This can be simplified to give us another equivalent formwhich we can extract more meaningful characteristics of how this circuit behaves and how it is controlled.Consider a differential pair driving a current mirror with no degeneration resistors and a single ended load.This circuit can be modeled as shown in the following two figures.


(a) Simplified Stage 1 Circuit [1](b) Simplified Small Signal Model [1]

Figure 9: Simplified Stage 1

In the case of a differential input - a virtual ground is produced. This means that the wire connectingthe node at R11 to the nodes between the current sources gm1vπ1, gm2vπ2, and the output resistances ro1and ro2 - has the same potential without any current flowing through it. The result of this effect is that R11

and that wire can effectively be removed, with no impact on the circuit’s behavior.Therefore, we make one more reduction to obtain the following model.

Figure 10: Small Signal with Virtual Ground Removed [1]

Using the simple model shown in figure 10 - the behaviour can now be analyzed. The voltage across theload (output to stage 2) can be shown by:

vL = (RL||ro6||ro2)(gm2vπ2 − gm6vπ6)

vπ6 = −(gm2vπ2)(ro5||rπ5||1

gm5

)

Since both transistors at Q5 and Q6 should be biased identically: gm5 = gm6.


Therefore the voltage across the load becomes:

vL = (RL||ro6||ro2)(gm2vπ2 + gm6(gm2vπ2)(

1

gm5

)

)vL = (RL||ro6||ro2)(2gm2vπ2)

vπ2 =

(rπ1

rπ1 + rπ2

)vin =

vin2

Finally, the overall gain can be represented as:

vL = 2gm2vin2

(RL||ro6||ro2)

Av1 =vLvin

= gm2(RL||ro6||ro2) = 281.85

The output resistance of stage one can be expressed using a test voltage to give:

Rout1 = ro6(1 + gm6(R2||rπ6) + (R2||rπ6) ≈ 10.5MΩ

If the input impedance of the second stage is large - the gain will be limited by the size of ro6. It isimportant to note that this gain is only an approximation. The addition of the degeneration resistancewould improve the output impedance roughly 15-20%. In this case, the output impedance is large enoughthat it does not make a significant difference. For the ease of analysis it was left out. The effect of thislarge output resistance is to limit the amount of extra current flowing from the first stage into the secondstage.


3.2 Stage 2The second stage of the op-amp is considered to have the input at the base of Q16 and the output at thecollector of Q17. Figure 11 shows the second stage of the op-amp.


The equivalent small signal model is illustrated in figure 12.

Figure 12: Stage 2 Equivalent Small Signal Model [Dean]

The input impedance of stage 2 can be described by:

Rin2 = rπ16 + (β + 1)[ro16||R9||(rπ17 + (β + 1)(R8||(ro17 +R12||RL)))]

Where RL in this case is Rin3. The value of RL is insignificant since it is in series with ro17 which isalready large (≈ 118kΩ) when compared to R8 (100Ω) which is in parallel with RL and ro17. Therefore,the small size of R8 will limit that term. Another simplification can be appended noting that the large sizeof ro16 ≈ 4MΩ it can be discarded since its parallel nature will have virtually no effect on the expression:

Rin2 = rπ16 + (β + 1)[R9||(rπ17 + (β + 1)(R8))] = 1.21MΩ


The gain can be determined in two steps: 1 - the gain from the output to the base of Q17, 2 - from the baseof Q17 to the input. These can be obtained using voltage divider expressions.

vout = −gm17vπ17(RL||R12)

1 + r8gm17 + R8

rπ17

vπ17 = vin

(ro16||R9||(rπ17 + (β + 1)R8)

ro16||R9||(rπ17 + (β + 1)R8) + re16

)Therefore, the gain can be expressed as:

Av2 =voutvπ17· vπ17vin

Av2 = −(

ro16||R9||(rπ17 + (β + 1)R8)

ro16||R9||(rπ17 + (β + 1)R8) + re16

)gm17(RL||R12)

1 + r8gm17 + R8

rπ17

= −195.37

The effect of ro17 was neglected since it is much larger than anything it is in parallel with. The currentwould much rather flow through the voltage controlled current source as if there was no ro17 in the circuit.

3.3 Stage 3The third and final stage of the op-amp can be defined with the input to the base of Q23 and the outputbetween the emitter’s of transistors Q14 and Q20. This segment can be seen below in figure 13.


The equivalent small signal model was realized in figure 14.This is a relatively simple small signal model due to the fact that the output is connected through theemitters of both transistors. Therefore it can be seen in figure 15 to help visualize the one step gainequation.


Figure 14: Stage 3 Equivalent Small Signal Model [Dean]

Figure 15: Stage 3 Gain Network [Dean]

The input resistance can be modeled by:

Rin3 = rπ23 + (β + 1)[(β + 1)R10 + (rπ14 + (β + 1)R6)||(rπ20 + (β + 1)R07)||(β + 1)R13] = 10.2GΩ

The gain for stage three can now be determined, using voltage divider expressions.

vout = vb20

(R10

R10 + ( rπ20β+1

+R7)||( rπ14β+1+R6)

)

vb20 = vin

((β + 1)[R10 + (re14 +R6)||(re20 +R7)||R13]

re23 + (β + 1)[R10 + (re14 +R6)||(re20 +R7)||R13]

)Av3 =

voutvb20· vb20vin

Av3 =

(R10

R10 + (re20 +R7)||(re14 +R6)

)((β + 1)[R10 + (re14 +R6)||(re20 +R7)||R13]

re23 + (β + 1)[R10 + (re14 +R6)||(re20 +R7)||R13]

)≈ 1

Note: the rπ’s are reduced to re’s due to the reflection from the base to the emitter in each transistor. R10

is the dominant resistance of each term respectively, therefore the large size of this resistances makes thegain of this stage approximately equal to 1.


3.4 DC Open Loop GainThe DC open loop gain is defined as the gain obtained when no load is attached to the circuit. This is aresult of the gain of the entire op-amp from stage 1 to stage 3. The gains for each stage were calculatedpreviously and will be used to help determine this result.

Aopen = Av1 · Av2 · Av3

Aopen = −gm2(Rin2||ro6||ro2) ·(

ro16||R9||(rπ17 + (β + 1)R8)

ro16||R9||(rπ17 + (β + 1)R8) + re16

)gm17(RL2||R12)

1 + r8gm17 + R8

rπ17

· 1

The above expression gives the overall open loop gain for the op-amp. Some of the terms in this expressionwere simplified with explanations in the respective sections.

gm17(RL2||R12)

1 + r8gm17 + R8

rπ17

≈ gm17(R12)

1 + r8gm17 + R8

rπ17

This input impedance is much larger than the 30kΩ value of the resistor R12. Therefore the simplified gaincan be expressed as:

Aopen ≈ −gm2(Rin2||ro6||ro2)(

ro16||R9||(rπ17 + (β + 1)R8)

ro16||R9||(rπ17 + (β + 1)R8) + re16

)gm17(R12)

1 + r8gm17 + R8

rπ17

≈ −55065V

V

This gain calculation is an approximation expected to be higher than the actual value - due to simplifica-tions. For example, large parallel resistances were ignored in the cases where the difference was negligible.Terms that were essentially 0.999 were taken to be one.


3.5 Common Mode RangeThe common mode range for DC biasing will be when the base ofQ2 is at 1.6V to 4.4V while still allowingthe transistors Q1 and Q2 to remain in the active mode.

Figure 16: Common Mode Ratio Justification [Dean]

The process used to find the minimum voltage at the base of Q2 was as follows (reference figure 7):

• The minimum voltage at the base of Q5 was determined to be 0.6V using the VBE property

• The base of Q5 is connected to the emitter of Q7: Using the VBE property again leaves VB7 = 1.2V

• Assuming a safe operating point of VCE = 1V this gives VE1 = 2.2V

• This traces around to VE2 = 2.2V - by VBE again: VB2 = 1.6V

Therefore the minimum voltage to stay within a reasonable operating point gives VB2 = 1.6V . Themaximum that can be achieved is the top rail at VE2 = 5V , therefore the maximum voltage that can appearon the base would be VB2 = 4.4V . In summation - the common mode range was determined to be from1.6V to 4.4V at the base of Q2.

3.6 Output SwingThe output swing is maximized when the voltage that appears at the output is half of the maximum inputvoltage - if the biasing allows this voltage to appear without affecting the desired behaviour of the transis-tors in between the input and output.Therefore the maximum voltage that can appear at the output is 4V with the VCE drop across transistorQ14 and the minimum voltage that can appear at the output is 1V from the VCE of Q20.Thus the output swing will range from 1V < swing < 4V .


3.7 Design Value for C1 and Slew RateFigure 11 shows the configuration of the second stage with the position of the capacitor C1. This capacitorlinks the input to the output of the second stage. Using Miller’s Theorem this capacitor can be split intotwo equivalent capacitances. Since the gain of stage 2 is sufficiently large - the pole will be dominated bythe capacitance that is extracted onto the input side.

Figure 17: Miller Theorem Equivalent Capacitances [Dean]

This equivalent capacitance shown in figure 17 is given as:

Ceq1 = C1(1−vc17vb16

) = C1(1 + Av2)

∴ C1 =Ceq1

1 + Av2

The equivalent resistance seen by the capacitor is the output impedance of stage 1 in parallel to the inputimpedance to stage 2.

Rout1 = ro6(1 + gm6(RS||rπ6)) + (R2||rπ6) ≈ 10.5MΩ

Rin2 = [re16 + ro16||R9||(rπ17 + rπ17R8gm17 +R8)] ≈ 1.21MΩ

The frequency at which the gain becomes one can be calculated by:

ωT = Avωp

ωp =ωTAv

ωp =2π · 1Mhz

55065≈ 114.1

rad

s

ωp =1

Ceq1(Rout1||Rin2)

∴ Ceq1 =1

ωp(Rout1||Rin2)

Substituting all appropriate equations and values yields:

C1 =1

ωp(1 + Av2)(Rout1||Rin2)

C1 ≈ 41.3pF


The slew rate represents the fastest rate of change of the amplifier. From Miller’s Theorem the fastestrate of change occurs when all the current flows into Ceq1. The resulting rate of change is determined forthe input of stage 2 - not the output. However, the gain from the input to the output of stage 2 is knownto be Av2. The gain of the second stage is sufficiently large such that the second effective capacitance iscanceled out. Therefore, the slew rate is defined as:

∆Vout1∆t

=I1Ceq1

From this we can relate the input voltage to the output voltage by:

∆Vout2∆t

= Av2∆Vout1

∆t= Av2

I1Ceq1

= Av2I1

(1 + Av2)C1

≈ I1C1

Using I1 = 19µA from the ideal current source in the simulation diagram - the resulting slew rate isdetermined to be:

SR =19µA

41.3pF= 0.460

V

µs

Note: The value of the capacitor used during simulation was 69.6pF - due to an initial calculation error.After further review, the values above were recalculated as the theoretical C1. A more in depth discussionis provided in the Results and Analysis section.

3.8 Theory QuestionsQuestion 1: Explain the difference in role of V10 and V5. Why are both needed?

V10 is the DC input voltage. It represents the DC voltage offset of the input signal when testing thedifferential input mode of the 741 op-amp. V5 is the common mode voltage which is applied to thedifferential terminals to test the common mode input of the 741 op-amp. Both are needed because a 741op amp has two possible input methods; differential mode and common mode. V10 is used for testing thedifferential mode input, while V5 is used to test the common mode input.

Question 2: What is the purpose of Q7 and R3 in this circuit? What difference would there be ifinstead of both, the collector and base of Q5 were shorted as in the current mirror in Lab 1?

Q7 and R3 are a safety mechanism built in to the 741 op-amp to prevent a high current at the input fromdamaging the amplifier. IfQ7 andR3 were removed, the circuit would behave very similarly under normalconditions. The Q5 and Q6 transistor network behave as a current mirror - they copy the DC currentfrom the branch of the circuit connected to Q5 into the branch connected to Q6. If the current in Q5 wasvery large, it would be copied into the second stage of the op-amp, which could potentially damage theamplifier. However, the addition of Q7 and R3 the high current in the Q5 branch will turn off transistorQ7. Hence, the purpose of a safety mechanism to protect the rest of the circuit. The excess current wouldtravel through transistor Q5 and into ground through resistor R3.

Question 3: What is the role of C1 and what would happen if it were absent?

The role of capacitorC1 is to provide a dominant high frequency pole of the op-amp through use of Miller’sEffect. C1 links the output of the first stage to the input of the second stage. Using Miller’s Theorem, C1

can be split into two equivalent capacitances. It can be seen that due to the large gain of the second stage,


the dominant pole will depend on the equivalent capacitance that appears on the input side of stage 2.If C1 were removed from the circuit, the high frequency pole of the op-amp would not have a singleobvious and dominant pole. The cut-off would have to be calculated through the Cπ and Cµ capacitanceswithin the transistors of the op-amp. This is extremely tedious and does not allow the high frequency poleto be designed with ease. C1 is a convenient way to control the high frequency cut-off point.

Question 4: The circuit uses ideal current sources. How would these be implemented in a realcircuit? What differences in performance might be seen as a result? The answer is not finite outputimpedance since the output impedances are already modeled by R11, R12 and R13.

The ideal current sources in the simplified model of the 741 op-amp would be implemented using currentmirrors in the real circuit. Ideal current sources will always produce a current regardless of the operatingpoint of the circuit. In a real circuit, the current mirrors rely on biasing voltages of the transistors, andcopying the currents to the rest of the circuit if the transistors are in the active mode of operation. The firstcurrent mirror uses a negative feedback loop to reduce the current in the 1st stage to equilibrium - whena change occurs. The remaining ideal current sources in the simplified model depend on the first currentmirror being able to supply an appropriate current to the rest of the circuit. If the first current mirror is notactive, the remaining current mirrors which behave as sources to the 2nd and 3rd stage will also be off,essentially turning off the op-amp.

Question 5: What is the purpose of V2 and how would it be implemented in a real circuit?

The purpose of V2 is to create a biasing voltage which keeps transistors Q14 and Q20 in the active region.If the bases of both transistors Q14 and Q20 did not have this additional voltage drop between them, theywould be directly shorted together which would force one of the transistors to be off and the circuit wouldnot work. In a real circuit, V2 would be implemented using two diode connected transistors (shorting thebase to the collector) to produce a constant voltage drop across them and supply a voltage drop of 1.4Vbetween the base of Q14 and Q20.

Question 6: Why are 3 stages used in this op-amp design? Why bother with the third stage if itprovides such a low gain?

The three stages of the 741 op-amp include an input stage, intermediate stage, and output stage. The pur-pose of the input stage includes producing a high differential gain, rejection of the common mode signaland provide a high input impedance. Transistors Q1 and Q2 turn the differential input voltage signal intheir base into a current signal in the collector of Q5 while simultaneously rejecting the common modesignal due to the virtual ground between them. The high input impedance is provided by R11.

The intermediate stage of the amplifier provides a high voltage gain while also serving to control thesingle high frequency cut-off through capacitor C1. This stage contains two NPN transistors cascaded inthe CC-CE configuration which provides the high voltage gain. The capacitor C1 is connected from thebase of Q16 to the collector of Q17. Miller’s Effect is used to control the high frequency cut-off.

The final output stage of the op-amp is required even though it provides a low voltage gain. R6 andR7 (both 30Ω) produce a low output impedance which is desirable for the op-amp. Although the lowvoltage gain, this stage produces a high current gain. Additionally, even though the model in this lab issimplified, in a full 741 op-amp the third and final output stage also includes short-circuit protection as asafety mechanism.


Question 7: What is the DC power consumption of the entire circuit?

The total DC power consumption of the 741 op amp can be calculated by using the currents found in eachbranch from the DC section of the prelab and the corresponding resistances in each branch. Summing theindividual power consumption of each resistor will yield the total DC power consumption of the circuit.Table 2 shows the results of computing the DC power consumption where:

P = I2R,PDC =n∑i

I2i Ri

and n represents the number of resistors in the circuit.

Table 2: DC Power Consumption Data

Component Resistance (Ω) I (µA) Power (µW )R1 1000 10.43 0.109R2 1000 10.43 0.109R3 50000 12.2 7.442

R11 1000000 1.9 3.61R9 50000 13.4 8.798R8 100 686 47.06

R12 30000 127 483.87R6 + R7 60 1142.4 78.305

R10 1000000 2.5 6.25R13 90000 20.2 36.724

TOTAL 672.277

Therefore the total DC power consumption was found to be 672.277µW .


4 SimulationThis section outlines the results produced by the electronic simulation software SPICE.

4.1 Vo − Vd Plot

Figure 18: Vo vs Vd Plot [Zach]

From the plot shown in figure 18 the range of the linear region can be determined. Measured pointsfrom the plot can be found in table 3 to determine this range precisely. The linear regions represents therange for which the output is a linear multiple of the input.

Table 3: Linear Region Data Points

Linear Region Vd(µV ) Vo(V )

Begin 470 4.8724End 530 1.7638

The range of Vd in the linear region spans from 470µV to 530µV for a total range of 60µV .Using data from table 3, the output voltage swing in the linear region can also be calculated. Vo has a totalspan of 4.8724V < Vo < 1.7638V for a total output swing of 3.1086V in the linear region of the responseplot.

The differential gain can be calculated from the Vo vs Vd response. This can be shown by calculatingthe slope of the line constructed by choosing two points from the plot that appear in the linear region.

Aopen =Vo2 − Vo1Vd2 − Vd1

Aopen = −51810


The input offset voltage is the value of Vd required to produce a voltage at the output of 2.5V. Using thecursors, Vd was measured to be 515.65µV when the output was at a value of 2.5006V. Therefore the DCoffset voltage is Vd = 515.65µV .

In the theoretical calculations, the values for the parameters measured were determined to be:

• Output Swing: 1V < swing < 4V

• Aopen = −55065VV

Comparisons: Output SwingThe value calculated before the experiment was determined to be the range 1V < swing < 4V . Themeasured value was found to be 1.7638V < swing < 4.8724V . The theoretical value was calculated byassuming a VCE of 1V to ensure a safe mode of operation for transistors Q14 and Q20. This was a roughestimate, which disregarded the rest of the circuit. Based on the measured values, it is clear that likely dueto biasing in prior stages to the output - the same magnitude of voltage swing was obtained, although theestimation was low by about 0.7V on both ends of the swing. The voltage on the emitters of Q14 and Q20

were estimated by using VCE = 1V - 1V down from the top rail, and 1V up from ground. However, theemitter voltages are determined by the VBE property which helps justify the low estimation error.

Comparisons: Open Loop GainThe open loop gain calculated before the experiment was found to be Aopen = −55065 and the measuredvalue was determined as Aopen = −51810. This yields a 5.9% error between the theoretical and experi-mental data. As stated before - the predetermined value of the open loop gain was expected to be high. Dueto simplifications some accuracy was lost - large parallel resistances being neglected would have loweredequivalent resistances - rounding errors on gain expression at a high level; significant digit truncation atthe lower levels. Additionally the values of β were all assumed - despite the differences in actual β values,the predetermined open loop gain coincidentally evaluated to within a close proximity of the actual valuedetermined in the simulation.


4.2 Common Mode Range Plot

Figure 19: Vo vs Vcm Plot [Zach]

NOTE: Vcm is labeled V5 in schematic.The common mode range can be calculated from the plot of Vo vs Vcm illustrated in figure 19. Thecommon mode range begins when the voltage starts increasing after initially dropping off from 5.0V whenthe sufficient value of Vcm is reached. The common mode range continues through the full range of V5which stops at 5V. Through the DC sweep from 0 to 5V - the common mode range was measured usingthe software’s cursors to be:

1.063V → 5V

In the preliminary calculations, the common mode range was calculated to be 1.6V → 4.4V . The mea-sured data differs slightly from the calculated data with regard to the lower bound of Vcm. The first mainerror observed with this estimation was a large VCE = 1V . A correct value for the lower limit of thecommon mode range would be obtained if the VCE was taken to be 0.5V . The larger voltage was takeninitially as a cautionary move to ensure the transistors were in the active mode of operation. ChoosingVCE = 0.5V is approaching the saturation region - however that is not to say the transistor could still befunctioning as desired.As for the upper bound - the simulation produced an upper limit that approached 5V and would have sur-passed it - if the DC sweep continued past 5V . This is due to the effect of the ideal current source attachedto the emitters of Q1 and Q2. In reality - this would be a real current mirror which would limit the rangeto the top rail before turning off the appropriate transistors. The ideal current source would continue todrive 19µA of current into the first stage. The result of this would be that the op-amp would not want toturn off. Using the current mirror - their purpose is to stop the op-amp from entering a state where too


much current or voltage is supplied at stage 1. Therefore, the upper bound of the common mode range isessentially undetermined.

4.3 Comparison of DC ParametersThis section will compare the values tabulated in the prelab calculations (table 4) with the values measured(table 5) after performing the SPICE simulation.

Table 4: Calculated DC Parameters

Transistor IC(µA) IB(µA) IE(µA) gm(µA/V ) ro(kΩ) rπ(kΩ) β VBE(V )

Q1 (PNP) 10.35 0.1035 10.4535 0.414 1932.38 241.54 100 0.6Q2 (PNP) 10.35 0.1035 10.4535 0.414 1932.38 241.54 100 0.6Q5 (NPN) 10.33 0.1033 10.4333 0.4132 7744.43 242.01 100 0.6Q6 (NPN) 10.33 0.1033 10.4333 0.4132 7744.43 242.01 100 0.6Q7 (NPN) 16.15 0.1615 16.3115 0.646 4953.56 154.80 100 0.6

Q16 (NPN) 20 0.2 20.2 0.8 4000 125.0 100 0.6Q17 (NPN) 679 6.79 685.79 27.16 117.82 3.68 100 0.6Q14 (NPN) 1131 11.31 1142.31 45.24 70.73 2.21 100 0.6462Q20 (PNP) 1131 11.31 1142.31 45.24 17.68 2.21 100 0.6853Q23 (PNP) 198 1.98 199.98 7.92 101.01 12.63 100 0.6

Table 5: Measured DC Parameters

Transistor IC(A) IB(A) IE(A) gm(A/V ) ro(Ω) rπ(Ω) β VBE(V )

Q1 (PNP) 1.03E-05 5.33E-08 1.04E-05 3.99E-04 1.94E+06 4.85E+05 1.94E+02 5.86E-01Q2 (PNP) 1.05E-05 5.44E-08 1.06E-05 4.04E-04 1.90E+06 4.76E+05 1.92E+02 5.86E-01Q5 (NPN) 1.02E-05 1.55E-07 1.04E-05 3.94E-04 7.32E+06 2.02E+05 7.94E+01 5.47E-01Q6 (NPN) 1.02E-05 1.55E-07 1.04E-05 3.94E-04 7.33E+06 2.02E+05 7.95E+01 5.46E-01Q7 (NPN) 1.13E-05 1.36E-07 1.15E-05 4.36E-04 6.91E+06 1.92E+05 8.37E+01 5.48E-01

Q16 (NPN) 1.96E-05 2.58E-07 1.99E-05 7.57E-04 3.97E+06 1.21E+05 9.15E+01 5.62E-01Q17 (NPN) 6.80E-04 5.36E-06 6.85E-04 2.60E-02 1.09E+05 5.61E+03 1.47E+02 6.56E-01Q14 (NPN) 7.57E-04 5.79E-06 7.36E-04 2.89E-02 1.09E+05 5.21E+03 1.51E+02 6.58E-01Q20 (PNP) 7.57E-04 3.86E-06 7.61E-04 2.90E-02 2.71E+04 6.71E+03 1.94E+02 6.96E-01Q23 (PNP) 1.97E-04 1.03E-06 1.98E-04 7.60E-03 1.00E+05 2.51E+04 1.90E+02 6.62E-01

Note: The calculated values are given in convenient units, while the measured values are given in baseunits.


The following figure (20 ) represents the percentage error on the calculated values (table 4) relative tothe simulated values (table 5).

Figure 20: Percent Difference Representation [Zach]

The cells highlighted in yellow represent the component/parameter problem in general. The cells high-lighted in orange are errors related to the value of β. In the case of all rπ values, the value is directlyproportional to β by:

rπ =β

gm

The values of β = 100 assumed in the preliminary calculations, were realistically different as observed inthe simulation. With exception of the transistors highlighted in yellow, it is shown that the values for gmall had negligible error - therefore the mismatching values of rπ can be accounted for by the difference inβ. Another prime example - note the value of rπ for transistor Q16, is very close to the theoretical valuebecause the simulated value of β was reasonably close to 100.

The values of IB were highlighted in orange because of their high error and inversely proportional re-lationship to β:

IB =ICβ

Differences in β measured in the simulation account for the corresponding shifts in the values of IB. Thisis due to the small errors in IC which match the theoretical calculations with the exception of the transistorshighlighted in yellow.


The original calculated values were then re-evaluated using the appropriate β values and the followingresults are shown in table 6.

Table 6: Re-calculated Values Using Simulated Results

Transistor IC(µA) IB(µA) IE(µA) gm(µA/V ) ro(kΩ) rπ(kΩ) β VBE(V )

Q1 (PNP) 10.35 0.05 10.4535 0.414 1932.38 468.60 1.94E+02 5.86E-01Q2 (PNP) 10.35 0.05 10.4535 0.414 1932.38 463.77 1.92E+02 5.86E-01Q5 (NPN) 10.33 0.13 10.4333 0.4132 7744.43 192.16 7.94E+01 5.47E-01Q6 (NPN) 10.33 0.13 10.4333 0.4132 7744.43 192.40 7.95E+01 5.46E-01Q7 (NPN) 16.15 0.19 16.3115 0.646 4953.56 129.57 8.37E+01 5.48E-01

Q16 (NPN) 20 0.22 20.2 0.8 4000 114.36 9.15E+01 5.62E-01Q17 (NPN) 679 4.62 685.79 27.16 117.82 5.41 1.47E+02 6.56E-01Q14 (NPN) 1131 7.49 1142.31 45.24 70.73 3.34 1.51E+02 6.58E-01Q20 (PNP) 1131 5.83 1142.31 45.24 17.68 4.29 1.94E+02 6.96E-01Q23 (PNP) 198 1.04 199.98 7.92 101.01 23.99 1.90E+02 6.62E-01

Now, if these recalculated values are compared with the measured data, the results are much more accurate- eliminating the assumed β values. This can be seen in figure 21.

Figure 21: New Percent Difference [Zach]

The remaining three transistors that appear to have a high percent difference compared to the simulateddata are a result of calculation error in the preliminary calculations. There were discrepancies on how todetermine the correct currents involving the transistor Q7. As mentioned before - it caused a contradictionof IC , IB and IE . Unfortunately at this point there is nothing that can fix the pre-determined values withoutrecalculating the entire DC section.

Q14 and Q20 had an assumption that the amount of current flowing into the resistor R10 was zero, tosolve for their emitter currents. This could be a potential sources of error. Since IC is a function of IE -if the current through R10 had not been neglected it would likely reduce the difference between the calcu-lated value, and the value determined by the simulation. Essentially, anywhere there was an assumption


made - a noticeable error was produced.

4.4 Revised Gain CalculationsUsing the gain equations found in the AC calculations section - using the simulated values, the gain ofeach stage was recalculated.First Stage Gain:

Av1 = gm2(RL1||ro6||ro2) = 282.63

Where:RL1 = Rin2 = rπ16 + (β16 + 1)[R9||(rπ17 + (β17 + 1)(R8))] = 1.304MΩ

Second Stage Gain:

Av2 = −(

ro16||R9||(rπ17 + (β17 + 1)R8)

ro16||R9||(rπ17 + (β17 + 1)R8) + re16

)gm17(RL2||R12)

1 + r8gm17 + R8

rπ17

= −197.69

Where:

RL2 = Rin3 = rπ23+(β23+1)[(β23+1)R10+(rπ14+(β14+1)R6)||(rπ20+(β20+1)R7)||(β23+1)R13] = 36GΩ

Therefore it can be ignored as it was previously.Third Stage Gain:

Av3 =

(R10

R10 + (re20 +R7)||(re14 +R6)

)((β23 + 1)[R10 + (re14 +R6)||(re20 +R7)||R13]

re23 + (β23 + 1)[R10 + (re14 +R6)||(re20 +R7)||R13]

)≈ 1

The overall revised gain calculation was then calculated to be:

Av = Av1 · Av2 · Av3Av = −55856

A summary of the calculations can be seen in table 10. This shows that the assumptions (for the values)

Table 7: Revised Gain Calculation Summary

Stage Pre-lab RevisedAv1 281.85 282.63Av2 -195.37 -197.63Av3 1 1Av -55065.03 -55856

made in the pre-calculations were reasonable. However, this does not mean that the gain is perfectly cor-rected to match the simulation output for the gain value. This is because, even though the revised gaincalculations were evaluated with the measured values - the equations used are still derived using assump-tions and therefore any misalignment’s encountered by the prelab calculations would have propagatedthrough to the revised calculations.


5 Results and AnalysisThis section will outline the findings and summarize the analysis process.

5.1 Frequency Response and Bode Plot

Figure 22: Frequency Response and Bode Plot of 741 [Zach]

Figure 22 demonstrates the differential magnitude and phase response of the simulated 741 op-ampfrom 1Hz to 10MHz with the input voltage set to unity.

Looking at the phase response (top portion) it is observed that at low frequencies the phase response of theop-amp is 180 degrees, in the mid-band frequencies (300Hz to 300kHz) the phase response is shifted byapproximately 90 degrees. Past the unity gain frequency of 1Mhz the phase response reduces to 0 degreesfor a total phase shift of 180 degrees from the value at low frequencies (phase inversion). This is expectedas past the unity gain frequency a phase inversion should appear (negative in the Av expression). If thephase inverted before the unity gain frequency, problems would arise when connecting the 741 op-amp ina feedback configuration due to the positive feedback that would occur from the positive gain. Once thegain is below unity the 180 phase inversion will not result in positive feedback.

Looking at the magnitude response (bottom portion) it is observed that a linear roll off occurs as frequencyincreases and eventually reaches the unity gain frequency (0dB) at a value of approximately 1Mhz. Theunity gain frequency fu is determined by the value of capacitor C1 which dominates the high frequencypole as discussed in the Theory and Design Questions. Using the cursors to measure this value precisely,fu was determined to be:

fu = 925.85kHz


5.2 Calculated fu vs Simulated fuThis frequency is slightly lower than the desired frequency of 1 MHz. In the lab, the value of C1 used inthe SPICE simulation was 69.6pF due to a calculation error before the simulation. As discussed in theTheory and Design section, the correct theoretical value for C1 was determined to actually be 41.3pF .Despite using a high value in the simulation for C1, if the proper theoretical calculation of 41.3pF wasused, the correct value of fu = 1Mhz would not have necessarily been produced. The equation for C1

used the values of A0, Rout1 and Rin2 which were all calculated using approximations, increasing theirvalues slightly when compared to the values determined in simulation. The calculated value of C1 wasinversely proportional to these values and in reality the decrease of the real values would have an increasein the effective value of C1. Therefore the value of C1 which would produce exactly 1Mhz unity gainfrequency would be somewhere below the value used in the simulation of 69.6pF (high) and above thecorrect theoretical value of 41.3pF (low) due to the inversely proportional relationship of fu and C1. Insummation, the correct value for C1 that would produce a unity gain frequency of 1Mhz lies in the range:

41.3pF < C1 < 69.6pF

5.3 Slew Rate Plot

Figure 23: Slew Rate Plot of 741 [Zach]

Figure 23 shows both the input (in blue) and transient response (in red) of the 741 op-amp in theunity-gain voltage follower configuration. The positive and negative slew rate are measurements of themaximum rate of change in the output voltage in response to a square wave input changing between 1Vand 4V. The values measured using the cursor to determine the positive and negative slew rate can befound in table 8 below: The slew rate is determined as the slope of the line in the positive increase and


Table 8: Positive and Negative Slew Rate Data

Time (µs) Vo (V)Positive Slew Rate: 2.4136 1.874

7.7395 3.4207Negative Slew Rate: 26.053 3.7383

32.589 1.8632

negative decrease region:

SR+ =3.4207V − 1.874V

7.7395µs− 2.4136µs= 0.2904

V

µs

SR− =1.8632V − 3.7383V

32.589µs− 26.053µs= −0.2869

V

µs

The theoretical value of slew rate determined in the Theory and Design section was:

SR = ±0.4601V

µs

This theoretical value is high compared to what was measured. This is because the theoretical value ofthe slew rate was calculated using the correct theoretical value of C1 - which was not actually used duringsimulation. In the simulation the value of C1 was incorrectly set to 69.6pF due to a calculation error whichhas a direct effect on the slew rate calculation. Recalculating the theoretical slew rate using the simulatedvalue of C1 produces a slew rate much closer to the measured values:

SRnew =I1

C1actual

=19µA

69.6pF= 0.2730

V

µs

This new theoretical value is much closer to what was measured in the simulation for both the positiveand negative slew rate with errors of 6.4% and 5% respectively. The reason these values do not matchexactly is due to the theoretical calculation determining the maximum slew rate and the measured valueswere taken using a location for where the slew rate appeared to have the maximum slope on the responseplot. If the data points were taken at the true values of where the maximum slopes occurred, they wouldin theory be even closer to what was predicted.

6 ConclusionThis report aimed to provide the the characteristics and parameters of the simplified 741 op-amp. TheDC analysis showed the internal workings of the circuit to provide the expected behaviour of the op-amp.Through the AC calculations the characteristics of the op-amp were observed and extracted.

The main purpose of the DC calculations were to observe the state at which each transistor was operatingand the characteristic values that help show each transistor’s function. The parameters extracted for eachtransistor were: terminal currents in the base, emitter and collector - gm - the internal resistances ro and rπ.

The AC calculations highlight the three main stages of the op-amp. The first stage serves as a differ-ential voltage amplifier which provides the largest gain of all three stages. Stage 2 serves as a voltage


amplifier - essentially its main purpose is to boost the gain of the overall circuit. The output stage doesnot provide any additional voltage gain. It provides a low output drive to serve as a current gain stage. Ina real 741, all of these stages are surrounded by fail safe components including current mirrors and shortcircuit protection - most of which were removed for the purposes of this experiment. A summary of theresults can be seen below in table 9.

Table 9: Gain Summary

Stage Pre-lab Revised SimulationAv1 281.85 282.63 -Av2 -195.37 -197.63 -Av3 1 1 -Av -55065.03 -55856 -51810

The open loop gain of the op-amp was determined as a result of the individual gains from stage 1-3. Thisvalue was determined to be roughly -55065. This approximate value was found to be reasonable throughthe logical assumptions mentioned in the open loop gain section.

A common mode range was simulated to give a result from 1.063V → 5V but for the same reasonsmentioned before - this upper bound is likely high due to the ideal current source always driving a currentinto the input stage when realistically at some point it would shut off.

The measured output swing ranged from 1.7638 → 4.8724V . This was shifted 0.7V higher than theexpected value determined beforehand. Although the range was roughly the same magnitude.

After sorting out the slew rate calculations - finding the slew rate using the theoretical value of the capaci-tor that was used in simulated compared very accurately with the measured slew rate of SR+ = 0.2904 V

µs

and SR− = −0.2869 Vµs

.

The overall power consumption of the op-amp used in the simulation was determind to be 672.28µW .

The DC parameters were measured and compared with the theoretical values. The discrepancies wereanalyzed, and the measured values were used to obtain revised calculations to see if again the theoreti-cal expressions could better match the simulation. Many of the errors encountered were a results of thesimulated values being much different than the assumed values for the first round of theoretical calcula-tions. Any errors that were not fixed were supplemented with a discussion of why they are possibly stillincorrect.


Again, using the simulated values - the gain expressions were then re-evaluated and compared to seethe contrast between the theoretical values and simulation. The frequency response and body plot were

Table 10: Revised Gain Calculation Summary

Stage Pre-lab RevisedAv1 281.85 282.63Av2 -195.37 -197.63Av3 1 1Av -55065.03 -55856

discussed along with reasons as to why the desired unity gain frequency was not achieved in simulation.There were errors concerning the correct theoretical value of the capacitor that should have been obtained- while a different capacitor value was actually used in simulation. However the discussion shows thecontrast between the ideal and actual scenarios for each capacitor value.

Lastly, the slew rate of the op-amp was determined using the slew rate plot obtained from the simula-tion. The values of the positive and negative slew rates were found to be:

SR+ = 0.2904V

µs

SR− = −0.2869V

µs

Overall, the theoretical expressions used to analyze the circuit used in the simulation provided reasonableresults - given large assumptions for important values (β, VBE) and minimal human error in derivingexpressions.

References[1] ELEC 3509 Manual F2014. Ottawa: Carleton University, 2014. 9. Web. 17 Nov. 2014


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