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ELEC-E3550Integrated RF circuits
Spring 2017Spring 2017
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Topics of the previous lecture
Concepts related to mixers”mixing” = multiplication in time-domain = frequency shift in frequency domainConversion gain, SSB / DSB NF, IIP2 / IIP3, ICP, isolation
Active mixersCascode amplifier
Active mixer Active mixer Single-balanced mixer
Double-balanced mixerGilbert cell mixer
Passive mixersVoltage-mode passive mixer
Current-mode passive mixer
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Frequency Synthesizers (SX)Channel
• System level & concepts• SX principles
0
A D
Pre-select
Channel select
I
• Phase-locked loop• ”theory” / CP-PLL / ADPLL
0 90
A D
LO
Q Break
• Oscillators• Ring & LC
• Frequency dividersD
AI
Break
• Frequency dividers• Quadrature generation
90o
DAQ Break
Exercises & HomeworkD Break
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
SX Requirements
LO phase noise
spurious tones
fLO
harmonics
fLO
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
SX Requirements
LO phase noise
spurious tones
fLO
harmonics
• Frequency span --- cover the required bandwidth + margin for PVT
fLO
• Channel spacing & settling time• Phase noise • IQ-generation --- Amplitude and phase imbalance (IRR)• IQ-generation --- Amplitude and phase imbalance (IRR)
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Impact of Phase Noise
Phase noise impacts
LOInterferer Down-
ConversionQ
Phase noise impactsIQ-constellation Reciprocal mixing
signal
Conversion
I
In TX, phase noise causes out-of-band spurious emission. In TX, phase noise causes out-of-band spurious emission.
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Impact of Phase Noise
Phase noise impacts
LOInterferer Down-
ConversionQ
Phase noise impactsIQ-constellation Reciprocal mixing
signal
Conversion
I
In TX, phase noise causes out-of-band spurious emission.
Phase noise requirement depends on:• Channel spacing• Modulation method (eg. compare QAM-16 vs. QAM-256)
In TX, phase noise causes out-of-band spurious emission.
• Modulation method (eg. compare QAM-16 vs. QAM-256)• Required sensitivity and selectivity• Specified environment (”hostile” / ”friendly”)• TX: emission mask
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Phase Noise SpecificationsPhase noise specification for SX given either by Phase noise specification for SX given either by • N/C at certain offset, e.g N/C@1 MHz < -120 dBc/Hz• Integrated N/C profile can be then converted to jitter spec
System Band [MHz]
Ch. spacing [kHz]
N/C [dBc/Hz]@kHz
norm-N/C* [dBc/Hz]
IS54 824-849 30 -115@60 -132
GSM 880-915 200 -141@3000 -125GSM 880-915 200 -141@3000 -125
DECT 1880-1900 1728 -97@1800 -91
WCDMA 1920-1980 5000 -129@8000 -111
WLAN (b) 2400-2483.5 22000 -103@1000 -105WLAN (b) 2400-2483.5 22000 -103@1000 -105
BlueTooth 2400-2483.5 1000 -109@1000 -111
GPS 1575.42 - -95@1000 -93
DOCSIS** 47-862 6000 -82@10 -100DOCSIS** 47-862 6000 -82@10 -100
DVB-S 10700-12750 fixed LO1 -95@100 -131
* Normalized to 2GHz and 1MHz, N/C~(fo/fm)2 **data over cable-TV
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
IQ ImbalanceHartley Receiver DCR
LNA
LO_I
LNA
LO_I
A D
Hartley Receiver DCR
LNA
LO_Q
LNA
LO_Q
A D
• LO signals (I) and (Q): equal amplitude (A) and 90-degree phase shift ( )• LO signals (I) and (Q): equal amplitude (A) and 90-degree phase shift ( )• A and results in imperfect image rejection or reduced SNR for DRC• Every signal path element contribute to IRR, but usually LO imperfections dominate• Image-Reject Ratio (IRR) is a measure of LO signal imbalance • Image-Reject Ratio (IRR) is a measure of LO signal imbalance
2
21 2 cos1 2 cos
bal bal
bal bal
A AIRR
A A1 2 cosbal balA A
• Typically DCRs need IRR > 30 dB Abal < 0.5 dB and < 4°• LO chain often includes limiting amplifiers phase error remains a challenge
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Frequency Synthesis Methods
1. Direct analog synthesis
2. Direct digital synthesis ”DDS”
”DAS”
2. Direct digital synthesis
3. Indirect digital synthesis
”DDS”
3. Indirect digital synthesis
4. Indirect analog synthesis”PLL”
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Direct Analog Synthesis (DAS)
……sw
sw
sw
f1
witch
witch
witch
f2f3f4
h h h
• Filters are filter banks and/or tunable filters• Amplifiers not drawn
Main problem for RF IC implementation: good filters can not be integrated.
• Amplifiers not drawn• Chain may include dividers as well
Main problem for RF IC implementation: good filters can not be integrated.
DAS is in use e.g. in measurement instruments – High perf, high price
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Direct Analog SynthesisAt RF IC context we may use simplified versions of DAS.At RF IC context we may use simplified versions of DAS.
”Manipulate a frequency tone with basic mathematical operators” - addition mixer- substraction mixer- substraction mixer- division frequency divider- multiplication frequency doubler / tripler
Band 1Band 1
Band 2
Band 3
/ N1
/ N VCOFractional-N
PLL
Band 3
Band 4
/ N2
Band 5 / N3 N4
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Direct Digital Synthesis (DDS)
Phase Accumulatordata ROM D/A
time-sampledphase
time-sampledamplitude
analogsignal
Accumulator
clock
data ROM D/A
Problems: Problems: needs a high-speed D/Aneeds fclock > 3* fout
DDS is used in base stations and LF radios (e.g. military)DDS is used in base stations and LF radios (e.g. military)Enables very complex modulations (military)
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Indirect FS -- Phase-Locked Loop
VCO PDfRef fout
Basic idea is to lock the oscillator into the incoming signal using a feedback loop.Compare to: feedback amplifier analysis in electronics
feedback systems in control theory and automationfeedback systems in control theory and automation
VCO PDfRef fout
1/N1/N
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Some Books on PLL’s
• Many basic text books on RF/analog IC electronics include a chapter on PLLs– Razavi: RF Microelectronics, – Lee: The Design of CMOS RF IC, – Lee: The Design of CMOS RF IC, – Grebene: Bipolar and MOS Analog IC Desing, etc.
• U. Rohde: many books on PLL’s, not RF IC oriented• F. Gardner: Phaselock Techniques • F. Gardner: Phaselock Techniques • R. Best: Phase-Locked Loops: design, simulation and applications • J. Crawford: Frequency Synthesizer Design Handbook• D. Wolaver: Phase-Locked Loop Circuit Design• D. Wolaver: Phase-Locked Loop Circuit Design• C. Vaucher: Architectures for RF Frequency Synthesizers • D. Banerjee: PLL Performance, Simulation and Design (wireless.national.com) • ... and many more• ... and many more
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Typical Results of Linear Analysis
VCOspur
C/Nphase noise
PLL
spur
log
PLL performs a high-pass filtering for the phase-error flat in-band noise
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Integer-N PLL:Fractional-N Concept
• reference frequency = channel spacing• if N is very large
• stability requires loop-BW < fref/10 loop-BW small long settling time & poor phase noise reduction at high offsetlong settling time & poor phase noise reduction at high offset
• ref. source & PD noise is multiplied by N • Recall: GSM1800 ch. spacing=200 kHz, N~10000
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Integer-N PLL:Fractional-N Concept
• reference frequency = channel spacing• if N is very large
• stability requires loop-BW < fref/10 loop-BW small long settling time & poor phase noise reduction at high offsetlong settling time & poor phase noise reduction at high offset
• ref. source & PD noise is multiplied by N • Recall: GSM1800 ch. spacing=200 kHz, N~10000
Basic integer-N PLL is not good for small channel-spaced systemsBasic integer-N PLL is not good for small channel-spaced systemsImprovments on PLL architecture (mixers in loop, dual-loop, frac-N PLL)
Dual-modulus divider fTfTDual-modulus divider
111
1
f
fN
fTT
TNf
TTT
outin
BA
Bin
BA
A
fin fout
)1(
111
NT
TTNT
TTNff
B
BA
A
BAeffin
out
TA TB
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Fractional-N Concept
• With the aid of dual-modulus divider division ratio can be set to N...N+1Example: TA/(TA+TB)=90%, TB/(TA+TB)=10% and N=100 => Neff 100.1
Frac-N PLL provides small channel step and still large loop-BW.Frac-N PLL provides small channel step and still large loop-BW.
• Main problem : ”fractional spurs” Can be partly compensated by randomizing the timingCan be partly compensated by randomizing the timingand using noise shaping.
(for details, Razavi presents an easy-to-read presentation in RF Microelectronics)
• Frac-N PLL requires more hardware and suffers from high spurios content• Frac-N PLL requires more hardware and suffers from high spurios contentand increased noise level compared to int-N PLL.
use only when integer-N is not feasible.
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Charge-Pump PLL
VCOLoop FilterPhase-Frequency
Detector
Charge Pump
UP
PFD fOUT
Loop FilterDetector
fREF
UP
DW
1/N11/N2 1/N11/N2
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
)cos()()sin()( tVtvandtVtv
Phase Detector
1) Analog multiplier (mixer)
K depends on input signal level, not good !
)2sin()sin(
)cos()()sin()(
2121
2121
2211
tVVVVKVtVtvandtVtv
mD
KD depends on input signal level, not good !
If mixer inputs are overdriven, outputs saturates into ”0” or ”1”This is equivalent to drive a XOR gate with squarewaves.This is equivalent to drive a XOR gate with squarewaves.
2) Digital comparator (XOR gate)- performs essentially the same function as analog multiplier
These circuits do not provide frequency information: PD can not distiguish whether in> out or in< out : this is called ”self acquisition”A small DC component in the error signal guides the loop.Therefore, it takes a relatively long time for the loop to settle.Therefore, it takes a relatively long time for the loop to settle.
we need a phase-frequency detector
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Phase - Frequency Detector
• also called ”tri-state phase detector”• also called ”tri-state phase detector”• two D-flipflops and AND-gate• Delay element is used to avoid ”dead-zone” problem.
+ edge-trigged circuit duty-cycles of the inputs 50% OK
+ Frequency steering
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Charge Pump
Up/Dn control pulses from PFD are driving a buffer stage.• Three basic configurations• Key challenges:
• Linear response ( time – charge )
UP
DN • Linear response ( time – charge )• Matching of IUP / IDW
DN
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
CP creates an additional pole into transfer function loop becomes potentially unstable
Loop Filter
loop becomes potentially unstableR has to be added for stability, and another C for attenuating ripple.
Active filter+ Can provide DC gain: additional design freedom+ (partial) remedy for charge leakage+ Not resiprocical suppress VCO feedthrough+ Not resiprocical suppress VCO feedthrough- Higher noise, higher component count & power
Oscillator and divider will be discussed in detail later.
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Impact of Technology EvolutionRecall our earlier paradigm changes, e.g.• GaAs MESFET Si Bipolar CMOS• Superheterodyne receiver DCR• Monolithic capacitors: vertical field lateral field• Gilbert cell mixer current-mode passive mixer
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Impact of Technology EvolutionRecall our earlier paradigm changes, e.g.• GaAs MESFET Si Bipolar CMOS• Superheterodyne receiver DCR• Monolithic capacitors: vertical field lateral field
“Simple PD” (mixer)PLL
• Gilbert cell mixer current-mode passive mixer
PLL
Charge-pumpPLL
All-digitalPLL
1990 2000 20101990 2000 2010
“In a highly-scaled CMOS technology, time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals”
R. Bogdan StaszewskiManager of
TI’s DRP group
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
All-Digital PLL
DCO
TDCfOUT
DCOLoop Filter Dither
fREF
FCW Tune
1/N
• Frequency control word (FCW) defines the target frequency• Time-to-Digital converter (TDC) describes the output frequency with a digital word• Error signal (digital) is filtered in the digital loop filter • Error signal (digital) is filtered in the digital loop filter • Digital-controlled oscillator (DCO) is tuned accordingly• Dithering (compare to frac-N principle) is used to achieve fine frequency step• Prescaler used to lower fout (only if needed!) (65-nm CMOS: TDC fmax~1.7 GHz)
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
10 minutes break 10 minutes break
OscillatorsOscillatorsDividersIQ generation
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Oscillators
Oscillator is an autonomous device which generates a waveformOscillator is an autonomous device which generates a waveformIt converts power from DC to ”AC”
Variable frequency oscillator converts a control signal into frequencyVariable frequency oscillator converts a control signal into frequencyinformation is converted from one mode to another
• VCO – voltage-controlled oscillator• ICO – current-controlled oscillator• ICO – current-controlled oscillator• DCO – digitally controlled oscillator
Oscillator waveform can beOscillator waveform can be• Sinusoidal : low level of higher harmonics• Square : high level of higher harmonics, ”clock signal”
• ramp or triangular is used at LF control circuits
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Oscillator Classification
oscillation mode oscillator structure
• Stable (no oscillation)• Harmonic (sinusoidal)
• Phase shift (RC)• Gm-C
• Harmonic (sinusoidal)• Relaxation• Chaotic
• Gm-C• Crystal• MultivibratorNo correlation !!
• Ring • LC
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Oscillator Terms and Figures of Merit • Tuning Range : ratio of maximum and minimum oscillation frequency• Tuning Range : ratio of maximum and minimum oscillation frequency• VCO gain (KVCO) and its deviation (linearity)• Output power (preferably constant)• supply voltage / current consumption / power efficiency• supply voltage / current consumption / power efficiency• Distortion in ”sinusoidal” oscillators• Temperature stability ( freq/ T)• Pushing (PSRR) ( freq/ supply)• Pushing (PSRR) ( freq/ supply)• Pulling (load) : Frequency shift caused by load impedace variation• Pulling (injection) : Frequency shift caused by external disturbance• Phase Noise / Jitter• Phase Noise / Jitter• Die Area (IC implementation) / Component count (discreate circuits)
RangeTuningnconsumptioPowerNoisePhase
RangeTuningFOM
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Ring Oscillator
0 1 0 11 0 1 00 1 0 10 1 0 1
Nfosc 2
1
NCIf
IC
loadosc
load
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Ring Oscillator
0 1 0 11 0 1 00 1 0 1 Real implementation is differential and
simple cross-coupling creates proper fb.0 1 0 1 simple cross-coupling creates proper fb.
+ can be transistor-only circuit small areaN
fosc 21
small area+ Easy to tune, large tuning range
power cons. is relative to freq.(although follows technology-nodes)
NCIf
IC
loadosc
load
(although follows technology-nodes)moderate (poor) phase noise
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
LC Oscillator
Gloss Gneg0
1osc
GGLC
Is negative resistor a plausible device at all?
0negloss GG
Is negative resistor a plausible device at all?
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
LC Oscillator
Gloss Gneg0
1osc
GGLC
Is negative resistor a plausible device at all?
0negloss GG
Is negative resistor a plausible device at all?
Transconductor in unity feedback Gunn diode
voutI
)( outm
outin vg
vR
i=gm vinvin
-vout
V
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Negative Conductance : Unity Feedback (most of modern RFIC VCOs use these)
• Cross-coupled pair (CCP) : NMOS / PMOS / CMOS• Biasing : top / bottom / none• Biasing : top / bottom / none• Advanced techniques like noise filtering
Really many different topologies exist
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
NMOS CCP Biasing
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
CMOS Cross-Coupled Pair
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Negative conductance : reactive feedbackZinZin
Vbias
C
1mgZ
nmos = gm and Vbias–node is signal ground
Vbias
C
222
1C
min jC
gZVbias
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Negative conductance : reactive feedbackZinZin
Vbias
C
1mgZ
nmos = gm and Vbias–node is signal ground
Vbias LjRC
222
1C
min jC
gZVbias LjRcoil
Add a coil oscillator
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Negative conductance : reactive feedbackZinZin
Vbias
C
1mgZ
nmos = gm and Vbias–node is signal ground
Vbias LjRC
222
1C
min jC
gZVbias LjRcoil
Add a coil oscillator
Some Classical Oscillators
bias bias
MEISSNER ARMSTRONG HARTLEY COLPITTS
CLAPP MILLER
bias bias
bias
bias
bias
bias
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Linear Analysis Methods
B(s)
A(s)1) Loop-Gain
180)()(1)()(
oscosc
oscosc
jBjAjBjA
B(s)
0)()( 00 LG RRR
2) Negative-Resistance
oscosc
ZG ZL0)()(
0)()(
00
00
LG
LG
XXXRRR
3) Nodal EquationSee details:L. Larson : RF and microwave circuitdesign for wireless communications
0
000
YIM
YREYVY
design for wireless communications
in each case you get two equationsone for fosc and second for -gm
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Example: Common-Drain Colpitts
RC1
C2L
Yin
g (V -V )Yo
V2V1
GL
C1
2L gm(V1-V2)YoGL
1
Vb C2
01)(
1
211
11
moinmin
inLin
gYR
YCCjgCjY
CjYGCjYLj
moL
CCC
ggR
G
CCC
)1(1 inLo
inm CC
CC
CCGgRC
CCg 211 2)1(in
in
in CCCCCC
CCCL 12
21
12 inLom CCC
GgRC
g122
2)(
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Oscillator Simulations1) Small-signal analysis : loop-gain or neg-res method (AC or S-par analysis)1) Small-signal analysis : loop-gain or neg-res method (AC or S-par analysis)
rough estimation for fosc and adequate gain- NOT ACCURATE due to various large-signal phenomena
2) Time-domain analysis (TRAN) Oscillation frequency and amplitude2) Time-domain analysis (TRAN) Oscillation frequency and amplitude• You need a time-varying element for oscillation build-up
(eg. exp. incr. supply, init current in coil)• Use constant time-step• Use high precision settings
.option HMIN=2p HMAX=2p eps=0.1u reltol=1u
Vprobe drain1 drain2 probe• Use high precision settings
- Sweeps toilsome in some simulators- No noise analysis / analysis really heavy
3) Harmonic Balance (SST, ”steady-state” sim.)
Vprobe drain1 drain2 probe
.sst oscil nharm=10 fund_osc=3G
.extract fsst label=taajuus fund_osc
.extract fsst label=Voscpp yval(vm(drain1), fund_osc)
.sstnoise v(drain1) harm (1) dec 10 1k 10e63) Harmonic Balance (SST, ”steady-state” sim.)gives oscillation frequency and amplitudePhase noise analysis
+ Results readily in frequency domain+ Easy to sweep parameters and analyze results
.sstnoise v(drain1) harm (1) dec 10 1k 10e6*.plot sstnoise db(phnoise).extract sstnoise label=N/C@10k yval(db(phnoise), 1e4).extract sstnoise label=N/C@1M yval(db(phnoise), 1e6)
+ Easy to sweep parameters and analyze results- Not available in all softwares, may include flaws- Not a general simulation, you can not simulate everything with SST
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Remainder: Monolithic CoilsVery important for RF ICs Self-learning assignment
H
Very important for RF ICs Self-learning assignment
i i
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Remainder: VaractorsInversion-mode PMOS Inversion-mode NMOS
N-well
G
Inversion-mode NMOS
G
N-wellP-type substrate
G
N-type accumulation-MOS
P-type substrate
G
P-type accumulation-MOS
N-wellP-type substrate
G
N-isoP-type substrate
G
P-well
P-type substrate P-type substrate
• Four types are available, inversion-mode are “ordinary” MOSFETs• Quality factor and tuning range (Cmax/Cmin) are competing properties • Quality factor and tuning range (Cmax/Cmin) are competing properties • Typ. Q~50 at 2 GHz and TR~3• Process variation tracks to MOSFET variation
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Coarse tuning with SC-network• Large VCO tuning range ( high Kvco) is needed to compensate PVT variations.• Large VCO tuning range ( high Kvco) is needed to compensate PVT variations.• High Kvco means that oscillator is noisy, and it also causes problems in PLL design.• How to implement large tuning range with small Kvco ?
switched-capacitor network for coarse tuningswitched-capacitor network for coarse tuning
10
8.5
9
9.5
Freq
tune
7
7.5
8
Freq [GHz]
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 16
6.5
Tuning voltage [V]
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Oscillator Phase NoiseIntuitive approach : ”noise mixing”Intuitive approach : ”noise mixing”• Oscillator is a nonlinear circuit• oscillation swing is ”internal LO”• noise (int. & ext.) is mixed into carrier
noisen
• noise (int. & ext.) is mixed into carrier• fb-loop performs filtering
Intuitive approach II : ”Frequency modulation”
"LO"
Intuitive approach II : ”Frequency modulation”• Oscillator is a VCO & ICO• noise is modulating the oscillator frequency
VCO ICO
n- n
ttKVAtAtv mmm
VCOmosc )cos()cos(
2cos)( 000
Narrowband FMapproximation
Low phase noiseMinimize nonlinearityMinimize KVCO and other sensitivities
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Oscillator Phase Noise Consider ideal parallel LCR-type oscillator with noiseless Gneg.neg
There are losses in the resonator and corresponding noise source is
Impedance of the LC-tank
kTGf
in 42
00 )( LjZImpedance of the LC-tank
Tank quality factor
We have
0
02
)( jZ
QGL
LGQ
00
11
1We have
Noise voltage is
0
00
00 2
1
2)(
QGQGZ
20222
214Q
kTRZf
if
v nnNoise voltage is
This is both amplitude and phase noise. Oscillator performs amplitude clipping no amplitude noise. Thus, divide above by two. Also recall
2Qff
RPv sigsig2
Noise-to-carrier ratio is
20
212/QP
kTCNsig
Low phase noiseMaximize Psig and Q
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Leeson’s Phase Noise Model
-80
-70
-110
-100
-90
-80
C/N[dBc/Hz]
-30 dB/dec
-20 dB/dec
-140
-130
-120
-110 -20 dB/dec
noise floor
cfQP
FkT 1)21(12log10 20L
10 100 1000 10000-140
Frequency [kHz]
sig QP1)
2(1log10L
Heurestical model (based on experiments) • fc is 1/f-noise corner close-in noise f is not the same as device’s 1/f-corner• fc is 1/f-noise corner close-in noise • constant term ”1” is included to describe the noise floor
• F is for additional noise due to –gm
fc is not the same as device’s 1/f-cornerF is difficult to estimate a prioriBased on linear time-invariant model
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Frequency DividersFrom RF designer’s point of view there are two types of logic: dynamic & static
Static logic (SCL = source-coupled logic) • devices have constant bias (no saturation)
Dynamic logic: • transistors operate as switches
From RF designer’s point of view there are two types of logic: dynamic & static
2
• devices have constant bias (no saturation)• no speed limitation (as with dyn. logic)• power – frequency dependency weaker• differential signals (dyn. logic single-ended)
Better immunity to noise, glitches etc.
• transistors operate as switches• many logic families • on/off switching limited speed • power consumption is related to speed :
CVfP ddDC2 Better immunity to noise, glitches etc.
• speed scales with the technology.• power consumption scales with the technology
There is a frequency limit, set by the limited speed of dynamic logic or increased power consumption, where static logic becomes superior.With 65-nm CMOS this limit is in range of 2-3 GHz, in 28-nm at 5-7 GHz.
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
SCL D-flipflop divider
• D-flipflop in unity feedback is a divide-by-two circuit • D-flipflop in unity feedback is a divide-by-two circuit • D-flipflop consists of two D-latches
• resistor
Q
• resistor• PMOS• inductor
D-latchD Q
DX QX CLK
D-latchD Q
DX QX CLK
foutD
CLK CLK
DFFfin
CLK
TRACK HOLD
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Divider ChainsAsynchronous chain • Power consumptionAsynchronous chainDivide by 2N D Q
DFF
QX D Q
DFF
QX D Q
DFF
QX
• Power consumptionlower after each division
• Higher noise (jitter)
Johnson counterDivide by 2N
D Q
DFF
QX D Q
DFF
QX D Q
DFF
QX D Q
DFF
QX • Each DFF runs at fin
higher power cons.• smaller noise (jitter)
modulusDiv-2/3 Div-3/4
Dual-modulusDFF DFF
in
out
DFF DFF
modulus ctrl
Dual-modulusdividers
modulus ctrl
in
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
IQ Generation
APre-
Channel select
I Four LO signals needed:
0 90
A D
A
Pre-select
LO
I Four LO signals needed:0° / 90° / 180° / 270°
IQ amplitude and phase balance (IRR) very important.A
D Q balance (IRR) very important.
1. RC phase shifters polyphase RC filter2. Divide-by-two circuit3. Quadrature oscillators3. Quadrature oscillators
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
RC Phase Shiftersvin Ip ( 0 deg) RC-CR networkvin
vinI QQp ( 90 deg)
Im ( 180 deg)
Qm ( 270 deg)
Ip ( 0 deg)
• Narrow bandwidth• Sensitive to process spread• Post-tuning possible• Clipping amplifier helps
RC-CR network
Im ( 180 deg)
constant IQ phase balance constant IQ amplitude balance
• Clipping amplifier helps
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
RC Phase Shiftersvin Ip ( 0 deg) RC-CR networkvin
vinI QQp ( 90 deg)
Im ( 180 deg)
Qm ( 270 deg)
Ip ( 0 deg)
• Narrow bandwidth• Sensitive to process spread• Post-tuning possible• Clipping amplifier helps
RC-CR network
Im ( 180 deg)
constant IQ phase balance constant IQ amplitude balance
• Clipping amplifier helps
vin Qp
Ip
70
80
90
100
110
Polyphase RC filter
vin Qp
Im
30
40
50
60
70
3-stage
IRR
[dB
]
Qm
0
10
20
30
2-stage
Frequency
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Divide-by-two IQ Generation• Wide bandwidth
D-latchD Q
DX QX
D-latchD Q
DX QX
• Wide bandwidth• Compact size, easy to design well• IRR limited by latch matching• Requires double-freq signal• Non-perfect input signal:DX QX
CLKDX QX CLK
DFFIN
I Q
• Non-perfect input signal:• Amplitude error => phase error• Phase error attenuates a bit
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Divide-by-two IQ Generation• Wide bandwidth
D-latchD Q
DX QX
D-latchD Q
DX QX
• Wide bandwidth• Compact size, easy to design well• IRR limited by latch matching• Requires double-freq signal• Non-perfect input signal:DX QX
CLKDX QX CLK
DFFIN
I Q
• Non-perfect input signal:• Amplitude error => phase error• Phase error attenuates a bit
BIAS &POWER CTRL
Q
IX
QX
INI
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Quadrature Oscillators
Oscillator 2Oscillator 1 0 90 180
270 0 180
0° 90° 180° 270° 0°
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Quadrature Oscillators
Oscillator 2Oscillator 1 0 90 180
270 0 180
0° 90° 180° 270° 0°
• Quadrature coupling results• Quadrature coupling resultsin increased phase noise
• Large die area
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017
Summary
• SX requirements, impact of phase noise, IQ imbalance (IRR)• DAS / DDS / PLL • DAS / DDS / PLL • CP-PLL • ADPLL
• Oscillators: Ring & LC• LC-oscillators: unity feedback / reactive feedback• Phase noise
• Frequency Dividers: dynamic ”CMOS” / static ”SCL”• IQ signal generation: RC polyphase / Div-2 / quadrature osc.
Department of Micro and NanosciencesStadius, Ul Haq
Integrated RF circuitsSpring 2017