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EIAJ ED-7311-19 - JEITA · EIAJ ED-7311-19 - 3 - semiconductor package “ at the EIAJ ED-7300, and a package with formed terminals led out of longer side of itself in two directions,

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Page 1: EIAJ ED-7311-19 - JEITA · EIAJ ED-7311-19 - 3 - semiconductor package “ at the EIAJ ED-7300, and a package with formed terminals led out of longer side of itself in two directions,
Page 2: EIAJ ED-7311-19 - JEITA · EIAJ ED-7311-19 - 3 - semiconductor package “ at the EIAJ ED-7300, and a package with formed terminals led out of longer side of itself in two directions,

EIAJ ED-7311-19

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Standard Japan Electronics and Information Technology Industries Association

Standard of integrated circuits package (P-SOP)

1. Scope of Application

This standard covers the registered dimensions of the Plastic Shrink Small Outline Package (herein after

referred to as P-SOP), which terminal straight pitch e is 1.27mm, among the packages classified as

form B in the EIAJ ED-7300 (Recommended practice on Standard for the preparation of outline drawings

of semiconductor packages)

Note This standard is created and corresponds to EIAJ EDR-7320 [Design guideline of integrated circuits

of Small Outline Package (SOP)] established in December 1998. The other relation standards are

shown below.

EIAJ EDR-7312 [Design guideline of integrated circuits for Thin Small Outline Package(TYPE I)(TSOP I)]

established in April 1996

EIAJ EDR-7313 [Design guideline of integrated circuits for Thin Small Outline Package (TYPE II)(TSOP

II)] established in April 1996

EIAJ EDR-7314 [Design guideline of integrated circuits for Shrink Small Outline Package (SSOP)]

established in April 1996

EIAJ ED-7311-1 [Standard of integrated circuits package (TSOP(1))] established in August 1997

EIAJ ED-7311-2 [Standard of integrated circuits package (TSOP(2))] established in August 1997

2. Definition of the Technical Terms

The definition of the technical terms used in this technical report is in conformity with EIAJ ED-7300, and

the definition of technical terms appearing a new are given within the text of this standard.

3. BACKGROUND

Recently, electronic appliance become smaller and thinner, on such background it is appearance the

P-SOP, terminal straight pitch e is 1.27mm (50mil). And after that, Terminal straight pitch e made

shrink, and it is appearance Plastic Shrink Small Outline Package (herein after referred to as P-SSOP) , it

also became used. This technical report intended to standardize the outer dimensions of P-SOP and

ensu re compa t ib i l i t y be tween p roduc ts as f a r as poss ib le fo r s tanda rd i za t i on .

4. Definition of P-SOP

P-SOP is defined as Form B with L terminal in the item 6, “Outline classification of shapes of

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EIAJ ED-7311-19

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semiconductor package “ at the EIAJ ED-7300, and a package with formed terminals led out of longer

side of itself in two directions, whose terminal pitch e is 1.27mm, are flat toward the outside of the

package body for mounting on print circuits board surface. (gull wing shape lead)

5. Numbering of Terminals

Numbering of terminals complies with the EIAJ ED-7300.

6. Nominal Dimensions

Package width X Package length(Symbol : E X D ) is applied to Nominal Dimensions.

However as the exception, old nominal dimensions is possible to use places (side by side) and it writes

which package width (Symbol : E).

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REFERENCE CHARACTERS AND DRAWING Outline Drawing

Figure 1

H

M

S

E(

)4

( )

2

ZD

1

y S ( )2

A1

( )

A1

4

e 0.10

X n

A2

bp

A

S

x

E

n/2 X4f

n

/2D

5

A20.

10

A

/2/2

H

E(

)4E

n/2+1 B

D ( )4

( )1

AP S ( )3

A B

BtX2

S A

JEITA STANDARD PACKAGE OUTLINE DRAWINGS

DATE 2001-12-01

SHEET 1/75

PACKAGE NAME P-SOP

JEITA REGISTRATION NO. IC-7320-001

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Figure 2 Detail area of datum A For even number of terminals on a package side For odd number of terminals on a package side

n/4

e /2

A1

3n/4+1

e /2

n/4+1 (n+2)/4

e /2

0.10

0.10

(3n+2)/4

0.10

3n/4

A2

A1

e /2

0.10

A2

JEITA STANDARD PACKAGE OUTLINE DRAWINGS

DATE 2001-12-01

SHEET 2/75

PACKAGE NAME P-SOP

JEITA REGISTRATION NO. IC-7320-001

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APPENDIX ALLOWABLE RANGE OF SOLDERING PART OF TERMINALS

The range where the terminals to be soldered can exist is shown Figure 4 as reference for the foot

print design.

Figure 4

eE

/2

B

l1eE

e A b3

JEITA STANDARD PACKAGE OUTLINE DRAWINGS

DATE 2001-12-01

SHEET 5/75

PACKAGE NAME P-SOP

JEITA REGISTRATION NO. IC-7320-001

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Registration table Package name:P-SOP Registration number: IC-7320-001

serial number table

Note The Numbers in the table indicate, (serial number) of 1st cord and 2nd cord.

JEITA STANDARD PACKAGE OUTLINE DRAWINGS

DATE 2001-12-01

SHEET 6/75

PACKAGE NAME P-SOP

JEITA REGISTRATION NO. IC-7320-001

P-SOP(terminal pitch e =1.27)Package

widthBodyheight

E max A2nom 6 8 14 16 18 20 22 24 28 30 32 36 40 42 442.701.701.501.401.202.701.701.501.401.202.701.701.501.401.202.701.701.501.401.202.701.701.501.401.202.701.701.501.401.20 FE

Remark

L/L1=1.00/0.50L/L1=1.60/0.80

FAFBFCFD

EBECED

CEDADB

EE

DCDDDEEA

CACBCCCD

BBBCBDBE

L/L1=1.00/0.50ADAEBA

Nominal dimensions

eEPin number

AA

0572 4.72(0225)ABAC

0762 (0300) 6.62

(0525) 11.94

1524 (0600) 13.84

8.13(0375)0953

1324

1143 (0450) 10.03

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