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NOV/DEC-2007/EI43-ANSWER KEY

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University Question R3306 Key

Part-A

1. E3FA -> (1110 0011 1111 1010)2

2.Demorgans Theorem:

De Morgan's theorems state that

1. A . B = (A +B)

2. A + B = (A.B)

The first equation reads "NOT A AND NOT B EQUALS A NOR B" and

the second reads "NOT A OR NOT B EQUALS A NAND B"

3. Truth table for Full Adder:

A B CIN S COUT

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

4. Use of Multiplexer:

1. Sequence detector

2. Function generator

3. Parallel to Serial Converter

5. Excitation table for JK flip flop:

Q Q+ J K

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0 0 0 X

0 1 X 1

1 0 1 X

1 1 X 0

6. Logic diagram for T flip flop:

7. Common clock pulse is applied for the entire flip flop in synchronous circuitwhere as output of the previous flips flop is applied as clock in asynchronous

circuit.

8. Advantage:

1. Easier to design2. Easy to analyze

Disadvantage:

1. Races and cycles2. Hazards

9. Advantage of CMOS;

1. High speed2. Less Propagation delay

3. Less Power dissipation

10. ROM can not be reprogrammable where as PROM is reprogrammable

Part-B

11 a) i) XY+XZ+YZ = XY + XZ ( By consensus theorem)

ii) (X+ Y) (X+Z) (Y+Z) = (X+ Y) (X+Z) ( By consensus theorem)

iii) XYZ+XYZ = XZ ( Y+Y)

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= XZ

iv) XY+XY+XY =XY + X(Y+Y)

= XY +X

= X+ Y

v) A+ AB = A(1+B)

= A

vi) X y + X y = X (y + y)

= X

vii) X+XY = X+Y

11 b) i) f(W,X,Y,Z) = m(0,1,2,4,5,6,8,9,12,13,14)

YZ YZ YZ YZ

WX 1 1 1

WX 1 1 1

WX 1 1 1

WX 1 1

F = Y + WZ + XZ

ii) f (A,B,C,D) = m(0,1,2,4,5,10,11,13,15)

CD CD CD CD

AB 1 1 1

AB 1 1

AB 1 1 1

AB 1

F = AC + BCD + ABC + BCD

12) BCD to Seven Segment Display:

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12 b) i) 2 to 4 line decoder:

ii) 4 to 1 line Mux:

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13 a) 4 bit binary counter:

State table:

D C B A D+ C+ B+ A+ JD KD JC KC JB KB JA KA0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 1

0 0 0 1 0 0 1 0 0 X 0 X 1 X 1 1

0 0 1 0 0 0 1 1 0 X 0 X X 0 1 1

0 0 1 1 0 1 0 0 0 X 1 X X 1 1 1

0 1 0 0 0 1 0 1 0 X X 0 0 X 1 1

0 1 0 1 0 1 1 0 0 X 1 X 1 X 1 1

0 1 1 0 0 1 1 1 0 X 1 X X 0 1 1

0 1 1 1 1 0 0 0 1 X X 1 X 1 1 1

1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 1

1 0 0 1 1 0 1 0 X 0 0 X 1 X 1 1

1 0 1 0 1 0 1 1 X 0 0 X X 0 1 11 0 1 1 1 1 0 0 X 0 1 X X 1 1 1

1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 1

1 1 0 1 1 1 1 0 X 0 1 X 1 X 1 1

1 1 1 0 1 1 1 1 X 0 1 X X 0 1 1

1 1 1 1 0 0 0 0 X 1 X 1 X 1 1 1

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13) b) Mod-6 Counter:

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14 a)

State Table:

Present State Next State with output

00 01 11 10

A A,0 B,- -,- C,-

B A,- B,0 D,- -,-C A,- -,- D,- C,0

D -,1 B,- D,1 C,-

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State Reduction:

A B

C

D

A,B,C S0D S1

State Table:

Present State Next State with output

00 01 11 10

S0 S0,0 S0,0 S1,- S0,0

S1 S0,- S0,- S1,1 S0,-

Excitation Table:

Q X1 X2 Q+ T

0 0 0 0 0

0 0 1 0 0

0 1 0 0 0

0 1 1 1 1

1 0 0 0 1

1 0 1 0 1

1 1 0 0 11 1 1 1 0

T = QX1 + QX2+ QX1X2

Z = Q

14 b) i) Eliminating race condition:

Two methods:

1. Shared row state assignment2. One hot state assignment

1. Shared row state assignment:

- New temporary unstable state is introduced in between two state

changes

2. One hot state assignment:- Only one binary value is hot at a time

- New states are added later.

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ii) Steps involved in analysis of Asynchronous sequential circuit:

1. Expression for input and output variables are found2. Excitation table is obtained from the expression

3. Primitive flow table is constructed from the excitation table

4. State diagram is obtained

iii) Out of syllabus

15 a) FPGA:Field Programmable Gate Arrays are two dimensional array of logic blocks and

flip-flops with a electrically programmable interconnections between logic blocks.

The interconnections consist of electrically programmable switches which is why FPGAdiffers from Custom ICs, as Custom IC is programmed using integrated circuit

fabrication technology to form metal interconnections between logic blocks.

In an FPGA logic blocks are implemented using mutliple level low fanin gates,which gives it a more compact design compared to an implementation with two-levelAND-OR logic. FPGA provides its user a way to configure:

1. The intersection between the logic blocks and

2. The function of each logic block.

Logic block of an FPGA can be configured in such a way that it can providefunctionality as simple as that of transistor or as complex as that of a microprocessor. It

can used to implement different combinations of combinational and sequential logic

functions. Logic blocks of an FPGA can be implemented by any of the following:

1. Transistor pairs2. combinational gates like basic NAND gates or XOR gates

3. n-input Lookup tables

4. Multiplaexers5. Wide fanin And-OR structure.

Figure 1: Simplefied version of

FPGA internal architecture.

Routing in FPGAs consists of wire segments of varying lengths which canbe interconnected via electrically programmable switches. Density of logic block

used in an FPGA depends on length and number of wire segments used for

routing. Number of segments used for interconnection typically is a tradeoff

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between density of logic blocks used and amount of area used up for routing.

The ability to reconfigure functionality to be implemented on a chip gives a

unique advantage to designer who designs his system on an FPGA It reduces thetime to market and significantly reduces the cost of production.

ii) EPROM:

A rewritable memory chip that holds its content without power. EPROM chips are

written on an external programming device before being placed on the circuit board. The

chip requires an expensive ceramic chip package with a small quartz window that iscovered with opaque, sticky tape. For reprogramming, the chip is extracted from the

circuit board, the tape is removed, and it is placed under an intense ultraviolet (UV) light

for approximately 20 minutesEPROMs use a transistor with a floating gate underneath a control gate. To

program the bit, a high voltage is applied to the control gate. This causes electrons to

tunnel through the insulating oxide layer into the floating gate, which impedes thesubsequent operation of the control gate. The 0 or 1 is determined by whether the voltageon the control gate is blocked or not.

The floating gate can hold the charge for more than a decade or until the device is

erased; however, EPROMs only support a few hundred erase-write cycles.

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15 b) Comparison:

Family Basic Fanout Pd Noise Prop. delay Clock

gate (mW/gate) immunity (ns/gate) (MHz)

TTL NAND 10 10 VG 10 35

TTL-H NAND 10 22 VG 6 50

TTL-L NAND 20 1 VG 33 3

TTL-LS NAND 20 2 VG 9.5 45

TTL-S NAND 10 19 VG 3 125

TTL-AS NAND 40 10 VG 1.5 175

TTL-ALS NAND 20 1 VG 4 50

ECL 10K OR-NOR 25 40-55 P 2 >60

ECL100K OR-NOR ?? 40-55 P 0.75 600

MOS NAND 20 0.2-10 G 300 2

74C NOR/NAND 50 0.01/1 VG 70 10

74HC NOR/NAND 20 0.0025/0.6 VG 18 60

74HCT NOR/NAND 20 0.0025/0.6 VG 18 60

74AC NOR/NAND 50 0.005/0.75 VG 5.25 100

74ACT NOR/NAND 50 0.005/0.75 VG 4.75 100

ii) CMOS NAND gate:

The structure can be inverted, as shown to the left. Here we have a two-inputNAND gate, where a logic 0 at either input will force the output to logic 1, but it

takes both inputs at logic 1 to allow the output to go to logic 0.

This structure is less limited than the bipolar equivalent would be, but there are

still some practical limits. One of these is the combined resistance of the MOSFETs

in series. As a result, CMOS totem poles are not made more than four inputs high.

Gates with more than four inputs are built as cascading structures rather than singlestructures. However, the logic is still valid.

Even with this limit, the totem pole structure still causes some problems in

certain applications. The pull-up and pull-down resistances at the output are neverthe same, and can change significantly as the inputs change state, even if the outputdoes not change logic states. The result is uneven and unpredictable rise and fall

times for the output signal. This problem was addressed, and was solved with the

buffered, or B-series CMOS gates.

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The technique here is to follow the actual NAND gate with a pair of

inverters. Thus, the output will always be driven by a single transistor, either P-

channel or N-channel. Since they are as closely matched as possible, the outputresistance of the gate will always be the same, and signal behavior is therefore

more predictable.

One of the main problems with CMOS gates is their speed. They cannot

operate very quickly, because of their inherent input capacitance. B-seriesdevices help to overcome these limitations to some extent, by providing

uniform output current, and by switching output states more rapidly, even if the

input signals are changing more slowly.

Note that we have not gone into all of the details of CMOS gate constructionhere. For example, to avoid damage caused by static electricity, different

manufacturers developed a number of input protection circuits, to prevent input

voltages from becoming too high. However, these protection circuits do not

affect the logical behavior of the gates, so we will not go into the details here.

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