Emerging Technologies in Nano-electronics AreaAdersh Miglani

Email: Adersh.Miglani@gmail.com, Date: 24-July-2013

In the semiconductor industry, miniaturization of featuresize is led by rapid improvements in integration, cost, speed,power, compactness, and functionality of integrated circuits.These ”scaling” improvements, are largely influenced by theadvancing research in nanotechnology. Research in nanotech-nology influences all the stages from modification of atom andmolecular structure to system and package level integratedcircuits, an end-product. Broadly interpreted, capabilities ofCMOS process should be augmented by devising new semi-conductor devices which provide useful properties in additionto traditional CMOS devices.

In this text 1, we attempt to describe the emerging researchin semiconductor devices which is primarily led by the rise ofthe realm of nanotechnology. The CMOS dimensional scalingtechniques would end when current nanotechnology of 22nm will scale to around 7 nm by 2020. There are multipletechniques to further scale CMOS beyond 7 nm technology.Few important ones are discussed here. After making allthose changes in the CMOS devices, the electrical propertiesare altered and should be investigated in detail. Most of theresearch in nanoscale MOSFET for CMOS is to modify itschannel to achieve scale improvements.

The compound semiconductor materials offering highermobility and higher quasi-ballistic-carrier velocity should re-place strained silicon MOSFET channel and, convincingly,alter source and drain regions. This imposes few challengessuch as heterogeneous fabrication of selected materials forchannel. Band-to-band tunneling should be minimized dueto narrow bandgap channel materials. The dielectric interfacebetween channel and gate should not have Fermi level pinning.Since, these CMOS gates scaled and doping concentrations arealso altered, the leakage current and power dissipation shouldnot be compromised.

The Ferroelectric FET (FeFET) has an integrated ferroelec-tric capacitor within the gate stack. Due to the capacitance,the charges in the channel modify the FET output charac-teristics. Carbon Nanotube FETs (CNT FET) have highlymobile charge carriers and minimum short channel effects.Graphene Nanoribbon FETs have carrier mobilities higher thanCNT FET. The main problem in using graphene as transistorchannel is that it has zero bandgap energy. The bandgap energywas increased by enabling carrier transport through graphenenanoribbons with 2-nm width.

Another technique is to use semiconductor nanowire withdiameter 0.5 nm in place of established MOSFET channel.The compound semiconductors from III-V and II-VI groups

1Referenced from ITRS www.itrs.net/

can be used to form this nanowire. The off-chip interconnectcapacitance puts a limitation on the operating speed in circuitsdesigned using devices with nanowires.

Use of III-V compound semiconductors have much betterelectron mobility. These materials are right candidates forusing as a n-channel in MOSFETs. This imposes a challengein hetro-integration on silicon substrate. Devices with thesechanges are called heterostructure FETs (HFETs). Addition-ally, low EOT (equivalent oxide thickness) gate dielectric andlow resistivity junctions should be considered. Germanium canalso be used as channel in MOSFETs but this reduces electronmobility. The bottleneck was high interface state densitynear conduction band edge. This problem is fixed by usinggermanium oxide at the Ge-dielectric interface. Additionalefforts in reducing EOT and in scaling gate-length are inprogress.

The transition from Ion to Ioff should be quick. This abrupttransition is measured by low subthreshold swing limit atthe room temperature and controlled by thermal injectionof carriers from the source to the channel. Less than 60mV/decade subthreshold, which is a limit for conventionalMOSFETs, is achieved in Tunnel FETs with gate reversedbiased p-i-n junctions. Therefore, Tunnel FETs can work withlower VDD which results in low power dissipation. Impactionized based FETs (IFET) have steeper Ion to Ioff currenttransition at room temperature.

Low operating voltage and power is achieved by replacinginsulator from MOSFET gate stack by ferrorlectric insulator.This leads to subthreshold limit to below 60 mV/decadewithout modifying physics in FET. Thus, higher Ion levels areachieved at lower voltages with suitable ferroelectric materialswith minimal hysteresis. The negative capacitance matchingwith device capacitance shows steep subthreshold transitionthat is achieved with no hysteresis. Since, capacitance varieswith voltage, a thin double gate structure solve the purpose.

The number of choices to improve performance of MOSFETinclude multiple gates in FET (FinFETs) and silicon-on-insulator (SOI) MOSFET. Research on reducing equivalentgate oxide thickness and on incorporating high-channel dopingto control short-channel effects are still in progress. Thesetechniques including ultra-thin body FD-SOI should be con-sidered to improve planar MOSFETs.

The short term challenges are confined to scaling of SiCMOS. The long term challenges comprise incorporatingadvanced non-planar multi-gate MOSFETs with short gatelength, controlling short-channel effects, controlling parasiticresistance involving source and drain and enhancing thermalvelocity and quasi-ballistic transport.