EEL-6167 VLSI DESIGNSPRING 2004 TERM PROJECT

Mirror Circuits: Design and Simulation

Craig ChinMiguel Alonso Jr.

Overview

The theory behind mirror-circuit logic design is introduced.

The method and tools involved in the simulation and layout of the various logic circuits are discussed.

The simulation circuits, the circuit layouts, and the simulation results are presented.

Observations pertaining to the design process and the simulation results are discussed.

Introduction

Mirror circuits are based on series-parallel configurations of MOSFETs.

A mirror circuit has the same transistor topology for the nFETs and the pFETs (refer to Figure 1).

NAND2, NOR2, EXOR2, or EXNOR2 logic gates can be constructed using the same mirror circuit structure.

The different functionalities are implemented by varying the inputs at each gate.

Only one general layout is necessary. This simplifies the layout process.

Introduction

OUT

IN

VCC

IN

0IN

IN

IN

IN

VCC

0

ININ OUT

IN

Figure 1- Mirror Circuit for (a) Inverter and (b) Generic two input logic gate

Introduction

The rise times and fall times of the EXOR and EXNOR mirror circuit gates are shorter than their AOI counterparts.

However, the rise times and fall times the mirror circuit AND and NOR gates are slightly longer (see Table 1).

Introduction

Gate Mirror Conventional

NAND

NOR

MODEL

outpppr CRCRt 2

outnnnf CRCRt

outpppr CRCRt

o u tnnnf CRCRt 2

outnf CRt 2

outpr CRt

ou tpr CRt 2

outnf CRt

Table 1- Rise Times and Fall times of Mirror Circuits vs. Conventional Circuits

Method

The circuits to be explored were designed using Orcad’s PSPICE for the circuit simulation, and the LASI utility for designing the physical layout.

www.mosis.org, provides information on design rules for various processes, along with the scalable CMOS (SCMOS) design rule set.

A scalable CMOS (SCMOS) design rule set is based on reference measurement lambda (λ), which has units in microns.

All of the dimensions in the layout are written in the form Value = mλ

The layer maps used are shown in Figures 2 and 3.

Method

Figure 2- Layer Map for SCMOS

Method

Figure 3- Layer Map for SCMOS (cont'd)

Method

LASI is available free from http://members.aol.com/lasicad This tool combines the layout process with PSPICE, giving a very

accurate representation of the physical model using SPICE. It auto-routes layouts, calculates parasitic capacitances, and provides

circuit files for use during SPICE simulation. It has the capability of performing design rule checks for a set of design

rules. ORCAD simulations provides the advantage of the hierarchical circuit

structures, where design takes place using sub-circuits. The Taiwan Semiconductor Manufacturing Corporation (TSMC) was

chosen to be the process, because their process parameters were the only ones available on the Mosis website.

Method

With the process parameters already defined, in order to provide an accurate model for simulation, the length and width of the NFET and PFET were specified to be:Ln = 0.7um, Wn = 1.4um, Lp = 0.7um, Wp = 3.5um

The (W/L) ratio for the NFET is 2 and for the PFET is 5, in order to maintain the device trans-conductance’s the same.

These values, in addition to the SPICE model parameters, are used for performing the circuit simulations for the Inverter, NAND, NOR, EXOR, and the D Flip Flop.

Circuit Diagrams and Layouts

Figure 4-NMOS FET Layout

Figure 5- PMOS FET Layout

Circuit Diagrams and Layouts

V C C

M 3

M b re a k n D

0

V C C

5 V

0

M 4

M b re a k p D

0

V 1

TD = 0

TF = 0 . 0 1 nP W = 0 . 0 0 5 uP E R = 0 . 0 1 u

V 1 = 0 V

TR = 0 . 0 1 n

V 2 = 5 V

Figure 4 – Inverter Circuit Diagram

Figure 5 – Inverter Layout

Circuit Diagrams and Layouts

Figure 6 – NAND2 Circuit Diagram Figure 7 – NAND2 Layout

5 V d c

0

M 5

M b re a k N D

V 1

TD = 0

TF = 0 . 0 1 nP W = 0 . 5 uP E R = 1 u

V 1 = 0 V

TR = 0 . 0 1 n

V 2 = 5 V

V aV a

V a

M 8

M b re a k N D

M 4

M b re a k P D

V C C

M 6

M b re a k N D

V a

0

V b

M 3

M b re a k P D

V 2

TD = 0

TF = 0 . 0 1 nP W = 1 uP E R = 2 u

V 1 = 0 V

TR = 0 . 0 1 n

V 2 = 5 V

M 1

M b re a k p D

V C C

V b

V a

V b

M 7

M b re a k n D

0

V b

V b

M 2

M b re a k P D

0

Circuit Diagrams and Layouts

Figure 8 – Edge-Triggered D Flip-Flop Circuit Diagram

N / A

V 1

TD = 0

TF = 0 . 0 1 nP W = 1uP E R = 2 u

V 1 = 0 V

TR = 0 .0 1 n

V 2 = 5 V

V 2

TD = 0

TF = 0 . 0 1 nP W = 0 . 5 uP E R = 1 u

V 1 = 5 V

TR = 0 .0 1 n

V 2 = 0 V

D in

0

D in

U 2

D la t c h

1

2

3

4

D

E N A B L E

Q

/Q

C lo c k

Q

C lo c k

U 3

N o t

21YX

U 4

N o t

21YX

0

U 5

D la t c h

1

2

3

4

D

E N A B L E

Q

/ Q / Q

Circuit Diagrams and Layouts

Figure 9 – D Latch Sub-circuit Diagram

E N A B L E

Q

n a n d 3

S C H E M A TI C 5

V c 3V b 3

V a 3

n a n d 1

S C H E M A TI C 3

V a 1

V b 1V c 1

D

/Qn o t 1

S C H E M A TI C 7

V y 1V x 1

n a n d 4

S C H E M A TI C 6

V c 4V b 4

V a 4

n a n d 2

S C H E M A TI C 4

V c 2V b 2

V a 2

5 V

X

M 4

M b re a k p D

M 3

M b re a k n D

0

0

Y

Figure 10 – Inverter Sub-circuit Diagram

Circuit Diagrams and Layouts

Figure 11 – Edge-Triggered D Flip-Flop Layout

Results of Simulation

Figure 13 – Inverter Simulation at 10MHz

Time

0s 0.2us 0.4us 0.6us 0.8us 1.0us 1.2us 1.4us 1.6us 1.8us 2.0usV(V1:+)

0V

2.5V

5.0VV(M4:d)

0V

5.0V

-3.0VSEL>>

Time

0s 2ns 4ns 6ns 8ns 10ns 12ns 14ns 16ns 18ns 20nsV(M3:g)

0V

2.5V

5.0V

SEL>>

V(M4:d)

-2.5V

0V

2.5V

5.0V

Figure 12 – Inverter Simulation at 1MHz

Results of Simulation

Figure 14 – Inverter Simulation at 100MHz

Time

0s 2ns 4ns 6ns 8ns 10ns 12ns 14ns 16ns 18ns 20nsV(M3:g)

0V

2.5V

5.0V

SEL>>

V(M4:d)

-2.5V

0V

2.5V

5.0V

Results of Simulation

Figure 16 – NAND2 Simulation at 10MHz

Figure 15 – NAND2 Simulation at 1MHz Time

0s 0.5us 1.0us 1.5us 2.0us 2.5us 3.0us 3.5us 4.0usV(VA)

0V

2.5V

5.0VV(VB)

0V

2.5V

5.0VV(M4:d)

5V

10V

-3VSEL>>

Time

0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400nsV(VA)

0V

2.5V

5.0VV(VB)

0V

2.5V

5.0V

SEL>>

V(M4:d)

0V

5V

10V

Results of Simulation

Figure 17 – NAND2 Simulation at 100MHz

Time

0s 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40nsV(VA)

0V

2.5V

5.0VV(VB)

0V

2.5V

5.0V

SEL>>

V(M4:d)

0V

5V

10V

Results of Simulation

Figure 19 – Edge-Triggered D Flip-Flop Simulation at 10MHz Clock

Figure 18 – Edge-Triggered D Flip-Flop Simulation at 1MHz Clock Time

0s 0.5us 1.0us 1.5us 2.0us 2.5us 3.0us 3.5us 4.0usV(CLOCK)

0V

2.5V

5.0V

SEL>>

V(DIN)0V

2.5V

5.0VV(Q)

0V

2.5V

5.0V

Time

0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400nsV(CLOCK)

0V

2.5V

5.0VV(DIN)

0V

2.5V

5.0V

SEL>>

V(Q)

0V

2.5V

5.0V

Results of Simulation

Figure 20 – Edge-Triggered D Flip-Flop Simulation at 100MHz Clock

Time

0s 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40nsV(CLOCK)

0V

2.5V

5.0VV(DIN)

0V

2.5V

5.0V

SEL>>

V(Q)

0V

2.5V

5.0V

Results of Simulation

At 100 MHz The rise time for the inverter was .24 ns The fall time for the inverter was 0.04 ns The propagation delay for the D Flip Flop was

2.72 ns The rise time for the D Flip Flop was 2.02 ns The fall time for the D Flip Flop was 0.916 ns

Discussion

Mirror Circuits were investigated using the various tools

The advantage of using mirror circuits comes in the layout process

Mirror circuits do, however, experience changes in the rise and fall times when compared to their minimal realization counter parts

This is evident from the simulation plots

Conclusion

In general, in order to improve the performance of the various circuits Select a better process that allows for smaller geometries Since the SCMOS design convention was used, there is

no need to redesign the layouts, it is simply a matter of rescaling them

Perhaps, if the above does not improve performance, the placement of the various sub-cells can be improved to minimize metalization paths