By Alexander Czajor

Thierry Crespo

Frederic Le Cam

Olivier Ferrand

STMicroelectronics

The complexity of vehicle electronics has significantly increased during the last 20 years. A large number of new functionalities require a significant amount of status information to be displayed to the driver. This information is typically provided via the cluster panel by means of simple LEDs, a segment LCD or even dot matrix LCD displays.

In the past, TFT displays were not broadly used in vehicles for several main reasons: high price of the TFT panel, their inability to sustain automotive quality and reliability standards, and the high system cost of electronics required to drive the display panel and manage the HMI. The required electronic components such as graphic accelerators and flash or SDRAM/DDRAM memories were also adding to the impact on cost, quality and reliability. Due to the resulting high cost, TFT-based clusters were reserved for high-end cars with very low volumes.

The disadvantage of standard graphic solutions is that large frame buffers are required. The SPC56xS microcontroller family is a new bufferless concept, allowing the MCU to fetch graphics from arbitrary memory locations (flash or RAM). In addition, the graphic information is stored in layers minimising the required memory size through optimisation of the colour depth for each layer. A direct unbuffered bit blitter assembles the image providing excellent graphic

rendering with minimal memory and bandwidth resource usage.

The resulting reduction of system resources, memory in particular, paves the way to an integration of the complete infrastructure into a single-chip solution. Supporting typical QVGA/WQVGA display formats, this significantly reduces the semiconductor cost of future instrument cluster panels and dashboard applications.

ChallengesThe display market must be aware of the three main challenges when trying to understand the automotive instrument cluster applications:• System cost constraints;• Quality and reliability issues;• System compatibility and

scalability across a given range of products.

To understand these three main points, classical system architectures as they exist today shall be reviewed.

Basic cluster architecture—Figure 1 shows the architecture Figure 1: Shown is the architecture of a basic instrument cluster application.

Figure 2: Shown is a current TFT-display cluster architecture.

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Understanding automotive instrument cluster apps

AUTOMOTIVE ELECTRONICS

of a basic instrument cluster application.

It contains gauges to inform the driver about vehicle speed, engine speed, fuel level or oil temperature. Generally four to six gauges are required and are controlled with specific stepper motor control outputs of the MCU.

For information display, these architectures use a parallel LCD bus, an SPI or PWM signals to drive respectively a segment LCD, dot matrix or LEDs. Several communication buses are required to communicate with sensors, actuators or the body controller. These are usually LIN or CAN buses.

For cost optimisation, such applications use single or dual layer PCB boards.

Current TFT-display cluster architectureThe TFT-display cluster can come in many variants; with or without mechanical gauges, single or dual panels. A possible generic architecture is described in Figure 2.

This architecture embeds the same type of microcontroller as the one used in Figure 1 for the control of basic cluster peripherals (such as gauges) and a dedicated graphic controller. The graphic controller receives HMI information from the cluster MCU via fast SPI or EBI buses. This architecture requires storage of graphic data in an external parallel flash memory. For graphics processing, it uses several buffers stored in external SDRAM/DDRAM components. These buffers are usually the size and resolution of the display panel. As the buffers are large, it is difficult to integrate them into a monolithic circuit. The display data is sent to the TFT panel via the display controller.

This example helps to understand the limitations of this architecture regarding the three challenge segments listed above:• System cost—The

architecture requires up to four complex silicon

components, ruling out the possibility to use simple PCBs; multi-layer PCBs or even multiple boards are needed. The bandwidth requirement is high due to the amount of graphic data to be transferred.

• Quality and reliability—The devices are in different packages and technologies, thereby increasing quality and reliability concerns. If

multiple boards are involved, contact issues due to the connectors must be taken into account.

• System compatibility and scalability—The device complexity and large pin-count packages usually lead to PCB redesign and non-compatibility of hardware and software when addressing different application variants.

The SPC56xS controller family provides system cost savings by embedding the HMI and graphic display controller inside the main cluster microcontroller. The architecture is illustrated in Figure 3.

This architecture is possible thanks to a hardware graphic controller, working with very limited bandwidth and memory requirements.

The concept uses a display

Figure 3: Shown is the SPC56xS TFT display cluster architecture.

Figure 4: Shown is the SPC56xS60 block diagram.

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control unit, consisting of a direct unbuffered bit blitter. It fetches pre-rendered, or software

generated, bitmaps called layers from various memory resources and assembles them into the

display without going through a buffer mechanism. Arbitration allows prioritizing the bitmaps

before hardware blending and display. Figure 5 describes this concept.

Figure 5: The display control unit concept is illustrated.

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