EEE515J1ASICs and DIGITAL DESIGN

Lecture 8: Testing

Ian McCrum Room 5D03BTel: 90 366364 voice mail on 6th ringEmail: IJ.McCrum@Ulster.ac.ukWeb site: http://www.eej.ulst.ac.uk

Last changed 26/11/06@18:00

Introduction to Testing 2.

Exhaustive testing is only viable in small designs, but even then if testing is either costly or slow there may be a considerable motivation to optimise testing. Several approaches exist and indeed we could spend an entire module on testing.

Consider the need to find manufacturing faults or defects in an ASIC. We should first consider the type of faults that occur and then see how these can be identified.

Modern devices can have very fine tracks of less than .25 microns and very fast gates on the sub nanosecond area in some cases. Faults that cause malfunction may be dynamic in nature, if two tracks are close together then rapid changes of voltage in one line may induce a voltage and subsequent undesired effect in an adjacent track. Matrices of cells as found in RAM or PLA structures may have pattern induced problems, possibly due to inadequate power supply de-coupling or clock distribution effects. Solving these types of problems and providing a workable clock distribution tree with no skew is keeping modern ASIC designers busy these days!

Luckily (for you) it is too complex to model this type of fault and a simpler model is used. We assume that a fault may be caused by a blob or contaminant and the fault thus caused is static in nature. It is assumed that the net or node concerned will be stuck at one or stuck at zero: it will not “wiggle” up and down if excited.

The problems of test are therefore to find a way to “wiggle” every node in a circuit up and down and ensure we can observe something that confirms that the node has “wiggled” up and down.

Key terms used in testing are;

Fault model A simplification of real faults, but usable nonethelessStuck at zero (SA0) Find all these andStuck at one (SA1) all these and you’ll find most of the faulty chipsControllability You have to be able to “wiggle” nodes up and downObservability You have to be able to observe the effect of a “wiggle”Test vector An example input used to exercise the chipTest set A list of test vectors that form a complete test.Fault list A list of all detectable faultsFault coverage The percentage of faults found by a test set

Manufacturing Test A speck of dust on a wafer is sufficient

to kill chip Yield of any chip is < 100%

Must test chips after manufacturing before delivery to customers to only ship good parts

Manufacturing testers are very expensive Minimize time on tester Careful selection of

test vectors

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Stuck-At Faults

How does a chip fail? Usually failures are shorts between two

conductors or opens in a conductor This can cause very complicated behavior

A simpler model: Stuck-At Assume all failures cause nodes to be “stuck-at”

0 or 1, i.e. shorted to GND or VDD

Not quite true, but works well in practice

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Observability & Controllability

Observability: ease of observing a node by watching external output pins of the chip

Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip

Combinational logic is usually easy to observe and control

Finite state machines can be very difficult, requiring many cycles to enter desired state Especially if state transition diagram is not known

to the test engineer

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Test Pattern Generation Manufacturing test ideally would check every

node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors

necessary to prove each node is not stuck.

Good observability and controllability reduces number of test vectors required for manufacturing test. Reduces the cost of testing Motivates design-for-test

As a guide, most silicon foundries will insist on being given a test set along with the manufacturing data to make the chip; the fault coverage should be in excess of 98%. This will allow them to say, if the chip doesn’t work when you plug it into your application that it must be a design fault and not a manufacturing fault. An ASIc might have setup charges of £29,000 and unit costs of £3-4 per chip. Testing can easily be 30-50% of these figures. It makes sense to “design for test” right at the outset. The design methods I have promoted in this class produce reliable, easily tested circuits, some of the ad hoc design methods do not.

Design for test guidelines

Partition your design into small functional unitsIf using RAM or PLA structures think of adding extra rows to provide selftestingUse only synchronous designs,

Use only synchronous designs, 0) Never gate a clock pin of a flipflop, add an “enable” to the state diagram

1) Ensure that sufficient inputs and outputs are provided to allow sufficient “controllability” and “observability”. This may require pins to be dual purpose and the provision of multiplexors within the chip, perhaps to bring out the “state” of some internal FSM.

2) Never feed a clock pin from the Q output of another flipflop.

3) Don’t use more than one clock; this may require adding enables to your FSMs, For instance if you need a “dvide by 48” and you have a master 1MHz clock.Make a divide by 3 followed by a divide by 16. The divide by 16 should also be clocked by the 1 MHz signal but it should be enabled with the output of the divide by 3. Enabled within the logoc of its next state decoder (see (a) above)

4) Arrange all signals to be synchronised to the system clock, asynchronous inputs should be synchronised as a soon as possible. This prevents metastability problems.

5) Design your clock distribution ciruitry first to avoid clock skew.

The rules above can be bent or even broken and very large designs may use a multiphase clock. Use of digital phase locked loops can provide low skew clocks at any place across a million chip ASIC.

It is common to use the rising edge of the clock most of the time but add isolation latches clocked by the falling edge of the clock to get the “soldiers marching in step”. In fact isolation latches or pipelines are used to separate blocks in a partitioned design.

Not withstanding the above there is a simple technique called SCAN PATH TESTING that can provide easy access to all parts of a chip, or for that matter, all parts of an embedded Printed circuit board.

Provided a chip is designed with the guidelines above then it may be thought of as a collection of blocks, where each block is a combinational circuit of finite state machine.

The FSMs are themselves combinational blocks and banks of flipflops. The method is best suited to D-type flipflops because of their simplicity.

The technique has a fixed, deterministic cost and this is much better than starting to add extra test circuitry in an ad hoc fashion to improve controllability and observability.

SCAN PATH TESTING

This adds 3 gates to every flipflop, requires 3 or 4 extra pins and adds extra routing of 3 tracks around the chip.

The routing may add 15% to the chip area. But at least these costs are guaranteed maximums.

The disadvantage is that Scan path testing is slow.

The cost guarantee outweighs the disadvantages.

A FSM is comprised of a “NEXT STATE DECODER” and a bank of D-type flipflops. An optional combinational circuit may be used to form the outputs.

For this method to work most conveniently we would “capture” external inputs into a D-type register as soon as possible.

The method requires us to swop every simple D-type with a “SCAN PATH CELL” and these are then connected together with circuitry which is not used during NORMAL operation of the chip.

There are quite a few designs of scan path cells, many silicon vendors have their own designs using dual clocks, transparent latches of level sensitive scan cells to avoid a performance penalty or to minimise silicon area.

We will only consider the scan cell below, it only works if all flip-flops are already clocked from a common clock;

if this was not the case then an extra multiplexer is added to switch the clock pin of the flip-flop and extra care taken in the testing sequences.

NSD 1

NSD 2OD

Now consider the diagram below, a larger digital system can be thought of as a number of FSMs interconnected. The scan cells are interconnected as shown, as a huge snakelike shift register. The basis if scan path testing is to use this shift register to gain controllability and observability of all combinational circuits within the chip. Thus we can apply combinational tests and access the combinational circuits response.

For example the diagram above shows a 3 flip-flop FSM and a 2 bit FSM. We can shift in a 2 bit test vector for FSM 2 and a 3 bit test vector for FSM 1. The process is

Switch the muxes from normal to test.Clock in 5 bits on the DIN pinSwitch the muxes to normal

Clock once; the vectors are appliedAnd the answer is latched into the f/fs

Switch the muxes to testClock 5 times; note DOUT, the answer

(Actually you could clock in 5 new bits whilst reading the previous 5 bit answer.)

Perhaps 7 tests will suffice, the 5 one hot codes, the all zeroes and all ones. By overlapping the clocks we need 7*(5+1) + 5 = 47 clock cycles to test the chip.

Boundary Scan

Boundary-Scan Components

ChipCore

TAPController

I

O

Boundary Scan Interface Boundary scan is accessed through

five pins TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional)

Chips with internal scan chains can access the chains through boundary scan for unified test strategy.

TDI

TMS

TCK

TDO

Various TAPOutputs:

UpdateDR,CaptureDR,

TriState,Etc.

FiniteState

Machine

Instruction Register

Bypass Reg.

InstructionDecode

SOSI

TAP Controller Components

• Boundary Scan Standard has become absolutely essential --Not possible to test multi-chip

modules at all without itSupports BIST, external testing with

Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter

Now getting widespread usage

A Testability Standard

• Allows test instructions and test data to be serially fed into a CUT Allows reading out of test results Allows RUNBIST command as an instruction

Too many shifts to shift in external tests

• JTAG can operate at chip, PCB, & system levels

• Separate testing of:System interconnectsComponents

Instruction Register Loading with JTAG

System View of Interconnect

Boundary Scan Chain View

Elementary Boundary Scan Cell

Serial Board / MCM Scan

Boundary Scan Standard

Parallel Board / MCM Scan

PRSG Linear Feedback Shift Register

Shift register with input taken from XOR of state

Pseudo-Random Sequence Generator

Flo

p

Flo

p

Flo

pQ[0] Q[1] Q[2]

CLK

D D D

111 (repeats)7

0116

0015

1004

0103

1012

1101

1110

QStep

BILBO Built-in Logic Block Observer

Combine scan with PRSG & signature analysis

MODE C[1] C[0]Scan 0 0Test 0 1Reset 1 0Normal 1 1

Flo

p

Flo

p

Flo

p

1

0

D[0] D[1] D[2]

Q[0]Q[1]

Q[2] / SOSI

C[1]C[0]

PRSGLogicCloud

SignatureAnalyzer

Built-in Self-test BIST Built-in self-test lets blocks test themselves

Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it

produces the expected syndrome

Self Testing Using MISR and Parallel SRSG (STUMPS)

PRPG

MISR

SCAN PATH

SCAN PATH

SCAN PATH

PIs

POs

CUT

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IEEE 1149.1 JTAGBoundary Scan Standard

Motivation Bed-of-nails tester System view of boundary scan

hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Summary

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Bed-of-nails printed circuit board tester gone We put components on both sides of PCB &

replaced DIPs with flat packs to reduce inductance

Nails would hit components Reduced spacing between PCB wires

Nails would short the wires PCB Tester must be replaced with built-in test

delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors

Test bus identical for various components One chip has test hardware for other chips

Motivation for Standard

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Purpose of Standard Lets test instructions and test data be serially fed into a

component-under-test (CUT)

Allows reading out of test results Allows RUNBIST command as an instruction

Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from

components Lets components be tested separately from wires

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Tap Controller Signals Test Access Port (TAP) includes these signals:

Test Clock Input (TCK) -- Clock for test logic Can run at different rate from system clock

Test Mode Select (TMS) -- Switches system from functional to test mode

Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions

Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers)

Test Reset (TRST) -- Optional asynchronous TAP controller reset

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Optional / Required Instructions

Instruction

BYPASSCLAMPEXTESTHIGHZ

IDCODEINTEST

RUNBISTSAMPLE / PRELOAD

USERCODE

MandatoryOptional

MandatoryOptionalOptionalOptionalOptional

MandatoryOptional

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BYPASS Instruction

Purpose: Bypasses scan chain with 1-bit register

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Summary

Boundary Scan Standard has become absolutely essential -- No longer possible to test printed

circuit boards with bed-of-nails tester

Not possible to test multi-chip modules at all without it

Supports BIST, external testing with Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter

Now getting widespread usage