EECS150 Homework 3 Solutions Fall 2008 1.) The BCD Counterinst.cs.berkeley.edu/~cs150/fa08/Homework/Homework3Solutions.pdf · EECS150 Homework 3 Solutions Fall 2008 Page 1 of 20 1.)

EECS150 Homework 3 Solutions Fall 2008

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1.) The BCD Counter

(a) To write C1 in minterm form, we use the rows of the truth table that yield C1=1. For each row,

we write the minterm as a product of the inputs ABCD; if the input is a 0 in that row, use the

complemented form in the minterm. We get:

C1 (A, B, C, D) = m (0, 1, 2, 3, 4, 7, 8, 9)

=

ABCDABCDABCDABCDABCDABCDABCDABCD

The implementation of C1 in canonical SoP form is shown in Figure 1-1.

To write C1 in maxterm form, we use the rows of the truth table that yield C=0. The maxterm is the sum

of the inputs A+B+C+D; if the variable is a 1 in that row we use the complemented form in the maxterm.

This yields the expression:


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C1 (A, B, C, D) = M (5, 6, 10, 11, 12, 13, 14, 15)

=

(A BC D)(A BC D)(A BC D)(A B C D)

(A BC D)(A BC D)(A BC D)(A BC D)

The implementation of C1 in canonical PoS form is shown in Figure 1-2.


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(b) Use the same process outlined in part (a) to find the minterm and maxterm forms of C5.

The result for the minterm form is:

C5 (A, B, C, D) = m (0, 4, 5, 6, 8, 9)

=

ABCDABCD ABCD ABCDABCDABCD

The implementation of C5 in canonical SoP form is shown in Figure 1-3.

The result for the maxterm form is:


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C1 (A, B, C, D) = M (1, 2, 3, 7, 10, 11, 12, 13, 14, 15)

=

(A B C D)(A B C D)(A B C D)(A B C D)

(A B C D)(A B C D)(A B C D)(A B C D)

(A B C D)(A B C D)

The implementation of C5 in canonical PoS form is shown in Figure 1-4.

(c) For C1, the SoP and PoS forms each require 9 gates. Since exactly half of the inputs result in

C1=1 and the other half result in C1=0, there are exactly the same number of minterms as there are

maxterms. This means that the SoP and PoS forms both require the same number of 1st level gates (8

AND or 8 OR gates, respectively) plus one additional gate to make the C1 expression.


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For C5, however, there are only 6 rows where the output C5=1. Thus there are only 7 gates required for

the SoP form: 6 AND gates + 1 OR gate. That leaves 10 rows where the output C5=0, so the PoS form

requires 11 gates: 10 OR gates + 1 AND gate. While neither of these implementations is minimized, the

SoP form requires fewer gates because there are fewer minterms than maxterms for C5.


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2.) Typos

[Note: For this explanation, please refer to Figure 6.26 in CLD2 to see how the gates are numbered.]

Figure 6.25

The caption for this figure reads, “Negative edge-triggered D flip-flop when clock goes from high to low.”

In the figure, however, the Clock = 1. It should read “Clk = 0”. All other notations on this figure are

correct, though the output of gate number 5 could be labeled Q’ for clarity.

Figure 6.26

Here, the caption is “Negative edge-triggered D flip-flop when clock is low.” The point of this figure is to

illustrate what happens when the input D changes while the clock is held low. Since this is a negative

edge-triggered device, the output should not change in this situation.

Error #1: Again, the figure is labeled “Clk = 1”. The clock input should be “Clk = 0”.

Error #2: In figure 6.25, we see that when the clock is low, the output of gate 2 is D and the output of

gate 1 is D’. When the input D changes to Dnew, the inputs to gate 1 are D (from gate 2) and Dnew. Since

D is not equal to Dnew, the inputs to gate 1 are a 1 and a 0. Gate 1 performs the function 1 NOR 0 = 0.

Thus, the output of gate 1 should be 0.

Error #3: The output of gate 1 is fed in as an input to gate 4. This input is marked as D’, but should

be 0 (based on the explanation above).

All other notations on Figure 6.26 are correct, though the output of gate number 5 could be labeled Q’

for clarity.


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3.) CLD2 Problems

a) CLD2: 6.12

a. Master-slave R-S flip-flop

i. Inputs: 3 (Clock, R, S)

ii. First recognize that there is a master and a slave flip-flop with an inverted clock

going to the slave. Next, notice that each flip-flop looks just like an R-S flip-flop.

b. Master-slave D flip-flop

i. Inputs: 2 (Clock, D)

ii. Again, notice that there is a master and slave with an inverted clock going to the

slave. Try and follow the behavior for one flip-flop. This can also be viewed as a

master-slave J-K flip-flop where J is set to D and K is set to ~D.

c. Master-slave J-K flip-flop

i. Inputs: 2 (Clock, T)

ii. The flip-flop might be better described as a master-slave T flip-flop. However,

this is not a choice. In this case, it is a master-slave J-K flip-flop where both J and

K are set to T.

d. Clocked R-S latch

i. Inputs: 3 (Clock, R, S)

e. Positive edge D flip-flop

i. Inputs: 2 (D, Clock)

ii. Notice that this flip-flop looks very similar to the negative edge triggered D flip-

flop. However, the gates are replaced with NAND gates. By examining the

behavior of this new flip-flop, it is clear that it is triggered on the positive edge.

b) CLD2: 6.14

Show how to implement a D flip-flop starting with a J-K flip-flop:

Q Q+ J K D

0 0 0 X 0

0 1 1 X 1

1 0 X 1 0

1 1 X 0 1 Excitation table for D, J-K flip-flops (CLD Page 569).


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Any flip-flop can be implemented in terms of another flip-flop. By following the excitation table,

it is easy to see what logic is needed in order to do this. For more detailed information, see page

568 in CLD.

c) CLD2: 7.1

a. State diagram. Note that [I0, I1] is denoted as I0I1, so an input of [I0, I1] = [0, 0] is labeled as 00.

11 11

1111

00

0000

1001

1001

10 01

10

01

00

00

[00]

01

[01]

10

[10]

11

[11]

State transition table. S1 will be the most significant bit of my two-bit counter and S0 will

represent the least significant bit.

S1 S0 I0 I1 Next S1 Next S0

0 0 0 0 0 0

0 0 0 1 0 1

0 0 1 0 1 1


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0 0 1 1 1 0

0 1 0 0 0 1

0 1 0 1 1 0

0 1 1 0 0 0

0 1 1 1 1 1

1 0 0 0 1 0

1 0 0 1 1 1

1 0 1 0 0 1

1 0 1 1 0 0

1 1 0 0 1 1

1 1 0 1 0 0

1 1 1 0 1 0

1 1 1 1 0 1

From the truth table, we can arrive at these simplified sum of products boolean expressions for

Next S1 and Next S0 as a function of S1 and S0:

Next S1 = ~S1 ~S0 I0 + ~S1 S0 I1 + S1 ~S0 ~I0 + S1 S0 ~I1

Next S0 = ~S0 ~I0 I1 + ~S0 I0 ~I1 + S0 ~I0 ~I1 + S0 I0 I1

This can be implemented directly using two levels (three if you count the inverters needed to invert inputs) of logic (circuit drawn by Logisim):


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b. It is a little bit harder to implement this with only two-input gates given to us. However, we can apply DeMorgan’s Law a few times on our boolean expressions to make it easier to implement using only the gates given to us. This is very tedious, which is why we no longer asked you to go for the minimum gate count. The following implementation uses all NAND gates (drawn by Logisim):


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d) CLD2: 7.2

This question asks for a counter that is self-starting, composed of 3 flip-flops, and of a non-usual

pattern. By self-starting, the question means that if the counter were to initialize to an arbitrary 3-bit

state, it would be able to get back on track and continue counting its sequence. By 3 flip-flops, the

question means that the state of the counter should be stored in 3 bits of information.

Because the counter counts in a non-trivial pattern, we will represent the counter as a finite

state machine that non-conditionally transitions from state to state with the rising edge of the clock.

With appropriate transition logic, this state machine will accomplish exactly what a normal counter

would. In fact, all counters can be thought of as finite state machines in this way. We start with a high

level bubble-arc diagram as shown below:

000

[000]

001

[001]

011

[011]

110

[110]

100

[100]

111

[111]

010

[010]

Notice that by how we have encoded our states, the output for a given state is the same as the state

encoding. This simplifies the process of computing the outputs: the outputs are just the current state!

Also notice that we have specified a Moore machine. This is because our counter need not change its

outputs based on the current state and the inputs, but rather just the current state. When we can, we

should always use Moore machines as having synchronous outputs with the clock greatly reduces the

chance to have timing violations in our design.

The next step in the design process is to specify the state transition table. This will allow us to

construct a Sum of Products or Product of Sums canonical representation for our next state logic. Note

that you were not required to simplify the Boolean expressions resulting from this step. Karnaugh

maps, which we will soon cover, will designate a relatively simple way to perform this simplification.


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Our table is inferred directly from our bubble-arc diagram (CS is the current state and NS is the

next state):

CS NS

000

010

111

100

110

011

001

101

010

111

100

110

011

001

000

000

Notice that we have added the 101 state to our table, and that it transitions to state 000. This handles

the self-starting requirement. Specifically, if our circuit initializes to 101, which our counter does not

ever transition to and from naturally, return to 000, which is a legal state, and continue from there. Self-

starting circuits are useful for recovering from unexpected initialization problems, but can also lead to

circuits (which should have broken because of a large bug) seemingly running as expected. This is a

potential trap, and making a circuit self-starting should be done with care.

The next step is to generate a canonical form expression from the above transition table. We will use Sum of Products, however, Product of Sums can also be used. In this problem, as we have to specify the input for 3 different flip-flops, we must construct 3 different canonical form expressions (we will denote the state bits by index; i.e. if NS = 110, then NS[0] = 0, NS[1] = 1 and NS[2] = 1):

]0[]1[]2[

]0[]1[]2[

]0[]1[]2[

]2[

CSCSCS

CSCSCS

CSCSCS

NS

]0[]1[]2[

]0[]1[]2[

]0[]1[]2[

]0[]1[]2[

]1[

CSCSCS

CSCSCS

CSCSCS

CSCSCS

NS


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]0[]1[]2[

]0[]1[]2[

]0[]1[]2[

]0[

CSCSCS

CSCSCS

CSCSCS

NS

Again, you were not required to simplify these expressions.

The last step is to transform the above Boolean expressions into a combinational logic block that computes the next state. This inferred directly from the above equations. The complete counter, with this combinational logic block and the flip-flops that store the counter’s state, are shown below:

CS[2] CS[1] CS[0] !CS[2] !CS[1] !CS[0]

CS[2]

CS[1]

CS[0]

Count[2]

Count[1]

Count[0]

Clock


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5.) Digikey Problem

The best way to approach this problem is not to make up random numbers (we can tell – we’re

that good), but to sit down in front of a computer and learn how to use the Digi-Key catalogue. This

company is one of the leading US suppliers of various electronic and other components for large-scale

manufacture. Unlike most other suppliers, however, you can also buy things in very small quantities

from this store at nearly reasonable prices. Besides showing you where hardware comes from, this

problem is meant to give you a real estimate of how expensive/inexpensive hardware can be. We

encourage you to shuffle through the catalogue, find some of the parts used in the Calinx or your

computer’s motherboard. Understanding which design choices are expensive and which aren’t is an

important skill to an engineer.

That said, if you took this problem seriously, you probably found it more challenging than

expected: Digi-Key sells thousands upon thousands of similar components, yet does not allow sorting

search results by price. If you do not know exactly what you’re looking for, you may have a hard time

finding the cheapest part. Also important is the fact that Digi-Key lists parts it does not actually have.

Out-of stock parts may be difficult (or impossible) to purchase. When designing a system, you may want

to make sure you can actually buy your components and that the parts you chose have not been

obsolete for a year.

The following are essential when looking for a component:

Availability – is the item in stock? Being able to actually buy the item you want is

helpful.

Unit price – how much is one of these going to cost you?

Minimum quantity – unless you’re prepared to pay 1000x for a crate of these components,

you should pay attention to this number. For this problem, the

minimum order quantity should be 1.

Note : It’s not a problem if you have not found the absolute cheapest part. We’re looking for a sign of

effort, and will accept a broad range of prices found.

a) Here’s what we found:

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=568-3093-5-ND

This is the cheapest J-K flip-flop Digi-Key has in stock, and allows you to buy individually.

Some characteristics:

NXP Semiconductors HEF4027BTD dual posedge-triggered J-K flip-flop. $0.42 each. $550 bucks

for 5000. The word “dual” means there are two J-K flip-flops in each chip.

b) Assuming that your XCV2000Es in the Calinx have approximately (very approximately)

43,000 flip-flops, it is easy enough to realize that if you were to buy the 21,500 J-K flip-flops

one by one (they’re dual, remember?), it would set you back no less than $9,030.00.

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=568-3093-5-ND

http://ordering.digikey.com/Manufacturer.aspx?vendor=568&site=US&lang=EN


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Fortunately, due to volume pricing, the actual cost is much lower, at about $2300. You may

have noticed, however, that the store only stocks about 2500 of the dual flip flops.

Note: this is surprisingly not too far from the cost of your FPGA (~3 thousand dollars each (Digi-

Key sells them for $2,261.99, but they’ve been “out of stock” for a very long time)). Don’t get

any ideas about FPGAs being outrageously overpriced, as it is important to consider how much

space 50,000 discrete J-K flip-flops would take, their performance characteristics, not to

mention the vast amounts of other resources the FPGA provides.

c) The cheapest Xilinx FPGA we found on Digi-Key is the Spartan-II XC2S15 speed grade 5,

commercial temperature range, VQFP100 (VQG100) package. The cost of this part is $7.10

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1309-ND

Check out the package drawing here:

http://www.xilinx.com/support/documentation/package_specs/vq100.pdf

We would like to emphasize that this is a very, very small FPGA. This chip has 60 I/O pins and

less than 5 hundred logic blocks (and as few registers), whereas the XCV2000E has 512 I/O and

43,200 of logic blocks and registers.

We hope this problem has shown you that the resource you have at your disposal (The Calinx) is

an incredibly versatile platform. Using this board you can build anything from Ethernet switches

to GPUs and full-featured CPUs to oscilloscopes. We encourage you to be courageous and try

new things with the Calinx after developing the necessary skills. Make something impressive this

semester, don’t focus on flashy features.

d) To find the crossover point, find how many J-K flip-flops will cost as much as a Xilinx FPGA.

At $0.42 per dual flip-flop, only 20 parts are needed to exceed the very low $7.10. This

amounts to a total of 40 J-K flip-flops (two per package).

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1309-ND

http://www.xilinx.com/support/documentation/package_specs/vq100.pdf


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6.) Verilog Bugs

As it turns out, there was some ambiguity in this problem: part a specified that the user wanted

to create a shift register; parts b and c didn’t specify anything. For parts b and c, we just wanted you to

find the syntax errors in each Verilog fragment. The fragments didn’t necessarily do anything

interesting. The errors in b and c were either straight up compiler errors, or Verilog “pitfalls” that you

will always want to avoid (see Always.pdf and Reg.pdf).

In the following parts, code fragments indicate corrections to the original code fragments in red,

and make a comment about the correction in blue.

a) The first part is trying to represent a shift register. Instead, what the original code fragment produces is a series of parallel flip-flops. Always.pdf refers to this example explicitly: when you

want to infer registers, you must follow the rules for the always@(posedge Clock) block, namely that every reg assignment should be made with non-blocking (<=) statements. This

ensures that at the positive edge of the Clock, every reg gets set at exactly the same instant. If instead of using non-blocking assignments we use blocking assignments, what we actually get is: RegisterD = RegisterC = RegisterB = Input. This is because when

RegisterB gets set to Input, RegisterC gets set to RegisterB’s new value (by definition of the blocking (=) statement. RegisterB’s new value is Input. This same problem propagates down the flip-flop chain, and the result is either parallel flip-flops or a single

flip-flop whose output is split four-ways between RegisterB, RegisterC, and

RegisterD.

Part a: Errors and corrections

wire Input;

reg RegisterB, RegisterC, RegisterD;

always @(posedge Clock) begin

RegisterB <= Input; // from =

RegisterC <= RegisterB; // from =

RegisterD <= RegisterC; // from =

end

b) This part is an arbitrary Verilog segment. It doesn’t do anything intelligent. The errors in this part were merely syntactical, and specifically wire vs. reg issues. See Nets.pdf for more information. There are multiple ways to fix the bugs in this segment. We will discuss the two mainstream ways.

First, consider the actual bugs in the code fragment, reproduced below:

http://inst.eecs.berkeley.edu/~cs150/fa08/Documents/Always.pdf

http://inst.eecs.berkeley.edu/~cs150/fa08/Documents/Nets.pdf


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Part b: Errors

wire Input, B;


assign A = Input | RegisterC; // wire A not declared

assign RegisterB = Input & RegisterC; // RegisterB must be a wire

always@( * ) begin

B = Input | RegisterC; // B must be a reg

end

The first error deserves special recognition: if you assign a previously undeclared wire in an

assign statement, simulation/synthesis will NOT force a compiler error. Instead, the tools will

interpret that undeclared wire as a 1-bit wire and continue to use it throughout your design.

This is a large Verilog pitfall. Say, for example, that you have declared a 32-bit wire signal

named SigA. Later, you wish to assign SigA and accidentally spell it sigA. When you try to

assign sigA, you will not assign SigA, but rather assign a new 1-bit wire. As you were

probably assigning sigA a 32-bit value, sigA will take on the least-significant-bit of the 32-bit

signal you provided. Look for HiZ in your ModelSim waveform window to check for this bug.

Specifically, since you never assigned SigA, it should appear to be undriven in simulation

(which is easy to see because of the blue flat waveform that HiZ produces).

The second two errors are both reg vs. wire problems. These are less interesting because

they will cause simulation/synthesis to fail immediately (and are therefore just annoyances,

rather than major pitfalls). See Nets.pdf for more information. Two possible solutions are

shown below.

Part b: reg vs. wire fix (#1)

wire Input, A, B;


assign A = Input | RegisterC;

always@( * ) begin

RegisterB = Input & RegisterC;

end

assign B = Input | RegisterC;


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Part b: reg vs. wire fix (#2)

wire Input, A, RegisterB;

reg RegisterC, RegisterD, B;

assign A = Input | RegisterC;

assign RegisterB = Input & RegisterC;

always@( * ) begin

B = Input | RegisterC;

end

c) The final code fragment produces latches. See Always.pdf for more information. Latches are

inferred in always@( * ) blocks when a reg does not get assigned during that always@( * )

block’s “execution.” Specifically, for every possible execution of an always@( * ) block’s

control flow (taking arbitrary if/then/else/case branches, every reg must be set at least

once. If there exists a path in an always@( * ) block’s control flow that does not assign a

given reg at least once, that reg will be stored in a level-sensitive latch, causing delay/update

problems in your design. Consider the fragment below:

Part c: latch generation problem

wire Condition, Input;

reg A, B, C;

always @( * ) begin

A = 1'b0;

if (Condition) begin

B = Input;

C = Input; // if !Condition, C never gets set

end

else begin

B = Input;

end

end

There are several ways to fix this. First, we can set C to a default value like we did with A = 1’b0.

Alternatively, we can change the control flow so that in the !Condition case, C gets set to some value.

Both fixes are shown below. During synthesis, you can see if your design generated latches by opening

your synthesis report and searching for the word: “latch”.


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Part c: latch generation fix (#1)


reg A, B, C;

always @( * ) begin

A = 1’b0;

C = 1’b0; // C = 1’b1 works fine as well


B = Input;

C = Input;

end

else begin

B = Input;

end

end

Part c: latch generation fix (#2)


reg A, B, C;

always @( * ) begin

A = 1’b0;


B = Input;

C = Input;

end

else begin

B = Input;

C = 1’b0; C = 1’b1 works fine as well

end

end