SIGNAL INTEGRITY OF HIGH SPEED DIGITAL PCB DESIGNS

EECS 713 ProjectInstructor: Prof. Allen

Presented by: Chen Jia

Definition

Signal integrity (SI): is a set of measures of the quality of an electrical signal. We expect the signal can response time series, electrical level correspondingly.

Was not always a case in earlier days. Challenges for designers

Concerns: why, what, when, and how

Why

When SI happens, the noise margin requirement will not be satisfied – logic errors, false switching, system collapses, etc.

In high speed digital system, we are expecting a string that contains bits H(1) and L(0). A continuous voltage waveform. Receivers sample the signal by generating the rising and falling edge of the signal.

A Failure in catching rising or falling edge, or misreading an ambiguous logic state may result in an incomplete data transmission or even a failure of transmission.

Settle down to non-ambiguous before receiver kicks in

We want to see this

Not this

When

Delay

If the signal arrives its destination when it is supposed to.

Delay depends on the length of the transmission line and dielectric constant. In high speed digital system, the length of the transmission lines has the greatest impact of clock skew.

Clock skew: is the difference in the arrival time between two sequentially-adjacent registers

What

Parameters of PCB and components on it

The arrangement of components layout and high speed trace design

Reflection/crosstalk/power/ground noise

Electromagnetic Compatibility (EMC) Electromagnetic Interference (EMI)

How

Solution: crosstalk, reflection For crosstalk: 1. Reduce the coupling (a solid reference plane,

both ground and power plane will do) 2. Change the timing 3. Improve receiver noise margins (as we stated

before) 4. Downsize the aggressor nets (prevent large

voltages from affecting small ones, not always the case with digital logic)

5. 90 degree routing, avoid parallel layout (to minimize the impact)

6. More…

Solutions

For reflections: Happens when impedance changes

while the signal is transmitting. L> Tr/2Tpd Tpd: Transport Delay/unit length Impedance matching:

Matching

1. Parallel: load impedance matching (close to load side)

2. Series: source impedance matching (close to source side, R + Rs ≥ RL)

Summary

System requirements

Schematic

Interconnectioncomponents

selectionPhysical design

component placement

Constrain driven layout

PrototypePractical

measurementsMeet SI

requirement?

Production

Reference

http://www.csee.umbc.edu/csee/research/vlsi/

http://www.cc362.com/article/44852226.html

http://www.mr-wu.cn/signal-integrity-analysis-for-high-speed-digital-pcb/

http://www.sigcon.com/Pubs/news/6_01.htm

Thank you !