EECE 353: Digital Systems DesignLecture 8: Counters & Timing

Cristian Grecugrecuc@ece.ubc.ca

Course web site: http://courses.ece.ubc.ca/353/

Lecture 8, Page 2

Part 1: Counters

So now we know how to design with flip-flops, and weknow how to specify such circuits in VHDL.

Using the state machine design techniques you learned in second year, you can design any state machine, and given what we talkedabout in the last slide set, you can describe any of them in VHDL.

However, there are some very common sequential circuits that areused so often, they are worth talking about separately.

- Shift Registers- Counters- Linear-Feedback Shift Registers (LFSR’s)

Textbook: Sections 7.8 - 7.12

Lecture 8, Page 3

Shift Registers

Each cycle, shift contents of this register by one bit:

In Q1 Q2 Q3 Q4

cycle 0 1 0 0 0 0cycle 1 0 1 0 0 0cycle 2 1 0 1 0 0cycle 3 1 1 0 1 0cycle 4 0 1 1 0 1cycle 5 0 0 1 1 0

Lecture 8, Page 4

entity shift isport( clk, insig : in std_logic;

outsig : out std_logic;end shift;

architecture behavioural of shift isbegin

process (clk)variable int_value : std_logic_vector (3 downto 0);begin

if (clk='1' and clk'event) thenint_value := insig & int_value(3 downto 1);outsig <= int_value(0);

end if;end process;

end behavioural;

Lecture 8, Page 5

Shift Register with Parallel Input

If LOAD = 1: Loads a 4-bit value into the registerIf LOAD = 0: Operates as a normal shift register

Lecture 8, Page 6

entity pshift isport( clk, insig, load : in std_logic;

parallel_in : in std_logic_vector (3 downto 0);outsig : out std_logic;

end pshift;

architecture behavioural of pshift isbegin

process (clk)variable int_value : std_logic_vector (3 downto 0);begin

if (clk='1' and clk'event) thenif (load = ‘1’) then

int_value := parallel_in;else

int_value := insig & int_value(3 downto 1);end if;outsig <= int_value(0);

end if;end process;

end behavioural;

Lecture 8, Page 7

CountersThere are several types of counters:

- Binary counter- BCD counter- Ring counter- Johnson counter- Linear Feedback Shift Register

Each of these can be designed as a state machine, using techniquesyou learned last year. But they are so common, it’s worth talking about (some of) them.

Why use counters?- Produce a time delay (count to N)- As a controller stepping through instructions (Program COUNTER –

a.k.a. PC)

Lecture 8, Page 8

Binary Counter

Count in the “normal” sequence

Exercise: using techniques from last year, make a state machineto implement this

Lecture 8, Page 9

This shows a simple way to implement the binary counter.

Lecture 8, Page 10

entity count4 isport( clk, enable : in std_logic;

count : out std_logic_vector(3 downto 0));end count4;

architecture behavioural of count4 isbegin

process (clk)variable int_value : std_logic_vector (3 downto 0);begin

if (clk='1' and clk'event) thenif (enable = ‘1’) then

int_value := int_value + 1;end if;

end if;count <= int_value;

end process;end behavioural;

What sort of adder?

Signed? Unsigned?

Lecture 8, Page 11

Option 1:At the top of your file include one of:

library IEEE ; library IEEE;use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; use IEEE.std_logic_signed.all;

Option 2:Rather than using std_logic_vector, use type signed or unsigned

….variable int_value : unsigned (3 downto 0);.....

Lecture 8, Page 12

Same thing, but with a parallel-load capability (if you can’t read this, look at Fig. 7.25 in the textbook)

Good exercise: Specify this in VHDL (behavioural, *not* structural)

Lecture 8, Page 13

Suppose we want to make a counter that counts from 0 to 5, then goesback to 0 (this is called a modulo-6 counter)

Alternative 1: Construct a state machine using normal techniquesAlternative 2:

Use our counter from the previous slide. When the counter reachesfive, force the count back to 0.

Lecture 8, Page 14

Modulo-6 Counter:

This will detect “101”. When the counter is 101, the counter will be loaded with 000 on the next rising clock edge

Lecture 8, Page 15

Slight simplification:

Under normal operation, the counter will never pass through 111

So, we really only need to check the first and third bits

Lecture 8, Page 16

Lecture 8, Page 17

BCD Counters

A BCD Counter is nothing more than a modulo-10 counter.0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, …

Exercise (try at home):

Easy: Design a 4-bit BCD counter

More Challenging:Design an 8-bit BCD counter

- lower order 4 bits count 0 to 9 then back to 0- upper order 4 bits also count 0 to 9 then back to 0

- upper order bits increment each timelower order bits roles over from 9 to 0

Lecture 8, Page 18

Problem with Binary Counters:

Length of one clock period is the length of the longest path between flip-flops.

Length of one clock period is proportional to number of bits

Lecture 8, Page 19

One-Hot Counter

Count:100000000 > 01000000 > 00100000 > etc.

Advantage: - fast counting- sometimes, downstream logic is simpler

Disadvantage: - more flip-flops

Lecture 8, Page 20

One-Hot CounterInitialization: initialize one flip-flop to 1, and the others to 0

Lecture 8, Page 21

Linear Feedback Shift Register

Count Sequence:0000 -> 1000 -> 1100 -> 1110 -> 0111 -> 1011 ->

1101 -> 0110 -> 0011 -> 1001 -> 0100 ->1010 -> 0101 -> 0010 -> 0001 -> repeat

Counts through 15 numbers, but in a strange order

Lecture 8, Page 22

Linear Feedback Shift Register

An n bit LFSR counts through 2n-1 numbers(always one “dead” state, just avoid it. On the previous slide,the “dead” state is 1111).

Advantage: - Fast and small

Disadvantage:- If you need to count in a natural sequence, this won’t do it

- But sometimes, all that matters is to count to a knownvalue, the actual intermediate output values don’t matter

Another use of LFSR’s: pseudo-random number generators

Lecture 8, Page 23

Lecture 8, Page 24

entity lfsr4 isport( clk, reset : in std_logic;

count : out std_logic_vector(3 downto 0));end lfsr4;

architecture behavioural of lfsr4 isbegin

process (clk, reset)variable int_value : std_logic_vector (3 downto 0);begin

if (reset =‘1’) thenint_value := “0000”;

else if (clk='1' and clk'event) thenint_value := not (int_value(1) xor int_value(0)) &

int_value(3 downto 1);end if;count <= int_value;

end process;end behavioural;

Lecture 8, Page 25

Comparison of a 64-bit LFSR and 64-bit counter on our Altera device:

Area: about the same

Speed: binary counter: 151 MhzLFSR: 420 Mhz

- limited by other parts of the chip

Lecture 8, Page 26

Summary of Part 1

We talked about:- Shift Registers- Counters

- Binary Counters- BCD Counters- One Hot Counters

- Linear Feedback Shift Registers

Important point: These are simple subcircuits that you will use a lot in your digital design career.

Lecture 8, Page 27

EECE 353: Digital Systems DesignLecture 8, part 2: Timing of Synchronous Circuits

Cristian Grecugrecuc@ece.ubc.ca

Course web site: http://courses.ece.ubc.ca/353/

Lecture 8, Page 28

Part 2: Timing

We have seen in the lab that there is some relationship between gate delay, operating frequency, and circuit topology.

In this slide set, we will clear all that up. This is also importantwhen we start talking about datapathand ALU design, since we will beconcerned about the “speed” ofthe circuits we design.

This is fairly simple stuff, but you might not have seen it explicitly before

Lecture 8, Page 29

What is the longest delay in this combinational circuit?Assume the delay of each gate is 1ns

The longest delay is the delay of the longest path between any input and any output.

0

0

0

0

1

1 2

3

3

4

4

5

Longest delay = 5 ns

Lecture 8, Page 30

In other words, in the previous circuit, if we apply all inputs at time 0, then by time 5, all the outputs have settled to their final values.

Note: 1. Some outputs might settle earlier2. Some outputs may switch back and forth a few times before

settling to a final value

Lecture 8, Page 31

Add flip-flops to inputs and outputs:

Clock goes from 0 to 1 at time 0. Assuming no delay in the flip-flop, the outputs of each of the first four flip-flops go high at t=0.

Some time later, the clock goes high again, and latches data into the output flip-flops. This can happen any time >= 5.

Lecture 8, Page 32

In the previous slide, the minimum clock period (time between rising clock edges is 5 ns).

Therefore, maximum clock frequency is 1 / 5ns = 200 Mhz

In general, you find the maximum delay from any flip-flop output toany flip-flop input. This path is called the critical path of the circuit.The delay of the critical path dictates the maximum frequency ofyour circuit:

max freq = 1 / (delay of critical path)

Lecture 8, Page 33

Critical path is longest path between flip-flop output and flip-flop input.

In this case, it is 5 ns. So the maximum frequency of this circuit is 200Mhz

Lecture 8, Page 34

What happens if you run the clock slower?

Works fine. The maximum clock period is infinity (minimum frequency = 0)

So, if the maximum clock frequency is fmax, the circuit will work for any clock frequency between 0 and fmax.

Lecture 8, Page 35

Board notes: Glitches

Lecture 8, Page 36

Lecture 8, Page 37

Set-Up TimeBefore, I told you that tcp <= tcycle

But really, data must arrive at the D input of the FF a bit early

So, more accurate to say tcp <= tcycle -tsu

Lecture 8, Page 38

clk-to-Q delay of a flip-flopAfter a rising clock edge, it takes a small amount of time, tclk to Q, for the output of a flip-flop to appear on Q

So, more accurate to say tcp <= tcycle – tclk to Q – tsu

Or: tcp + tclk to Q + tsu <= tcycle

Lecture 8, Page 39

Hold time of a flip-flopFor a short time after the rising clock edge, the D input must notchange. This “short time” is denoted thold

If the shortest delay through the combinational path is faster than thold, we might have a problem. But, this is rarely the case. Anyway, in practice, thold is often 0

Lecture 8, Page 40

Board Notes: Metastability

Lecture 8, Page 41

1. No timing violation occurs, and the output moves to the appropriate state (high or low).

2. A timing violation does occur, and the output oscillates between the valid states (for a long time).

3. A timing violation does occur, and the output moves to the wrong state.

4. A timing violation does occur, and the propagation delay is increased. Causes the next device in the chain to see the wrong value.

5. A timing violation does occur, and no meta-stable behaviour occurs. The output moves to the correct state with no oscillation or increase in propagation delay.

Lecture 8, Page 42

Summary of Part 2

Most digital circuits operate this way:- Rising clock edge causes all flip-flop to produce a value on Q- These values propagate through combinational logic (this is

the “computation” of the circuit)- By the *next* rising clock edge, the computation is done, and

values are ready to be read into the next flip-flop

Some systems operate differently- Multiple clocks for different parts of the circuit (EECE 479)- No clock at all (asynchronous – later in this course!)

Rep

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