EE415 VLSI Design

DYNAMIC LOGIC

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design

Dynamic CMOS

In static circuits the output is connected to either GND or VDD via a low resistance path.» fan-in of n requires 2n (n N-type + n P-type)

devices

Dynamic circuits use temporary storage of signal values on the capacitance of high impedance nodes.» requires on n + 2 (n+1 N-type + 1 P-type)

transistors

EE415 VLSI Design

Dynamic Gate

In1

In2 PDN

In3

Me

Mp

Clk

Clk

Out

CL

Out

Clk

Clk

A

BC

Mp

Me

Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

on

off

1

off

on

((AB)+C)

EE415 VLSI Design

Conditions on Output

Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

EE415 VLSI Design

Properties of Dynamic Gates

Logic function is implemented by the PDN only» number of transistors is N + 2 (versus 2N for static complementary

CMOS)

Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect

the logic levels Faster switching speeds

» reduced load capacitance due to lower input capacitance (Cin)

» reduced load capacitance due to smaller output loading (Cout)

» no Isc, so all the current provided by PDN goes into discharging CL

EE415 VLSI Design

Properties of Dynamic Gates

Overall power dissipation usually higher than static CMOS» no static current path ever exists between VDD and GND

(including Psc)» no glitching» higher transition probabilities» extra load on Clk

PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn

» low noise margin (NML)

Needs a precharge/evaluate clock

EE415 VLSI Design

Issues in Dynamic Design 1: Charge Leakage

CL

Clk

Clk

Out

A

Mp

Me

Leakage sources

CLK

VOut

Precharge

Evaluate

Leakage is dominated by the subthreshold current

EE415 VLSI Design

Solution to Charge Leakage

CL

Clk

Clk

Me

Mp

A

B

Out

Mkp

Same approach as level restorer for pass-transistor logic

Keeper

EE415 VLSI Design

Issues in Dynamic Design 2: Charge Sharing

CL

Clk

Clk

CA

CB

B=0

A

OutMp

Me

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

EE415 VLSI Design

Charge Sharing Example

CL=50fF

Clk

Clk

A A

B B B !B

CC

Out

Ca=15fF

Cc=15fF

Cb=15fF

Cd=10fF

EE415 VLSI Design

Charge Sharing

Mp

Me

VDD

Out

A

B = 0

CL

Ca

Cb

Ma

Mb

X

CLVDD CLVout t Ca VDD VTn VX – +=

or

Vout Vout t VDD–CaCL-------- VDD VTn VX

– –= =

Vout VDD

CaCa CL+----------------------

–=

case 1) if Vout < VTn

case 2) if Vout > VTnB0

Clk

X

CL

Ca

Cb

A

Out

Mp

Ma

VDD

Mb

Clk Me

as CL VDD=CL VOUT + Ca VOUT

VOUT = VDD CL / (CL+Ca)

Vx increases up to VDD-VTn

when Ca is small comparing to CL

Vx increases less up to VOUT

when Ca is larger

Assume that initial voltage Vx=0 and Vout=VDD

EE415 VLSI Design

Solution to Charge Redistribution

Clk

Clk

Me

Mp

A

B

OutMkp

Clk

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

EE415 VLSI Design

Issues in Dynamic Design 3: Backgate Coupling

CL1

Clk

Clk

B=0

A=0

Out1Mp

Me

Out2

CL2 In

Dynamic NAND Static NAND

=1

When In goes up from 0 to VDD, output of static NAND gate (Out2) goes down from VDD to 0 and pulls down Out1 through the capacitive coupling

EE415 VLSI Design

Backgate Coupling Effect

-1

0

1

2

3

0 2 4 6

Vol

tage

Time, ns

Clk

In

Out1

Out2

EE415 VLSI Design

Issues in Dynamic Design 4: Clock Feed Through

CL

Clk

Clk

B

A

OutMp

Me

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD.

The fast rising (and falling edges) of the clock couple to Out.

EE415 VLSI Design

Clock Feed Through

-0.5

0.5

1.5

2.5

0 0.5 1

Clk

Clk

In1

In2

In3

In4

Out

In &Clk

Out

Time, ns

Vol

tage

Clock feed through

Clock feed throughMore noise is generated as a result of clock coupling

EE415 VLSI Design

Other Effects

Capacitive coupling between output wires pulls down prestored charges

Substrate coupling Minority charge injection Supply noise (negative ground bounce

may discharge the output)

EE415 VLSI Design

Cascading Dynamic Gates

Clk

Clk

Out1

In

Mp

Me

Mp

Me

Clk

Clk

Out2

t

V

Clk

In

Out1

Out2V

VTn

Only 0 1 transitions allowed at inputs!So do not connect these gates directly

Output signal loss

EE415 VLSI Design

Domino Logic

In1

In2 PDN

In3

Me

Mp

Clk

ClkOut1

In4 PDN

In5

Me

Mp

Clk

ClkOut2

Mkp

1 11 0

0 00 1

Here we guarantee proper 0 to 1 transitions between gates

EE415 VLSI Design

Why Domino?

Clk

Clk

Ini PDNInj

Ini

Inj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

EE415 VLSI Design

Properties of Domino Logic

Only non-inverting logic can be implemented Very high speed

» static inverter can be skewed, only L-H transition so make PMOS of inverter stronger» Input capacitance reduced

so smaller logical effort

EE415 VLSI Design

Designing with Domino Logic

Mp

Me

VDD

PDN

Clk

In1

In2

In3

Out1

Clk

Mp

Me

VDD

PDN

Clk

In4

Clk

Out2

Mr

VDD

Inputs = 0during precharge

Can be eliminated! but be aware of the short circuit path from delayed clock

EE415 VLSI Design

Footless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentA solution is to delay the clock for each stage

VDD

Clk Mp

Out1

In1

1 0

VDD

Clk Mp

Out2

In2

VDD

Clk Mp

Outn

InnIn3

1 0

0 1 0 1 0 1

EE415 VLSI Design

Differential (Dual Rail) Domino

A

B

Me

Mp

Clk

ClkOut = AB

!A !B

MkpClk

Out = ABMkp Mp

Solves the problem of non-inverting logic

1 0 1 0

onoff

EE415 VLSI Design

np-CMOS

Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

In1

In2 PDN

In3

Me

Mp

Clk

ClkOut1

In4 PUN

In5

Me

MpClk

Clk

Out2(to PDN)

1 11 0

0 00 1

Possible coupling in longer runs to dynamic node

EE415 VLSI Design

NORA Logic

WARNING: Very sensitive to noise!

In1

In2 PDN

In3

Me

Mp

Clk

ClkOut1

In4 PUN

In5

Me

MpClk

Clk

Out2(to PDN)

1 11 0

0 00 1

to otherPDN’s

to otherPUN’s

use np-CMOS blocks