EE213 Digital Integrated Circuits II Lecture 03-A ...EE213 Digital Integrated Circuits II Lecture 03-A: Manufacturing Primer Prof. Pingqiang Zhou ... Modern Semiconductor Devices for

EE213 L03A Manufacturing.1 Pingqiang, ShanghaiTech, 2017

EE213Digital Integrated Circuits II

Lecture 03-A: Manufacturing Primer

Prof. Pingqiang Zhou

http://sist.shanghaitech.edu.cn/faculty/zhoupq/Teaching/Spr17/Digital-IC-2.html

Chapte

r 2

Chapte

r 1&

15

http://sist.shanghaitech.edu.cn/faculty/zhoupq/Teaching/Spr17/Digital-IC-2.html


More Resources

EE 130/230A @UC Berkeley

EE143 @UC Berkeley

http://inst.eecs.berkeley.edu/~ee130/sp13/

https://inst.eecs.berkeley.edu/~ee143/fa16/lectures.html


A Brief History

1958: First integrated circuit

Flip-flop using two transistors

Built by Jack Kilby at Texas Instruments

2010

Intel Core i7 mprocessor

- 2.3 billion transistors

64 Gb Flash memory

- > 16 billion transistors

Courtesy Texas Instruments

[Trinh09]

© 2009 IEEE


EEOL and BEOL

http

s://e

n.w

ikip

edia

.org

/wik

i/Fro

nt_

end_

of_

line

http

s://e

n.w

ikip

edia

.org

/wik

i/Back_

end

_of_

line

https://en.wikipedia.org/wiki/Front_end_of_line

https://en.wikipedia.org/wiki/Back_end_of_line


Outline

A. MOS transistors

B. Fabrication

C. Packaging



Silicon Lattice

Transistors are built on a silicon substrate

Silicon is a Group IV material

Forms crystal lattice with bonds to four neighbors

Si SiSi

Si SiSi

Si SiSi


Dopants

Silicon is a semiconductor

Pure silicon has no free carriers and conducts poorly

Adding dopants increases the conductivity

Group V: extra electron (n-type)

Group III: missing electron, called hole (p-type)


p-n Junctions

A junction between p-type and n-type semiconductor forms a diode.

Current flows only in one direction


Transistor Types

Bipolar transistors

npn or pnp silicon structure

Small current into very thin base layer controls large currents between emitter and collector

Base currents limit integration density

Metal Oxide Semiconductor (MOS) Field Effect Transistors

nMOS and pMOS MOSFETS

Voltage applied to insulated gate controls current between source and drain

Low power allows very high integration

https://en.wikipedia.org/wiki/Transistor

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+Body

https://en.wikipedia.org/wiki/Transistor


Transistors as Switches

We can view MOS transistors as electrically controlled switches

Voltage at gate controls path from source to drain

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFFON

ONOFF

VDD

A Y

GND


nMOS Transistor

Four terminals: gate, source, drain, body

Gate – oxide – body stack looks like a capacitor

Gate and body are conductors

SiO2 (oxide) is a very good insulator

Called metal – oxide – semiconductor (MOS) capacitor

Even though gate is no longer made of metal*

* Metal gates are returning today!

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+Body

Polysilicon Aluminum


nMOS Operation

Body is usually tied to ground (0 V)

When the gate is at a low voltage:

P-type body is at low voltage

Source-body and drain-body diodes are OFF

No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S


nMOS Operation Cont.

When the gate is at a high voltage:

Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type

Now current can flow through n-type silicon from source through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

ox

Bssub

BfbtC

qNVV

222

+ for P-body,

– for N-body

Modern Semiconductor Devices for Integrated Circuits (C. Hu)


pMOS Transistor

Similar, but doping and voltages reversed

Body tied to high voltage (VDD)

Gate low: transistor ON

Gate high: transistor OFF

Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+


Outline

A. MOS transistors

B. Fabrication

C. Packaging


Schematic vs. Layout

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

See http://www.vlsi-expert.com/2014/11/cmos-layout-design.html

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S


CMOS Fabrication: Inverter Cross-section

Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called Shottky Diode (https://en.wikipedia.org/wiki/Schottky_diode)

Use heavily doped well and substrate contacts/taps

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell

tap

n+ p+


The Fabs

Chips are built in huge factories called fabs

Contain clean rooms as large as football fields

Courtesy of International

Business Machines Corporation.

Unauthorized use not permitted.


Growing the Silicon Ingot

From Smithsonian, 2000


CMOS Process at a Glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

Built (roughly) from the bottom up

1. metal 2

2. metal 1

3. polysilicon

4. source and drain diffusions

5. tubs (aka wells, active areas)

One full photolithographysequence per layer (mask)

n+

p substrate

p+

n well

n+p+ n+ p+


oxidationoptical

mask

process

step

photoresist coatingphotoresist

removal

(ashing)

spin, rinse,

dryacid etch

photoresist

development

stepper

exposure

Photolithographic Process


Patterning - Photolithography

1. Oxidation

2. Photoresist (PR) coating

3. Stepper exposure

4. Photoresist development and bake

5. Acid etchingUnexposed (negative PR)Exposed (positive PR)

6. Spin, rinse, and dry

7. Processing stepIon implantationPlasma etchingMetal deposition

8. Photoresist removal (ashing)

mask

SiO2 PR

UV light


Planarization (CMP): Polishing the Wafers

From Smithsonian, 2000


Photoresist overview

There are two types of photoresist:• Positive: exposed area removed by

developer.• Negative: unexposed area removed

by developer.

Mask

Positive ResistNegative Resist

Photoresist is a liquid mixture that can be spun onto a substrate, exposed and

developed into a pattern for subsequent processing.

Typically consists of 3 components:• Resin - a binder that provides mechanical properties (adhesion, chemical

resistance…).• Sensitizer - photoactive compound.• Solvent – e.g. n-butyl acetate, xylene, keep the resist in a liquid form for spin

coating. Its content determines viscosity and hence resist thickness.

Cr

resist

Photoresist


Photomasking

[Kahng]


Mask Cost vs. Engineering Cost for ASIC


Inverter Mask Set (Top View)

Transistors and wires are defined by masks

Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap



Detailed Mask Views

Six masks

n-well

Polysilicon

n+ diffusion

p+ diffusion

Contact

Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

GND VDD

Y

A

substrate tap well tap



Fabrication Steps - Converter

Start with blank p-type wafer

Build inverter from the bottom up

First step will be to form the n-well

p substrate

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell

tap

n+ p+


1. Oxidation

Grow SiO2 on top of Si wafer

900 – 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2


2. Photoresist

Spin on photoresist

Photoresist is a light-sensitive organic polymer

p substrate

SiO2

Photoresist


3. Lithography

Expose photoresist through n-well mask

Strip off photoresist defined by n-well mask

p substrate

SiO2

Photoresist


4. Etch

Etch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist


5. Strip Photoresist

Strip off remaining photoresist

Use mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step

p substrate

SiO2


6. n-well

n-well is formed with diffusion or ion implantation

Diffusion

Place wafer in furnace with arsenic (As) gas

Heat until As atoms diffuse into exposed Si

Ion Implanatation

Blast wafer with beam of As ions

Ions blocked by SiO2, only enter exposed Si

n well

SiO2


7. Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series of steps

p substrate

n well

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell

tap

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1


Polysilicon

Deposit very thin layer of gate oxide

< 20 Å (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4)

Forms many small crystals called polysilicon

Heavily doped to be good conductor

Thin gate oxide

Polysilicon

p substraten well


Polysilicon Patterning

Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well


Self-Aligned Process

Use oxide and masking to expose where n+ dopants should be diffused or implanted

N-diffusion forms nMOS source, drain, and n-well contact

p substraten well

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell

tap

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1


N-diffusion

Pattern oxide and form n+ regions

Self-aligned process where gate blocks diffusion

Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

p substraten well

n+ Diffusion


N-diffusion cont.

Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion

n wellp substrate

n+n+ n+


N-diffusion cont.

Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tapwell

tap

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1


P-Diffusion

Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+


Contacts

Now we need to wire together the devices

Cover chip with thick field oxide

Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact


Metalization

Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal


Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole


Layout

Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)

Feature size f = distance between source and drain

Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Absolute dimensions (micron rules)

Scalable design rules: l parameter

- Express rules in terms of l = f/2

- E.g. l = 0.3 mm in 0.6 mm process

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’


Simplified Design Rules

Conservative rules to get you started


Why Have Design Rules?

To be able to tolerate some level of fabrication errors such as

• Mask misalignment

• Dust

“Interlayer defects include missing material in the vias between two metal layers or between a metal layer and polysilicon; and extra material between the substrate and metal (or diffusion or polysilicon) or between two separate metal layers. These interlayer defects occur as a result of local contamination, e.g., dust particles.”

Isreal Koren and Zahava Koren, “Defect tolerance in VLSI circuits: Techniques and Yield analysis”, Proc of the IEEE, vol. 86, no. 9, pp. 1819-1836, Sept. 1998.

• Process parameters (e.g., lateral diffusion)

• Rough surfaces


Inverter Layout

Transistor dimensions specified as Width / Length

Minimum size is 4l/2l, sometimes called 1 unit

In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long


Summary

MOS transistors are stacks of gate, oxide, silicon

Act as electrically controlled switches

Build logic gates out of switches

Draw masks to specify layout of transistors

Now you know everything necessary to start designing schematics and layout for a simple chip!


Outline

A. MOS transistors

B. Fabrication

C. Packaging


Packaging Requirements

Electrical: Low parasitics

Mechanical: Reliable and robust

Thermal: Efficient heat removal

Economical: Cheap


56

Bonding Techniques – Wire Bonding

Lead Frame

Substrate

Die

Pad

Wire Bonding


Bonding Techniques – Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers


58

Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount



Next Lecture and Reminders

Next lecture

Advanced MOS fabrication

Reminders

Guest lecture topics will be posted by this Wed.

HW1 will be posted this week.

Set up HSPICE/Layout environment ASAP.

Chapte

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EE213 Digital Integrated Circuits II Lecture 03-A ...EE213 Digital Integrated Circuits II Lecture 03-A: Manufacturing Primer Prof. Pingqiang Zhou ... Modern Semiconductor Devices for