Ee202 Digital Electronic

EE202 DIGITAL ELECTRONIC

© Copyright 2000 Indiana University Board of Trustees

1

CHAPTER 1:

Number and Code Systems

http://modul2poli.blogspot.com/


2

Course Learning Outcomes, CLO

CLO 1 :

perform the conversion of number systems

correctly.



SUMMARY

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NUMBER AND CODE SYSTEMS

Decimal,

binary,

octal and

hexadecimal number systems;

Two’s complement systems;

BCD 8421 and ASCII Code.



Introduction to Numbering Systems

4

We are all familiar with the decimal number system (Base 10). Some other number systems that we will work with are: Binary Base 2 (N2 )

Octal Base 8 (N8 )

Hexadecimal Base 16 (N16 ) http://modul2poli.blogspot.com/


Characteristics of Numbering

Systems

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1) The digits are consecutive.

2) The number of digits is equal to the size of the base.

3) Zero is always the first digit.

4) The base number is never a digit.

5) When 1 is added to the largest digit, a sum of zero and a carry of one results.

6) Numeric values determined by the have implicit positional values of the digits.



Significant Digits

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Binary: 11101101

Most significant digit Least significant digit

Hexadecimal: 1D63A7A

Most significant digit Least significant digit



Decimal Number System (N10 )

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In the decimal number system each of the ten digits

( 0,1,2,3,4,5,6,7,8,9) represents a certain quantity.

The various digits in in appropriate positions within a

number to indicate the magnitude of the quantity.



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The digit 2 has a weight The digit 3 has a weight

of 10 in this position. of 1 in this

position.

2 3

2X10 + 3X1

20 + 3

23



9

The position of each digit in decimal

number indicates the magnitude of the

quantity represented and can be assigned a

weight.

The weight for whole numbers are positive

powers-of-ten that increase from right to

left, beginning with 100 = 1.

….. 105 104 103 102 101 100



10

For fractional numbers, the weight are

negative powers-of-ten that decrease from

left to right beginning with 10-1 = 0.1

102 101 100 . 10-1 10-2 10-3 …..

Decimal point



Example 1

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Express the decimal number 47 as a sum of the

values of each digit.

Solution:

47 = (4 X 101) + (7 X 100)

= (4 X 10) + (7 X 1)

= 40 + 7

= 47 http://modul2poli.blogspot.com/


Example 2

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Express the decimal number 568.25 as a sum of the values of

each digit.

Solution:

568.25 = (5 X 102) + (6 X 101) + (8 X 100)

+ (2 X 10-1) + (5 X 10-2)

= (5 X 100) + (6 X 10) + (8 X 1)

+ (2 X 0.1) + (5 X 0.01)

= 500 + 60 + 8 + 0.2 + 0.05

= 568.25



Binary Number System (N2 )

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Also called the “Base 2 system”

The binary number system is used to model

the series of electrical signals computers use

to represent information

0 represents the no voltage or an off state

1 represents the presence of voltage or an

on state



Binary Numbering Scale

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Base 2 Number Base 10 Equivalent Power Positional Value

000 0 20 1

001 1 21 2

010 2 22 4

011 3 23 8

100 4 24 16

101 5 25 32

110 6 26 64

111 7 27 128



Decimal to Binary Conversion

(N10 N2 )

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The easiest way to convert a decimal number to

its binary equivalent is to use the Division

Algorithm

This method repeatedly divides a decimal number

by 2 and records the quotient and remainder

The remainder digits (a sequence of zeros and

ones) form the binary equivalent in least

significant to most significant digit sequence



Example 3

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Convert the following decimal numbers to binary:

1910 ( N10 N2 )

Solution: REMAINDER

2 19

2 9 1

2 4 1

2 2 0

2 1 0

2 0 1

1 0 0 1 1

MSB LSB



Example 4

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Convert the following decimal numbers to binary: 0.312510 .(N2 N10 )

Solution: MSB LSB

. 0 1 0 1

CARRY 0.3125 X 2 = 0.625 0

0.625 X 2 = 1.25 1

0.25 X 2 = 0.50 0

0.50 X 2 = 1.00 1



Binary to Decimal Conversion

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The easiest method for converting a binary

number to its decimal equivalent is to use

the Multiplication Algorithm

Multiply the binary digits by increasing

powers of two, starting from the right

Then, to find the decimal number

equivalent, sum those products



Example 5

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Determine the decimal value of the binary whole number 11011012.

(N2 N10 )

Solution:

Weight: 26 25 24 23 22 21 20

Binary number : 1 1 0 1 1 0 1

1101101 = 26 + 25 + 23 + 22 + 20

= 64 + 32 + 8 + 4 + 1

= 109



Example 6

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Determine the decimal value of the binary whole number 0.10112.

(N2 N10 )

Solution:

Weight: 2-1 2-2 2-3 2-4

Binary number : 0. 1 0 1 1

0.1011 = 2-1 + 2-3 + 2-4

= 0.5 + 0.125 + 0.0625

= 0.6875



Octal Number System (N8 )

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Also known as the Base 8 System

Uses digits (0,1,2,3,4,5,6, 7)

Readily converts to binary

Groups of three (binary) digits can be used to represent each octal digit

Also uses multiplication and division algorithms for conversion to and from base 10



Octal to Binary Conversion

(N8 N2 )

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Each octal number converts to 3 binary digits

To convert 6538 to binary, just

substitute code:

6 5 3

110 101 011



Binary to Octal Conversion

(N2 N8 )

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3 binary digit converts to 1 octal numbers

To convert 1101010112 to octal, just

substitute code:

110 101 011

6 5 3



Substitution Code

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Substitution code can also be used to convert

binary to octal by using 3-bit groupings:

010 101 101 010 111 001 101 010

2 5 5 2 7 1 5 2



Decimal to Octal Conversion

(N8 N2 )

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Convert the decimal numbers to octal:

Solution: REMAINDER

8 359 = 44.875 0.875 X 8 = 7

8 44 = 5.5 0.5 X 8 = 4

8 5 = 0.625 0.625 X 8 = 5

Stop when whole number Octal number 5 4 7

quotient is zero.

359 = 5478 http://modul2poli.blogspot.com/


Octal to Decimal Conversion

(N8 N10 )

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Determine the decimal value of the octal whole number 23748.

(N8 N10 )

Solution:

Weight: 83 82 81 80

Binary number : 2 3 7 4

23748 = ( 2 X 83 ) + ( 3 X 82 ) + ( 7 X 81 ) + ( 4 X 80 )

= ( 2 X 512 ) + ( 3 X 64 ) + ( 7 X 8 ) + ( 4 X 1 )

= 1024 + 192 + 56 + 4

= 127610



Hexadecimal Number System

(N16 )

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Base 16 system

Uses digits 0-9 &

letters A,B,C,D,E,F

Groups of four bits

represent each

base 16 digit



Decimal to Hexadecimal Conversion

(N10 N16 )

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Convert the decimal numbers to hexadecimal:

650 (N10 N16 )

Solution: REMAINDER

16 650 = 40.625 0.625 X 16 = A

16 40 = 2.5 0.5 X 16 = 8

16 2 = 0.125 0.125 X 16 = 2

Stop when whole number hexadecimal number 2 8 A

quotient is zero.

650 = 28A16 http://modul2poli.blogspot.com/


Hexadecimal to Decimal

Conversion (N16 N10 )

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Determine the decimal value of the hexadecimal whole number E516.

Solution: (N16 N10 )

Weight: 161 160

Binary number : E 5

E516 = ( E X 161 ) + ( 5 X 160 )

= ( 14 X 16 ) + ( 5 X 1 )

= 224 + 5

= 22910



Binary to Hexadecimal

Conversion (N16 N10 )

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The easiest method for converting binary to

hexadecimal is to use a substitution code

Each hex number converts to 4 binary digits



Substitution Code

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Convert 0101011010101110011010102 to

hex using the 4-bit substitution code :

(N2 N16 )

0101 0110 1010 1110 0110 1010

5 6 A E 6 A

56AE6A16



Binary Addition

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4 Possible Binary Addition Combinations:

(1) 0 (2) 0

+0 +1

00 01

(3) 1 (4) 1

+0 +1

01 10

Sum Carry

Note that leading

zeroes are frequently

dropped.



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Illustrated the following addition of 11 + 1

= …… Carry Carry

1 1

0 1 1

+ 0 0 1

1 0 0



Positive and Negative numbers

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Several methods can be used :-

Positive only i.e. unsigned

E.g an 8 bit binary number can represent 28 or 256 different binary patterns or

numbers. Range 00000000 (010) to 11111111(25510)

What is the range of values for 16-bit values?

Positive & negative

Use most significant bit :-

0 – indicates a positive number

1 – indicates a negative number

The remaining bits hold the value

This method makes arithmetic very difficult!

1’s Complement

Negative numbers are the complement (0 -> 1, 1 -> 0) of the positive value. 7

Again arithmetic is not easy with 1’s complement numbers. http://modul2poli.blogspot.com/


Complementary Arithmetic

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1’s complement

Switch all 0’s to 1’s and 1’s to 0’s

Binary # 10110011

1’s complement 01001100



Complementary Arithmetic

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2’s complement

Step 1: Find 1’s complement of the number

Binary # 11000110

1’s complement 00111001

Step 2: Add 1 to the 1’s complement

00111001

+ 00000001

00111010



Representation of negative numbers

- Singed-magnitude system: the number consists of magnitude and symbol. The MSB is for the sign 0 means positive &1 means negative - There are two representation for 0, 1000 (-0) & 0000 (+0). - For n-bit integer the range is –(2n-1 – 1) to +(2n-1-1) +18 = 00010010 -18 = 10010010

37 http://modul2poli.blogspot.com/


- One complement : The MSB is for the sign. - Boolean complement all bits to negative +18 = 00010010 -18 = 11101101 - Two representations of zero: 0000 (+0)

1111 (-0)

- The range is –(2n-1 – 1) to +(2n-1-1).



- Two’s complement: MSB is for the sign.

- The range is –(2n-1) to (2n-1-1).

- 3 = 00000011 Boolean complement gives 11111100

Add 1 to LSB +1 11111101



- Only one representation for 0. 0 = 00000000 Bitwise not 11111111 Add 1 to LSB +1 Result 1 00000000 Overflow is ignored, so: - 0 = 0



- Two’s Complement Addition Overflow: An addition overflows if the signs of the addends are the same and the sign of the sum is different from the addends’ sign.

Two Complement in addition



1001 1100 + 0101 + 0100 1110 = -2 10000 = 0 (a) (-7) + (+5) (b) (-4) + (+4) 0011 1100 + 0100 + 1111 0111 = 7 11011 = -5 (c) (+3) + (+4) (d) (-4) + (-1)



0101 1001 + 0100 + 1010 1001 = Overflow 0011 = Overflow (e) (+5) + (+4) (f) (-7) + (-6)



Subtraction rules: Perform a bit-by-bit complement of the subtrahend and add the complemented subtrahend to the minuend with an initial carry in of 1 instead of 0.

Two Complement in Subtraction



0010 0101 + 1001 + 1110 1011 = -5 10011 = 3 (a) M = 2 = 0010 (b) M = 5 = 0101 S = 7 = 0111 S = 2 = 0010 -S = 1001 -S = 1110



1011 0101 + 1110 + 0010 11001 = -7 0111 = 7 (c) M = -5 = 1011 (d) M = 5 = 0101 S = 2 = 0010 S = -2 = 1110 -S = 1110 -S = 0010

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0111 1010 + 0111 + 1100 1110 = Overflow 10110 = Overflow

(e) M = 7 = 0111 (f) M = -6 = 1010 S = -7 = 1001 S = 4 = 0100 -S = 0111 -S = 1100



- Binary Coded Decimal (BCD) is another way to present decimal numbers in binary form. - BCD is widely used and combines features of both decimal and binary systems. - Each digit of a decimal is represented by its four-bit binary equivalent (1 to 9)

- To represent the decimal number 10 we need eight bits (0001 0000)

BCD 8421



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8 7 4 (decimal)

1000 0111 0100 (BCD)

• To convert the number 87410 to BCD

• Each digit always uses four bits. • The BCD value can never be greater than 9 • Reverse the process to convert BCD to decimal.



• BCD is not a number system.

• BCD is a decimal number with each digit encoded to its binary equivalent.

• A BCD number is not the same as a straight binary

number. • The primary advantage of BCD is the relative ease of converting to and from decimal.



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Decimal Binary Octal Hexadecimal BCD0 0 0 0 01 1 1 1 00012 10 2 2 00103 11 3 3 00114 100 4 4 01005 101 5 5 01016 110 6 6 01107 111 7 7 01118 1000 10 8 10009 1001 11 9 100110 1010 12 A 0001 000011 1011 13 B 0001 000112 1100 14 C 0001 001013 1101 15 D 0001 001114 1110 16 E 0001 010015 1111 17 F 0001 0101http://modul2poli.blogspot.com/


ASCII Code

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ASCII code is computer ‘languages’ for naming letters

The ASCII name for ‘a’ is ‘61’

- It is a seven bit code. It has 27 possible code groups.

Represents characters and functions found on a

computer keyboard.

- Examples of use are: to transfer information

between computers, between computers and printers

and for internal storage.



ASCII Reference Table Control , Numeric, Alphabetic, Punctuations Codes

MSD

0

1

2

3

4

5

6

7

0 NUL DLE SP 0 @ P p

1 SOH DC1 ! 1 A Q a W

2 STX DC2 “ 2 B R b r

3 ETX DC3 # 3 C S c s

4 EOT DC4 $ 4 D T d t

5 ENQ NAK % 5 E U e u

6 ACJ SYN & 6 F V f v

7 BEL ETB ‘ 7 G W g w

8 BS CAN ( 8 H X h x

9 HT EM ) 9 I Y i y

A LF SUB * : J Z j z

B VT ESC + ; K [ k {

C FF FS , < L \ l | D CR GS - = M ] m }

E SO RS . > N ^ n ~

F SI US / ? O _ o DEL

53

LSB



SUMMARY

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N10



EXERCISE 1

55

Convert to its DECIMAL equivalent:-

k) 3218

b) 1011012

c) 0.1012

d) 1111012

e) 110012

f) 100.1012

g) 76.3458

h) 1658

m) ABD16

i) 76.758

n) 1011.ACD16

o) 345A.8916

j) 576.458 p) 1A01916

a) 1011.012

q) 0.AFE16

l) 0.6748 r) 78.DEF6



EXERCISE 2

56

Convert to its HEXDECIMAL, BCD 8421

AND ASCII equivalent:-

k) 3218

b) 1011011102

c) 0.101102

d) 1111012

e) 110012

f) 100.1010112

g) 765.3458

h) 1658

m) 67510

i) 76.7548

n) 87610

o) 7810

j) 576.458 p) 0.9810

a) 1011.010112

q) 765.90810

l) 0.67548 r) 86.5610



EXERCISE 3

57

Use the 2's- complement to solve problem

c) -6710 - 910

b) +710 + 3410

a) +4510 - 8710

d) -2310 -[+ 7810 ]

e) +4510 - 1010

f) -910 - 5610

g) +710 + 4310

h) -4310 + 610

i) +1510 - 810

j) +810 -[- 910 ] http://modul2poli.blogspot.com/


QUIZ 1

58

Question 1: -2 Marks Convert 1000110110112 to its DECIMAL equivalent.

Question 2: -6 Marks Write the next four numbers in this HEX counting

sequence: i . 38, 39, 3A, 3B, 3C, 3D, 3E, _______, _______,

_______, ______(1M) ii. E8A, E8B, E8C, E8D, ______, _______, _______,

_______(1M) iii. Convert 42310 to HEX (4)



QUIZ 1

59

Question 3(6 marks) Assume the 2's- complement system for both questions

3.i and 3.ii: i. Consider the Addition of +7 and -7. Express the

sum as a signed binary number and as a decimal

number -3 Marks ii. Perform the Subtraction on the following pairs of signed numbers using the 2's complement system. Express the results as signed binary numbers and as decimal values. 01001 - 11010 = ? -3 Marks



QUIZ 1

60

Question 4 :- 6 Marks

i. Convert 0110100000111001 (BCD Code 8421)

to its decimal equivalent -2 Marks

ii. Comparison of BCD and Binary. Represent the Decimal Value of 17810 by its

straight Binary equivalent and BCD codes Equivalent.

7810 = _______________( Binary) -2 Marks

17810 = _______________( BCD code) -2 Marks


CHAPTER 2 :

BOOLEAN OPERATIONS

1



CLO 2:simplify logical expressions by using Boolean algebra and related techniques orderly. CLO 3:perform correctly basic arithmetic operations by using Boolean laws.

2


SUMMARY

3

BOOLEAN OPERATIONS

Symbols, truth table, logic gates applications; NOT, AND, OR, NOR, NAND, XOR, XNOR. Laws of Boolean Algebra, Sum of Product (SOP), Product of Sum (POS) and Karnaugh Map.


4

TRUTH TABLES

A truth table is a table that describes the behavior of a logic gate

The number of input combinations will equal 2N for an N-input truth table

4


LOGIC GATES

5

Circuits which perform logic functions are called gates

The basic gates are: I. NOT/INVERTER gate II. AND gate III. OR gate IV. NAND gate V. NOR gate VI. XOR gate VII. XNOR gate


6

I. NOT/INVERTER gate

Symbol

Truth Table

Timing Diagram


7

II. AND gate Symbol

Truth Table

Timing Diagram


8

III. OR gate

Symbol

Truth Table

Timing Diagram


9

IV. NAND gate


10

V. NOR gate


11

VI. XOR gate

Diagram http://modul2poli.blogspot.com/

12

VII. XNOR gate


Construct AND, OR and NOT gates using NAND gates

13


14

BOOLEAN ALGEBRA

The Boolean algebra is an algebra dealing with binary variables and logic operation

The variables are designated by: I. Letters of the alphabet II. Three basic logic operations AND, OR and NOT

A Boolean function can be represented by using truth table. A truth table for a function is a list of all combinations of 1’s

and 0’s that can be assigned to the binary variable and a

list that shows the value of the function for each binary combination

A Boolean expression also can be transformed into a circuit diagram composed of logic gates that implements the function http://modul2poli.blogspot.com/

15

Examples F = A + BC


16

BASIC IDENTITIES AND BOOLEAN LAWS


17


18


19

All these Boolean basic identities and Boolean Laws can be useful in simplifying a logic expression, in reducing the number of terms in the expression

The reduced expression will produce a circuit that is less complex than the one that original expression would have produced.

Examples Simplify this function

F = A B C + A B C + A C


20


21

STANDARD FORM

I. Product term A term with the product of literals The AND of literals Boolean multiplication

II. Sum term A term with the sum of literals The OR of literals Boolean addition


22

Sum of Product (SOP) A SOP is a switching expressions consisting either

of a single product term or the OR (sum) of product term

Standard form of SOP is where all the variables in the domain appear in each product term in the expression

There are two steps to convert the equation into a standard form of SOP: 1. Multiply each of the nonstandard term with the

missing term using Boolean algebra A + A = 1 2. Repeat until all variables appear in each

product term.


23

Examples Convert this Boolean equation into standard form of

SOP F = A + B C + A B C


24

Product of Sum (POS) POS is when two or more sum term is multiplied

together Standard form of POS is where all the variables in

the domain appear in each sum term in the expression

There are three steps in a way to convert a product term to standard form of POS:

1. Multiply each of the nonstandard term with the missing term using Boolean algebra A · A = 0

2. Second step: Apply the Boolean identities again (A + B C) = (A + B) (A + C) 3. Third step: Repeat until all variables appear in each

product term.


25

Examples Convert this Boolean equation into standard form of POS

F = (A + B) · (A + B + C) · (B + C)


26

KARNAUGH MAP provides a systematic method for simplifying a

Boolean expression or a truth table function The K-map is a table consisting of N = 2n cells,

where n is the number of input variables. The table format is such that there is a single

variable change between any adjacent cells


Two variables K-map with assume A and B as variable

Three variable K-map with assume A, B and C as variable

27


28

Looping 1. Looping of pair Looping a pair of adjacent 1s in a K-map eliminates the

variable that appears in complemented and uncomplemented form


29

2. Looping group of four Looping a quad of adjacent 1s eliminate the two

variables that appear in both complemented and uncomplemented form


30

3. Looping group of eight Looping an octet of adjacent 1s eliminates the three

variables that appear in the both complemented and uncomplemented form


31

Examples

Simplify this Boolean equation by using K-maps F = X Y Z+ X Y Z + X Y Z


32

Examples Find out the equation based on the given


33

Solution


LOGO

Chapter 3

Data processing Circuit

1


2


CLO 4:

explain correctly the application of data processing circuits in digital systems.


SUMMARY

3

DATA PROCESSING CIRCUITS

Encoder,

Decoder,

BCD to Seven Segment Display

Decoder,

Multiplexer

Demultiplexer.


Decoder

Decoder: a multiple input, multiple output logic circuit which converts coded input into coded output from n input line to a maximum of 2n unique output lines.

activates an output that corresponds to a binary number on the input.

Only one output is active for any given input

4


Decoder

The basic function is to detect the presence of a specified combination of bits (code) on its inputs and to indicate the presence of that code by a specified output level

In other word, decoder circuit look at its inputs, determine which binary number present there, and activates the output that correspond to that numbers; all other outputs remain inactive

Some decoder do not utilize the 2n possible input codes for example BCD to decimal decoder and Seven segment decoder

5


2-to-4 Decoder (Active HIGH)

6

2-to-4

Decoder

A

B

O0

O1

O2

O3

b) Truth table

a) Logic symbol

O0 = A’B’

O1 = A’B

O2 = AB’

O3 = AB

c) Boolean expression

O0

O1

O2

O3

A B

d) Logic diagram

@


2-to-4 Decoder (Active LOW)

2 to 4

Decoder

21

20

O0

O1

O2

O3

A

B

2 to 4

Decoder

21

20

O0

O1

O2

O3

A

B

O0

O1

O2

O3

A B

O0

O1

O2

O3

A B

7

a) Logic symbol

@

b) Truth table c) Boolean expression

ABO

BAO

BAO

BAO

3

2

1

0

d) Logic diagram


2-to-4 Decoder with active LOW enable input

8

ABenDBAenD

BAenDBAenD

31

20

,

,

a) Logic symbol b) Truth table

c) Boolean expression

d) Logic diagram

Enable input used to control the

operation of the decoderActive

mode is ‘0’- active low http://modul2poli.blogspot.com/

The 74x139 Dual 2-to-4 Decoder

9

a) Logic symbol

b) Logic diagram

1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1

1 X X 0 0 0 0 0 1 0 1 0 0 1 1

Y3 Y2 Y1 Y0 G B A

Outputs Inputs

Truth table for one-half of a 74x139 dual 2-to-4 decoder


10

3 to 8 Binary Decoder (active HIGH)

3-to-8

Decoder

X

Y

F0

F1

F2

F3

F4

F5

F6

F7

Z

a) Logic symbol

x y z F 0 F 1 F 2 F 3 F 4 F 5 F 6 F 7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

F1 = x'y'z

x z y

F0 = x'y'z'

F2 = x'yz'

F3 = x'yz

F5 = xy'z

F4 = xy'z'

F6 = xyz'

F7 = xyz

b) Truth table

c) Logic diagram & Boolean Expression


11

The 74x138 3-to-8 Decoder

a) Logic symbol

(b) Logic diagram. http://modul2poli.blogspot.com/

12


(b) Block Diagram

(c) Function table


13

The equation for the output signal Y5:

Active-low

It has three enable inputs, G1, G2A, G2B , all of which must be asserted for the selected output to be asserted.


ABCBGAGGY 2215


Exercise

Design a decoder listing below a) BCD to decimal decoder b) 4 to 16 decoder

14


Seven Segment Display

Used for displaying information in a form that can be understood by user or operator.

Information can be in alphanumeric (numbers and letters).

Seven segment configuration which its arrangement uses LED for each segment.

two ways of arrangement – common anode and common cathode.

Each arrangement needs different driver/ decoder to drive each segment of seven segment display.

15


16

BCD-to-7 Segment Decoder / Driver


A B C D a b c d e f g

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

17

FILL IN THE TRUTH FOR ACTIVE LOW BCD TO 7 SEGMENT DECODER


Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder (active HIGH) with m OR gates to generate a minterms

OR gate forms the sum The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate

Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

It can also use AND gates and n-to-2n decoder to generate a Maxterm function.

18

Decoder applications


Example: Full adder S(x, y, z) = S (1,2,4,7) C(x, y, z) = S (3,5,6,7)

19

Decoder applications (full adder)

x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

3-to-8 Decoder

S2 S1

S0

x

y

z

0

1

2

3

4

5

6

7

S

C

a) Truth table b) Minterm Expression


20

Decoder applications example

f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7)

(a) Using output or-gates. (b) Using output nor-gates.


21

f1(x2,x1,x0) = Sm(0,2,6,7) and f2(x2,x1,x0) = Sm(3,5,6,7)

(a) Using output and-gates. (b) Using output nand-gates.

Application Example Decoder applications example


An encoder is a combinational logic circuit that essentially performs a ‘reverse’ of decoder function

Number of input lines is larger than output lines Decoder VS Encoder

22

Encoder

Decoder Encoder


Only one of input lines is activated at a given time and produces an N-bit output code depending on which input is active.

For example octal to binary encoder: if input 4 is active, the output code should be 100 with 1 is MSB bit.

23

Encoder


I0

I3I2I1

I5I4

I7I6

22

21

20

24

Octal to Binary Encoder

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0

1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1

b) Truth table a) Logic Symbol


25

Octal to Binary Encoder

I0

I1

I2

I3

I4

I5

I6

I7

y0 = I1 + I3 + I5 + I7

y1 = I2 + I3 + I6 + I7

y2 = I4 + I5 + I6 + I7

c) Boolean Expression d) Logic diagram


Decimal to BCD Priority Encoder

26

The priority function means that the encoder will produce a BCD output corresponding to the highest-order decimal digit input that is active and will ignore any other actives input


Multiplexer

A multiplexer is a device that allows digitals information from several sources to be routed onto a single line for transmission over that line to a common destination

The basic multiplexer has several data-input line and a single output line

has data select inputs, which permit digital data on any one of the inputs to be switched to the output line

also known as data selector

27


Multiplexer

28


2 - to - 1 Multiplexer

2 inputMux

I0

I1

z

s

29

b) Truth Table

c) Boolean Expression

d) Logic Circuit a) Logic Symbol


4 - to - 1 Multiplexer

4 inputMux z

S1

I0

I3I2I1

S0

30

c) Boolean Expression

b) Truth Table

a) Logic Symbol d) Logic diagram

301201101001ISSISSISSISSz http://modul2poli.blogspot.com/

The 74ALS151 8 inputs Multiplexer

31


32

Multiplexer Application


Logic design using Mux

Case1- number of input is equal to number of select lines

Design procedure Connect inputs to selected

lines Identify the decimal number

corresponding to each minterm in the expression

Connect logic 1 level to input lines corresponding to these numbers

Connect logic 0 level to the others

33

f(x,y,z) = Sm(0,2,3,5)

Example - 3 variable function using 8-to1 line Multiplexer


34


Case 2: Number of inputs is higher than number of select

lines Design procedure Reduce the number of inputs to

the number of select lines by inspection k-map


xyz

00

10

10

11

01

1

0

10

0

00

1

I0

I2

I3

I1

S1S0

35

Logic design using Mux Example – implement f(x,y,z) = Sm(0,2,3,5) using 4

input mux

02

31

0

I

zII

zI

a) k-map b) Boolean Exp c) implementation


36


(Exercise)

Realize the f(a,b,c,d) =

Sm(0,2,3,5,8,9,11,12,14,15)

Using

a)8 input Mux

b)4 input Mux


37

Demultiplexer (Demux)

Basically reverses the multiplexing function Takes data from one line and distributes them to a

given numbers of output lines. Demultiplexer also known as a data distributor. Decoders can also be used as a demultiplexers.


38

Figure (a) shows a 1-line-to-4-line demultiplexer circuit. The data input lines goes to all of the AND gates. The two data lines only one gate at a time, and the data appearing on the data-input line will pass through the selected gated to the associated data output line.

Figure (a): 1-line-to-4-line demultiplexer


39

Example: The serial data input waveform (data in) and data selectors input (s0 and s1) are

shown in figure (b). Determine the data output waveforms on D0 through D3 for the demultiplexer in figure (a).

Solution: Notice that the select lines go through a binary sequence so that each successive

input bit is routed to D0, D1, D2 and D3 in sequence as shown by the output waveforms in figure (b).

Figure (b)


1

Chapter 4:

FLIP FLOPS (Sequential Circuits)



CLO 2: simplify logical expressions by using Boolean

algebra and related techniques orderly.

CLO 5: explain the operation of basic sequential circuits

correctly. http://modul2poli.blogspot.com/

Summary

- Types Of Flip Flops: SR Flip-Flop, Clocked SR Flip-Flop, T Flip-Flop and JK Flip-Flop. - Symbols, Truth Tables and Timing. T Flip-Flops and D Flip-Flops built using JK Flip-Flops.


4

4.0 Introduction Sequential Circuits The output of circuit depends on the previous output and the

present inputs.

The inputs must follow a specific sequence to produce a required output.

In order to follow a sequence of inputs the circuits must contain some form of memory to retain knowledge of those inputs, which have already occurred.

This memory are obtained by feedback connections, which are made so that history of the previous inputs is maintained.

Most sequential systems are based on a small number of simple sequential circuit elements known as Bistables or Flip Flops. http://modul2poli.blogspot.com/

5

4.0 Flip Flop (Sequential Circuits)

What is Flip flop? Answer: In digital circuits, the flip-flop, is a kind of bistable multivibrator.

It is a Sequential Circuits / an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory , bit 1 or bit 0.


http://www.answers.com/topic/digital-electronics

http://www.answers.com/topic/bistability

http://www.answers.com/topic/multivibrator

http://www.answers.com/topic/electronic-circuit-1

http://www.answers.com/topic/bit-1

http://www.answers.com/topic/computer-data-storage

6

4.0 Introduction – Flip Flop

They are 1 (HIGH) or 0 (LOW).

Whenever we refer to the state of flip flop, we refer to the state of its normal output (Q).

More complicated Flip flop

use a clock as the control input. These clocked flip-flops are used whenever the input and output signals must occur within a particular sequence.

Figure 4.0.1 : General Flip flop

symbol Inputs Q Normal output Inverted Output They have two stable conditions and can be switched from one to the other by appropriate inputs. These stable conditions are usually called the states of the circuit.

Q


Types Of Flip Flop

1. SR Flip Flop

a. SR Flip Flop Active Low = NAND gates

b. SR Flip Flop Active High = NOR gates

2. Clocked SR Flip Flop

3. JK Flip Flop

4. JK Flip Flop With Preset And Clear

5. T Flip Flop

6. D Flip Flop


The Used of Flip Flop

For Memory circuits For Logic Control Devices For Counter Devices For Register Devices


9

4.1 SR Flip Flop

The most basic Flip Flop is called SR Flip Flop. The basic SR flip flop is an asynchronous device. In asynchronous device, the outputs is immediately

changed anytime one or more of the inputs change just as in combinational logic circuits.

It does not operate in step with a clock or timing. These basic Flip Flop circuit can be constructed using

two NAND gates latch or two NOR gates latch. SR Flip Flop Active Low = NAND gates SR Flip Flop Active High = NOR gates


10

4.1 SR Flip Flop

Figure 4.1.1:

SR Flip Flop logic

Symbol

The SR Flip Flop has two inputs, SET (S) and RESET (R).

The SR Flip Flop has two outputs, Q and ¯

The Q output is considered the normal output and is the one most used.

The other output ¯ is simply the compliment of output Q.

Q

Q


11

4.1 SR Flip Flop - NAND GATE LATCH

NAND GATE LATCH

Figure 4.1.2: SR NAND (Active LOW) Logic circuit.

The NAND gate version has two inputs, SET (S) and RESET (R).

Two outputs, Q as normal output and ¯ as inverted output and feedback mechanism.

The feedback mechanism is required to form a sequential circuit by connecting the output of NAND-1 to the input of NAND-2 and vice versa.

The circuit outputs depends on the inputs and also on the outputs.

Q 1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2


12


Figure 4.1.3 Feedback Mechanism


13


Normal Resting State Figure 4.1.4.a

Input S=1 , R=1 , This is the normal

resting state of the circuit and it has no effect of the output states.

Output Q and ¯ will remain in whatever state they were in prior to the occurrence of this input condition.

It works in HOLD mode of operation.

1

2

0

1

1

1

0

1

1

1

1

1

1 1 1

2 1

0 0 0

1

Q 1

2


14


Input, S = 0, R = 1

This will set Q = 1.

It works in SET mode operation.

Figure 4.1.4.b

1

2

0

1

0 1

0 1


15


Figure 4.1.4.c Input S = 1, R = 0

This will reset Q = 0.

It works in RESET mode operation. 1

2

1

0 1

0

0

1


16


Figure 4.1.4.d This condition tries to set and reset the NAND gate latch at the same time.

It produces Q = ¯ = 1

This is unexpected condition, since the two outputs should be inverses of each other.

If the inputs are returned to 1 simultaneously, the output states are unpredictable.

This input condition should not be used and when circuits are constructed, the design should make this condition

S = R = 0 never arises. It is called INVALID/PROHIBITED

1

2

0

0 1

1

1

0

Q


17


From the description of the NAND gate latch operation, it shows that the SET and RESET inputs are active LOW.

The SET input will set Q = 1 when SET is

0 (LOW).RESET input will reset Q = 0 when RESET is 0 (LOW)

In the prohibited/INVALID state both

outputs are 1. This condition is not used on the RS flip-flop. The set condition means setting the output Q to 1.

Likewise, the reset condition means

resetting (clearing) the output Q to 0. The last row shows the disabled, or hold, condition of the RS flip-flop. The outputs remain as they were before the hold condition existed. There is no change in the outputs from the previous states.

The flip-flop memorizes the previous

condition.

Figure 4.1.5 : SR NAND gate

latch Truth Table

S R Q ¯ STATUS

0 0 1 1 INVALID

0 1 1 0 SET

1 0 0 1 RESET

1 1 Q ¯ HOLD (NoChange)

Q

Q

S R Q ¯ STATUS

0 0 1 1 INVALID

0 1 1 0 SET

1 0 0 1 RESET

1 1 Q ¯ HOLD (NoChange)


18

4.1 SR NAND Flip Flop-Waveforms

Exercise 4.1.1:

Determine the output of NAND gate latch which Q initially 1 for the given input waveforms.

S R Q ¯

Example 4.1.1: Determine the output of NAND gate latch which Q initialy 0 for the given input waveform.

S

R

Q

¯ Q Q


19

4.1 SR Flip Flop - NOR GATE LATCH

NOR GATE LATCH

Figure 4.1.6: SR NOR

(Active HIGH) Logic circuit

The latch circuit can also be constructed using two NOR gates latch.

The construction is similar to the NAND latch except that the normal output Q and inverted output ¯ have reversed positions.

Q


20


The analysis of a SR FLIP FLOP

NOR :

* S = 0, R = 0; This is the normal resting state of the circuit and it has no effect of the output states. Q and ¯ will remain in whatever state they were in prior to the occurrence of this input condition. It works in HOLD (no change) mode operation.

• S = 0, R = 1; This will reset Q to

0, it works in RESET mode operation.

SR FLIP FLOP NOR

(Active HIGH) Logic circuit

Q


21


S = 1, R = 0; This will set Q to 1, it works in SET mode operation. S = 1, R = 1; This condition tries to set and reset the NOR gate

latch at the same time, and it produces Q = ¯ = 0. This is an unexpected condition and are not used.

Since the two outputs should be inverse of each other. If the inputs are returned to 1 simultaneously, the output states are unpredictable. This input condition should not be used and when circuits are constructed, the design should make this condition SET=RESET = 1 never arises.

Q


22


From the description of the NOR gate latch operation, it shows that the SET and RESET inputs are Active HIGH.

The SET input will set Q = 1 when SET is 1 (HIGH). RESET input will reset Q when RESET is 1 (HIGH).

Figure 4.1.7 : SR NOR gate latch

Truth Table

S R Q ¯ STATUS

0 0 HOLD (NoChange)

0 1 0 1 RESET

1 0 1 0 SET

1 1 0 0 INVALID

Q Q

Q _


23

4.1 SR NOR Flip Flop -Waveforms

Example 4.1.2: Determine the output of NOR gate latch which Q initially 0 for the given input waveforms.

S

R

Q

¯

Exercise 4.1.2 : Determine the output of NOR gate latch which Q initially 1 for the given input waveforms.

S

R

Q

¯ Q Q


24

4.2 The CLOCK

In synchronous device, the exact times at which any output can change states are controlled by a signal commonly called the clock.

The clock signal is generally a rectangular pulse train or a square wave as shown in figure 4.9.

The clock is distributed to all parts of the system, and most of the system outputs can change state only when the clock makes a transition.


25

4.2 The CLOCK When the clock changes from a LOW state to a HIGH

state, this is called the positive-going transition (PGT) or positive edge triggered.

When the clock changes from a HIGH state to a LOW state, it is called negative going transition (NGT) or negative edge triggered.

Figure 4.2.1: Clock Pulse-Train

(a) Positive going transition

(b) Negative going transition

Enable

Disable


26

4.2 Clocked SR Flip Flop

Additional clock input is added to change the SR flip-flop from an element used in asynchronous sequential circuits to one, which can be used in synchronous circuits.

The clocked SR flip flop logic symbol that is triggered by the PGT is shown in Figure 4.2.2

Its means that the flip flop can change the output states only when clock signal makes a transition from LOW to HIGH.

Figure 4.2.2 : PGT Clocked SR Flip

flop symbol


27

4.2 Clocked RS Flip Flop

clock S R Q ¯ STATUS

0 0 Q Q HOLD (NoChange)

0 1 0 1 RESET

1 0 1 0 SET

1 1 0 0 INVALID

Figure 4.2.3: Truth Table for

clocked SR Flip Flop •The Truth Table in figure 4.2.3 shows how the flip flop output will respond to the PGT at the clocked input for the various combinations of SR inputs and output. • The up arrow symbol indicates PGT.

Q _


28

Example 4.2.1: Determine the output of PGT clocked SR flip flop which Q initially 0 for the given input waveforms

Cp

S

R

Q

¯

Exercise 4.2.1: Determine the output of PGT clocked SR flip flop which Q initially 1 for the given input waveforms.

Cp

S

R

Q

¯


Q Q


29


Figure 4.2.4 : NGT Clocked

SR Flip flop symbol The clocked SR Flip

Flop logic symbol that is triggered by the NGT is shown in Figure 4.2.4

It means that the Flip flop can change the output states only when clocked signal makes a transition from HIGH to LOW.


30


Figure 4.2.5: CLOCKED SR

FLIP FLOP LOGIC CIRCUIT


31


Figure 4.2.6: CLOCKED SR FLIP FLOP LOGIC CIRCUIT

If used NOR Gate, must used AND Gate in front.


32


Example 4.2.2: Determine the output of NGT clocked SR flip flop which Q initially 0 for the given input waveforms

Cp

S

R Q ¯

Exercise 4.2.2: Determine the output of NGT clocked SR flip flop which Q initially 1 for the given input waveforms.

Cp

S

R Q

¯

Q Q


33

4.3 JK Flip Flop - Symbol

Another types of Flip flop is JK flip flop.

It differs from the RS flip flops when J=K=1 condition is not indeterminate but it is defined to give a very useful changeover (toggle) action.

Toggle means that Q and ¯ will switch to their opposite states.

The JK Flip flop has clock input Cp and two control inputs J and K.

Operation of Jk Flip Flop is completely described by truth table in Figure 4.3.3.

Figure 4.3.1 : PGT JK Flip

flop symbol

Figure 4.3.2 : NGT JK Flip

flop symbol

Q


34

4.3 JK Flip Flop – Truth Table And Logic Circuit

Figure 4.3.3: Truth Table for JK

Flip Flop

Figure 4.3.4: JK FLIP FLOP

LOGIC CIRCUIT

clock J K Q ¯ STATUS

0 0 HOLD (No Change)

0 1 0 1 RESET

1 0 1 0 SET

1 1 Toggle

Q

Q _ Q

Q Q _


35

4.3 JK Flip Flop - waveforms

Example 4.3.1 : Determine the output of PGT clocked JK flip flop for the given input waveforms which the Q initially 0.

J

Clk

K

Q


36

4.3 JK Flip Flop - waveforms

Exercise 4.3.1:Determine the output of NGT clocked JK flip flop for the given input waveforms which the Q initially 0.

Exercise 4.3.2:Determine the output of PGT clocked JK flip flop for the given input waveforms which the Q initially 0.

J

K

Q

Cp

¯ Q

Cp Cp

K

J

Q

Q

¯


37

4.4 JK Flip Flop with Asynchronous Input

The J and K inputs are called synchronous inputs since they only influence the state of the flip flop when the clocked pulse is present.

This flip flop can also have other inputs called Preset

(or SET) and clear that can be used for setting the flip flop to 1 or resetting it to 0 by applying the appropriate signal to the Preset and Clear inputs.

These inputs can change the state of the flip flop

regardless of synchronous inputs or the clock. http://modul2poli.blogspot.com/

38

4.4 JK Flip Flop with Preset and Clear

Figure 4.4.1 : Symbol and Truth Table


39


Example 4.4.2 : The output of clocked JK flip flop which output initially 0 for the given input waveforms.

Cp

Preset

Clear

J

K

Q

Q


40


Exercise 4.4.3 : The output of clocked JK flip flop which output initially 0 for the given input waveforms.

Cp

Preset

K

Clear

Q


41

4.5 T Flip Flop - Symbol

The T flip flop has only the Toggle and Hold Operation.

If Toggle mode

operation. The output will toggle from 1 to 0 or vice versa.

Figure 4.5.1: Symbol for T Flip Flop

T clock Q status

0 Q Q

HOLD

1 Q Q TOGOL

Q

Figure 4.5.2 :Truth Table for T Flip Flop

CP T


42

4.5 T Flip Flop – Logic Circuit

Cp

T T

Logic circuit T Flip flop using NOR gate

Logic circuit T Flip flop using NAND gate

Figure 4.5.3: Logic circuit for T Flip Flop


43

4.5 T Flip Flop – Waveforms

Example 4.5.1 : Determine the output of PGT T flip flop for the given input waveforms which the Q initially 0.

T

Clk

Q

Q


44

4.5 T Flip Flop – Wave forms

Exercise 4.5.1 : Determine the output of PGT T flip flop for the given input waveforms which the Q initially 0.

Exercise 4.5.2 : Determine the output of NGT T flip flop for the given input waveforms which the Q initially 0.

Cp Cp

Q

T

Q

Q

T

Q


45

4.6 D Flip Flop

Also Known as Data Flip flop Can be constructed from RS

Flip Flop or JK Flip flop by addition of an inverter.

Inverter is connected so that the R input is always the inverse of S (or J input is always complementary of K).

The D flip flop will act as a storage element for a single binary digit (Bit).

Figure 4.6.1 :

D Flip flop symbol


46

4.6 D Flip Flop - Symbol

PGT NGT

D

Clk

Q

Q

D

Flip Flop

Positive Edge

D

Clk

Q

Q

D

Flip Flop

Negative Edge

Figure 4.6.2 : D Flip flop symbol using JK Flip Flop / SR Flip Flop


47

4.6 D Flip Flop- Logic circuit-Truth Table

Figure 4.6.3: Logic circuit for D Flip Flop

Figure 4.6.4: Truth Table for D Flip Flop

D clock Q ¯ status

0 0 1 RESET

1 1 0 SET

Q

Cp


48

4.6 D Flip Flop – Waveforms

Example 4.6.1 : Determine the output of PGT D flip flop for the given input waveforms which the Q initially 0.

Cp D

Exercise 4.6.1 Determine the output of NGT D flip flop for the given input waveforms, which output Q initially 0.

Cp

D

Q

Q

Q

Q


49

4.7 T Flip Flops and D Flip Flops can be Built using JK Flip Flop

The JK flip flop is considered as a universal flip flop.

A combination of Jk flip flop and an inverter can construct a D Flip Flop as shown in Figure 4.18

It also can construct T Flip Flop by combine both J and K inputs with HIGH level input as shown in Figure 4.19

Figure 4.7.1 : D Flip flop

symbol using JK Flip Flop / SR

Flip Flop

Figure 4.7.2 : T Flip flop

symbol using JK Flip Flop / SR

Flip Flop

T


LOGO

Chapter 5 : Counters

1


2


CLO 5 : Explain The Operation Of Basic

Sequential Circuits Correctly


SUMMARY

COUNTERS

Basic concepts of asynchronous and synchronous counters; logic circuits and timing diagram of counter. Various types of asynchronous and synchronous counters.


4

Introduction –COUNTERS A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses.

Asynchronous counters

Synchronous counters

Asynchronous Counters (or Ripple counters)

the clock signal (CLK) is only used to clock the first FF.

Each FF (except the first FF) is clocked by the preceding FF.

Synchronous Counters,

the clock signal (CLK) is applied to all FF, which means that all FF shares the same clock signal,

thus the output will change at the same time.

EE 202 DIGITAL ELECTRONICS


5

Modulus (MOD) – the number of states it counts in a complete cycle before it goes back to the initial state.

Thus, the number of flip-flops used depends on the MOD of the counter (ie; MOD-4 use 2 FF (2-bit), MOD-8 use 3 FF (3-bit), etc..)

Example: MOD-4 Ripple/Asynchronous Up-Counter.

Introduction –COUNTERS



Asynchronous Counters

6 EE 202 DIGITAL ELECTRONICS


Asynchronous (Ripple) UP Counters

The Asynchronous Counter that counts 4 number starts from 00011011 and back to 00 is called MOD-4 Ripple (Asynchronous) Up-Counter.

Next state table and state diagram

7

Present State Next State

Q1Q0 Q1Q0

00 01

01 10

10 11

11 00

00

01

10

11




A two-bit asynchronous counter is

shown on the left. The external clock is

connected to the clock input of the first

flip-flop (FF0) only. So, FF0 changes

state at the falling edge of each clock

pulse, but FF1 changes only when

triggered by the falling edge of the Q

output of FF0.

Note that for simplicity, the transitions

of Q0, Q1 and CLK in the timing

diagram above are shown as

simultaneous even though this is an

asynchronous counter. Actually, there

is some small delay between the CLK,

Q0 and Q1 transitions.

8

Figure 2.1 : MOD 4 Asynchronous Up Counter

Waveform



Because of the inherent propagation

delay through a flip-flop, the transition

of the input clock pulse and a transition

of the Q output of FF0 can never occur

at exactly the same time. Therefore,

the flip-flops cannot be triggered

simultaneously, producing an

asynchronous operation.

The 2-bit ripple counter circuit shown

has four different states, each one

corresponding to a count value.

Similarly, a counter with n flip-flops can

have 2 to the power n states. (2n) The

number of states in a counter is

known as its mod (modulo) number.

Thus a 2-bit counter is a mod-4

counter.


9


Waveform




Usually, all the CLEAR inputs are

connected together, so that a single

pulse can clear all the flip-flops before

counting starts. The clock pulse fed

into FF0 is rippled through the other

counters after propagation delays, like

a ripple on water, hence the name

Ripple Counter

A mod-n counter may also described as

a divide-by-n counter. This is because

the most significant flip-flop (the

furthest flip-flop from the original clock

pulse) produces one pulse for every n

pulses at the clock input of the least

significant flip-flop (the one triggers by

the clock pulse).

10


Waveform



MOD 8 Asynchronous Up Counter

The following is a three-bit

asynchronous binary counter and its

timing diagram for one cycle.

It works exactly the same way as a two-

bit asynchronous binary counter

mentioned above, except it has eight

states due to the third flip-flop.

11


Waveform



MOD 8 Asynchronous Up Counter

12

Figure 2.3a Next State Table Figure 2.3b State Diagram


CBA CBA

000 001

001 010

010 011

011 100

100 101

101 110

110 111

111 000

0

1

2

3

7

6

5

4



Exercise :

13

J Q

K Q

CLK

1 J Q

K Q

CLK

1 J Q

K Q

CLK

1

A B C

CLK

A 0

B 0

C 0




MOD 16 Asynchronous Up counter – (Negative Triggered)

14




Exercise : Draw a MOD 16 Asynchronous DOWN Counter (Negative Triggered) :

MOD 16 Asynchronous Up counter (Positive Triggered)

15




Asynchronous DOWN Counter Figure 2.7 : MOD 4 or 2-bit Asynchronous down counter

16

J Q

K Q

CLK

1 J Q

K Q

CLK

1

A (LSB) B (MSB)

A 0 1 0 1 0 1 0 1 0

B 0 1 1 0 0 1 1 0 0

CLK

Binary 0 3 2 1 0 3 2 1 0



17

Exercise:

Design a MOD-4 ripple down-counter Design a MOD-8 ripple down counter using negative triggered. Design a MOD-16 ripple down counter using positive triggered.




18

So far, we have design the counters with MOD number equal to 2N, where N is the number of bit (N = 1,2,3,4….) (also correspond

to number of FF)

Thus, the counters are limited on for counting MOD-2, MOD4, MOD-8, MOD-16 etc..

The question is how to design a MOD-5, MOD-6, MOD-7, MOD-9 which is not a MOD-2N (MOD 2N) ?

MOD-6 counters will count from 010 (0002) to 510(1012) and after that will recount back to 010 (0002) continuously.

Asynchronous Counters (MOD 2N)



19

MOD-6 ripple up-counter (MOD 2N)

Present St. Next St.

CBA CBA

000 001

001 010

010 011

011 100

100 101

101 000(110)

0

1

2

3

5

4

Reset the state to 0002 when 1102 is detected


Figure 2.8b :State Diagram

Figure 2.8a :Next State Table



20


Circuit diagram for MOD-6 ripple up-counter (MOD 2N)

J Q

K

CLR Q

CLK

1 1 1

A (LSB) B C(MSB)

J Q

K

CLR Q

CLK

J Q

K

CLR Q

CLK

Detect the output at CBA=110 to activate

CLR. NAND gate is used

to detect outputs that generates ‘1’!

CLK

Present St. Next St.

CBA CBA

000 001

001 010

010 011

011 100

100 101

101 000(110)



21

Exercise : Draw MOD-5 Ripple Down-counter and Up-

counter (MOD 2N)




22

IC for Asynchronous counters (IC 74293)

74293 IC for Asynchronous counter with Reset (MR1 and MR2)

MR1 MR2

Q0 Q1 Q2 Q3 CP0

CP1 74293

CLR Q

CLK

1 1 1

Q0 Q1 Q2

CLR Q

CLK

CLR Q

CLK

1

CLR Q

CLK

Q3

MR1 MR2

CP0

CP1

K K K K

J J J J Q Q Q Q



23

Using 74293 IC to design MOD 16 Asynchronous UP-Counter!

Exercise: Use 74293 IC to design MOD-10 ripple up-counter


MR1

MR2

Q0 Q1 Q2 Q3

CP0

CP1 74293

1 0 1 0



24

Exercise: Determine the MOD for each configuration shown below?


MR1

MR2

Q0 Q1 Q2 Q3

CP0

CP1 74293

MR1

MR2

Q0 Q1 Q2 Q3

CP0

CP1 74293

1 0 1

Answer : MOD 8

Answer : MOD 5


25

Determine the MOD for configuration shown below?


MR1

MR2

Q0 Q1 Q2 Q3

CP0

CP1 74293

Answer : MOD 14

1 1 1

1



26


Exercise : Design Asynchronous counters MOD-60

using IC 74293.

Solution : Discuss with your Lecturer in class.


Exercise : i. Design Asynchronous counters MOD-55

using IC 74293.

ii. Design Asynchronous counters MOD-

1000 using IC 74293.


Asynchronous Decade Counters

The binary counters previously introduced have two to the power n states. But

counters with states less than this number are also possible. They are designed to

have the number of states in their sequences, which are called truncated

sequences. These sequences are achieved by forcing the counter to recycle before

going through all of its normal states. A common modulus for counters with truncated sequences is ten. A counter with

ten states in its sequence is called a decade counter. The circuit below is an

implementation of a decade counter.

27

Figure 2.3 : Asynchronous Decade Counter


The sequence of the decade counter is

shown in the table below: Once the counter counts to ten (1010),

all the flip-flops are being

cleared. Notice that only Q1 and Q3 are

used to decode the count of ten. This

is called partial decoding, as none of

the other states (zero to nine) have

both Q1 and Q3 HIGH at the same time.

Asynchronous Decade Counters

28

Figure 2.4 : True Table Asynchronous Decade Counter


Asynchronous Up-Down Counters

In certain applications a counter must be able to count both up and

down. The circuit below is a 3-bit up-down counter. It counts up or down

depending on the status of the control signals UP and DOWN. When the

UP input is at 1 and the DOWN input is at 0, the NAND network between

FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock

input of FF1. Similarly, Q of FF1 will be gated through the other NAND

network into the clock input of FF2. Thus the counter will count up.

29

Figure 2.5 : Asynchronous Up-Down Counter


When the control input UP is at 0 and DOWN is at 1, the inverted outputs of

FF0 and FF1 are gated into the clock inputs of FF1 and FF2 respectively. If

the flip-flops are initially reset to 0's, then the counter will go through the

following sequence as input pulses are applied.


E2002 : Electronic System 2 30

Figure 2.5 : Asynchronous Up-Down Counters


Notice that an asynchronous up-down counter is slower than an

up counter or a down counter because of the additional

propagation delay introduced by the NAND networks.






Figure 2.3 : Asynchronous Up-Down Counters Waveform For 4 Bit Up-Down Counter


33

Disadvantages of Asynchronous Counters:-

Propagation delay is severe for larger MOD of counters, especially at the MSB.

Existence of ‘glitch’ is inevitable for MOD 2N counters.

Cannot design random counters (i.e:- to design circuit that counts numbers in these sequence 56723156723156….)

Solution, use SYNCHRONOUS COUNTERS.




Synchronous Counters



Synchronous Counters A synchronous counter, in contrast to an asynchronous counter, is one whose

output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time:



Now, the question is, what do we do with the J and K inputs? We know that we still have to maintain the same divide-by-two frequency pattern in order to count in a binary sequence, and that this pattern is best achieved utilizing the "toggle" mode of the flip-flop, so the fact that the J and K inputs must both be (at times) "high" is clear. However, if we simply connect all the J and K inputs to the positive rail of the power supply as we did in the asynchronous circuit, this would clearly not work because all the flip-flops would toggle at the same time: with each and every clock pulse!










39

For synchronous counters, all the flip-flops are using the same CLOCK signal. Thus, the output would change synchronously.

Procedure to design synchronous counter are as follows:- STEP 1: Obtain the State Diagram. STEP 2: Obtain the Excitation Table using state transition

table for any particular FF (JK or D). Determine number of FF used.

STEP 3: Obtain and simplify the function of each FF input using K-Map.

STEP 4: Draw the circuit.

How To Design Synchronous Counter



40

Design a MOD-4 synchronous up-counter, using JK FF. STEP 1: Obtain the State transition Diagram


0

1

2

3

00

01

10

11 Binary



41

STEP 2: Obtain the Excitation table. Two JK FF are used.


Present State Next State Input, J K

B A B A JB KB JA KA

0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1 X 0 1 X

1 1 0 0 X 1 X 1

OUTPUT TRANSITION

QN QN+1

FF INPUT

J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Excitation table



42

STEP 3: Obtain the simplified function using K-Map


B A

0

1

0 0 1

1 X X

JB = A

B A

0

1

0 X X

1 0 1

KB = A

B A

0

1

0 1 X

1 1 X JA = 1

B A

0

1

0 X 1

1 X 1

KA = 1



43

STEP 4: Draw the circuit diagram.

(MOD-4 synchronous up-counter )


JA QA

KA A Q

CLK

1 JB QB

KB B Q

CLK

A (LSB) B (MSB)



How To design Synchronous Counter

Let us employ these techniques to design a MOD-8 counter to count in the

following sequence: 0, 1, 2, 3, 4, 5, 6, 7.

Step1: Determined Flip Flop Used and Creating state transition

diagram. (Rajah Keadaan) N = 2n 8 = 2n n = log 8 / log 2

= 3 Flip Flop ( 3 Bit ) M = 2n-1 = 23 - 1 = 8 - 1 = 7

44

N = Modulo/MOD n = Flip Flop Used M = Maximum Number To Be Count



Step 2: Creating present state-next state table

How To design Synchronous Counter

45


Q2 Q1 Q0 Q2 Q1 Q0

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

Q0 = QA

Q1 = QB

Q2 = Qc



Step 3: Expand the present state-next state table to form the transition table.


46

Present

State

Next State Present inputs

QC QB QA QC QB QA JCKC JBKB JAKA

0 0 0 0 0 1 0X 0X 1X

0 0 1 0 1 0 0X 1X X1

0 1 0 0 1 1 0X X0 1X

0 1 1 1 0 0 1X X1 X1

1 0 0 1 0 1 X0 0X 1X

1 0 1 1 1 0 X0 1X X1

1 1 0 1 1 1 X0 X0 1X

1 1 1 0 0 0 X1 X1 X1

Excitation Table

(Jadual Ujaan Flip Flop

JK)

Q Q J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

_

‘X’ indicates a "don’t care" condition.



Step 4: Use Karnaugh maps to identify the present state logic functions for each of the inputs.

E.g. for J2 we get:


47

JC = QBQA Using similar techniques for the other inputs we get:

KC = QBQA

JB = QA

KB = QA

JA = 1

KA = 1

0

2

6

4

1

3

7

5

QA

QA

1 1 1 0 01 00

QcQB

QcQB

0

1 0

0 0

1

X

X

X

X



Step 5: Constructing Circuit


48

A

A

A

A B

B

C

C

C

C

B

B



How To Design Synchronous Counter that count Random number

Example :

Design a Synchronous Counter to Count 4,7,3,0 and 2 respectively

using JKFlip Flop negative trigered by showing: i. Flip Flop Used ii. State Transition Diagram iii. Exitation Table / Present state, next State iv. Karnough Map & perform Simplified Function v. The Synchronous Counter



Solution:

Step 1 : Flip Flop Used

Find Modulo, N= 2n

M = 7, M = 2n-1 = 7 2n = N , so, N = 7+1 = 8, MOD 8

2n = 8, n = log 8 / log 2 n = 3 bit = 3 Flip Flop.

Synchronous Counter to Count 4,7,3,0 and 2 respectively



Solution:

Step 2 : State Transation

Diagram, to count 4, 7, 3, 0

and 2.

Present

Qn

Next State

Qn+1

J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

100

000

111

011

010


Exitation Truth Table For Counter using JK FlipFlop



Step 3 : Exitation Table /present State, Next State

Decimal

Present State

Next State JC KC JB KB JA KA

QC QB QA QC QB QA

4 1 0 0 1 1 1 x 0 1 x 1 x

7 1 1 1 0 1 1 x 1 x 0 x 0

3 0 1 1 0 0 0 0 x x 1 x 1

0 0 0 0 0 1 0 0 x 1 x 0 x

2 0 1 0 1 0 0 1 x x 1 0 x




Step 4: Karnough Map and

Simplified Function

00 01 11 10

0 0 0 x 1

1 x x x x


K-Map For JA = QC

CB

A

0

3

4 2

1 5

6

7



00 01 11 10

0 0 0 X 1

1 X X X X

00 01 11 10

0 X X X X

1 X 1 0 X

K-Map For JA = QC

K-Map For KA = QC


CB

A

0

3

4 2

1 5

6

7

CB

A

0

3

4 2

1 5

6

7



00 01 11 10

0 1 X X 1

1 X X X X

00 01 11 10

0 X 1 X X

1 X 1 0 X

K-Map For JB = 1

K-Map For KB = QC


CB

A

0

3

4 2

1 5

6

7

CB

A

0

3

4 2

1 5

6

7



00 01 11 10

0 0 1 X X

1 X 0 X X

00 01 11 10

0 X X X 0

1 X X 1 X

K-Map For JC = QA+QB

K-Map For KC = QB


CB

A

0

3

4 2

1 5

6

7

CB

A

0

3

4 2

1 5

6

7



Step 5 : Perform Counter Circuit

By using simplified function from K-Map, JA = QC, KA = QC,

JB = 1, KB = QC, JC = QA + QB, KC = QB

'1' / Vdd


JA QA

KA QA

JB QB

KB QB

JC QC

KC QC

CP,CLOCK PULSE



Synchronous Counter

Exercises: Design a counter to count in the following

sequence: 6, 4. 2, 3, 1.

Design a counter to count in the following sequence: 15,9,11,5,2,13,1.

Do more exercises in Past Years Exam Paper.

End Of This Topic…..




REFERENCES:

1. "Digital Systems Principles And Application" Sixth Editon, Ronald J. Tocci. 2. "Digital Systems Fundamentals" P.W Chandana Prasad, Lau Siong Hoe, Dr. Ashutosh Kumar Singh, Muhammad Suryanata.


CHAPTER 6: SHIFT REGISTER



CLO 5 : Explain The Operation Of

Basic Sequential Circuits Correctly


SUMMARY

REGISTERS

Basic concepts of registers and shift registers; classification of shift registers; arithmetic circuit; integrated circuit of shift registers; Ring counters and Johnson counter.


Introduction – Shift Register

4

Shift registers are constructed using several flip-flop, connected in such a way to STORE and TRANSFER/ Shift digital data.

Basically, D flip-flop is used. The input data (either „0‟ or „1‟) is applied to the D terminal and

the data will be stored at Q during positive/negative-edge transition of the clock pulse. D Q

Q

EE 202 : DIGITAL ELECTRONICS http://modul2poli.blogspot.com/

5

One D FF is used to store 1-bit of data. Thus, the number of flip-flops used is the same with the number of bit stored.

Shift register mean that the data in each FF can be transferred/move to other FF upon edge triggering of the clock signal.

Four types of data movement in shift register are:-

Parallel in / parallel out (PIPO)

Serial in / serial out (SISO)

Parallel in / serial out (PISO)

Serial in / parallel out (SIPO)

Shift Register

EE 202 : DIGITAL ELECTRONICS


6

Serial Parallel

•Movement of N-bit data

require N number of CLK

pulses. Thus, the operation is

slow.

•Only one FF is required to be

connected at the output

terminal, thus only one wire is

required.

•Require only one CLK pulse

to transfer all N-bit of data.

Thus, operation is faster than

serial.

•Required N number of

connection to the output

terminal, which is proportional

to the number of bit. Thus, too

many connection is required.

Serial Data VS Parallel Data movement

EE 202 : DIGITAL ELECTRONICS http://modul2poli.blogspot.com/

7

D Q2

CP

D Q1

CP

D Q3

CP

D Q0

CP

D3 D2 D1 D0

Q3 Q2 Q1 Q0

Flip-flop configuration for PIPO register.

CLK



Parallel in / parallel out (PIPO)

8

PIPO data movement.

Q3

Q2

CLK

Q1

Q0

1 0 1 1 1

0

0

0

0

1 0 1 0 0

0

0

1 1 1 1

0 0 1 0

D3

D2

D1

D0

1

0

1

0

0

1

1


9

Flip-flop connection for SISO.

D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CP CLK

DIN

1st CLK 2nd CLK 3rd CLK 4th CLK



Serial in / serial out (SISO)

10

SISO data movement. Binary data 10111 is transferred!

DATA-IN

Q3

Q0

Q1

1st

CLK

2nd 3rd 4th 5th

Q2

1 0 1 1 1


11

Flip-flop connection for PISO.

D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CP CLK

D0 D1 D2 D3 SHIFT/LOAD

Serial data out


12

Parallel in / serial out (PISO)

PISO data movement.

SHIFT/ LOAD

CLK

Q3

0

0 1 1 1

1 0 1

0

0

0

1

1 1 1 1

0 0 1 1

D0

D1

D2

D3

1 0 0 1 0 1 http://modul2poli.blogspot.com/

13

A shift register counter is a shift register whose

output being fed back (connected back) to the serial input. This shift register would count the

state in a unique sequence! Two types of shift register counter:-

The ring counter

The Johnson counter

Shift Register Counters



14

Ring Counter Ring counters are used to construct “One-Hot”

counters It can be constructed for any desired MOD number A MOD-N ring counter uses N flip-flops connected in the arrangement as shown in fig. a) In general ring-counter will require more flip-flops than a binary counter for the same MOD number



15

Ring Counter

Q3 Q2 Q1 Q0



16

Ring Counter



17

Ring Counter

0 0 0 1

1 0 0 0

0 1 0 0

0 0 1 0



Exercise: Draw a 3 Bit Ring Counter Circuit with initial input 010 . show a True Table until 8 clock pulse/number sequence and draw the output waveform.

Answer: Discuss with Your lecturer

18

Ring Counter



19

Johnson Counter Or Twisted-ring counter

Johnson counter constructed exactly like a normal ring counter except that the inverted output of the last flip-flop is fed back to

first flip-flop



20

Johnson Counter



21

Johnson Counter

A

B

C

0 1 1 1

0 0 1 1

0 0 0 1



22

Chips for shift registers

74164 is a 8-bit SIPO shift register

74164

CLK

CLR

A B

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7



23


74165 is a 8-bit PISO register

74165

CLK

CLK INH

SH/LD SER

D0 D1 D2 D3 D4 D5 D6 D7

Q7

Q7



24


74195 can be used as a 4-bit PIPO register

74195

CLK

SH/LD

J K

Q0 Q1 Q2 Q3

CLR

D0 D1 D2 D3



25 EE 202 : DIGITAL ELECTRONICS


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Ee202 Digital Electronic