EE100B Lab Report

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EE100B Lab Report #1: Current Mirrors and Cascodes

Zaza Nguyen

860967146

Partner: Andrew Yu

Section 23

2-1-2013


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Abstract:

The objectives in this lab are to get familiar with the design of Current

Mirrors and Sinks (and similarly Sources. It is to also understand the purpose,

performance and design of cascade stages. In this lab we have successfully

accomplished these goals, by proving that our experimental data does match upwith theoretical data. In each part, a graph with a set of data is provided to show the

understanding of current vs. drain-source voltage characteristics and how to

calculate the resistance impedance with the input vs. output provided.

Lab Procedures:

Part 1:

1) Determine the appropriate to use in the circuit detailed in figure 1 byusing the theoretical equations listed below. We know that ), so plugging them in:

This is useful to comparing out experimental values to this value and analyze

whether we are correctly doing this lab. We should get roughly the same value if

my calculations are correct.

2) After assembling the circuit of Figure 1.1, we experimentally determine what

will yield a by varying . We set the current toroughly .203 mA, which will determine the are looking for.

Figure 1.1: Current mirror (sink)

3) In this step, we do the opposite of the previous step by finding the different

values of when the current reaches to .2mA. Keeping constant andvarying from 0.0V to +2.0V (with emphasis on 0.0V 1.0V), we wereable to tabulate . (Figure 1.2 in Analysis)


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4) We plotM2s Drain current vs. Drain-Source voltage (Figure 1.3 inData Analysis)

5) Perform a linear fit to the line in the saturation region and determine the

output impedance from the slope of this line using the equation: . ( data are in Figure 1.3 in Analysis)

6) We plot

by using our data from step 2 and a new table of data ofthe current gain

. We compare the results and see if it differs from unity.

(Figure 1.4 in the analysis section)

Part 2:

1) We assemble the circuit in Figure 2.1.

Figure 2.1: Current Mirror w/ Cascode stage using 2 (two) ICs CD4007

We still set , because we want to have the lowest voltage forbody effects in nMOSFETS. We do this while observing our Pin 14 and 7, and

remembering to reconnect Pin 14 to the highest voltage in the circuit.

2) Vary until the appropriate M3 biasing is established so that . In ourcase, we had set which is the highest from part 1 ofthis lab.

3) We vary

0.0V to +5.0V (with emphasis on 0.0V 1.0V) and tabulate data of

. (Figure 2.2 in Data Analysis)

4) Plot, linear fit to the line in the saturation region and determine theoutput impedance by using this equation: . (Figure 2.3 inData Analysis)

5) Compare this output impedance with the one calculated in Part 1.


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6) Compare this output impedance with the theoretical value calculated using the

equation:

Analysis:

Part 1:

1) (

)

Based on my calculations, my theoretical .

2) Our determined .

3)

VDD2 [V] VDS2 [V] IDS2 [uA] ro = VDS2 / IDS2

0.027 0.027 24 0.001125

0.05 0.05 41 0.00122

0.1 0.1 86 0.00116

0.19 0.19 132 0.00144

0.5 0.5 189 0.00265

0.7 0.7 193 0.00363

1 1 195 0.00513

1.3 1.3 196 0.00663

1.7 1.7 197 0.00863

2 2 198 0.010101

Figure 1.2: Table of being constant while is changing from varying of

was kept constant and we varied from 0.0V to +2.0V (with emphasis on0.0V 1.0V) to get a set of points that would reach . Using the equation , was found for each points which is used in step 5 of part 1lab.

4)

0

50

100

150

200

250

0 0.5 1 1.5 2 2.5

Current[

uA]

Voltage [V]

Part 1: ID2(VDS)


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Figure 1.3: M2s Drain current vs. Drain-Source voltage

From the linear fit, we can see that the slope is 0.01009, therefore the output

impedance is .

6)VDS2 Iout/Iin

0.027 0.99

0.05 0.99

0.1 0.99

0.19 0.99

0.5 0.99

0.7 0.99

1 0.99

1.3 0.99

1.7 0.99

2 0.99

Figure 1.4: Data Table and Graph of

Current gain

In Figure 1.4 we can see that for the region of saturation, our results are very close

to unity. However, it quickly diverges as we move in to the triode region, as well as

when .

Part 2:

2)

Iout = Iref

Iout = 198uA

3)

1) VOUT [V] IOUT [uA] ro casc = Vout / Iout0.02 13 0.00154

0.05 34 0.00147

0.11 71 0.00155

0.21 120 0.00175

0.3 152 0.00197

0.5 184 0.00272

0.75 194 0.00387

1 196 0.0051

2 197 0.01015

3 197 0.01523

12 198 0.060606

Figure 2.2: was kept constant and we varied from 0.0V to +2.0V (with

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

VDS

2

(V)

IOUT

/IIN

(mA)

Part 1 - #6

IOUT

/ IIN

(VDS

2

)


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In figure 2.2, we vary 0.0V to +5.0V (with emphasis on 0.0V 1.0V). This showsthat in the emphasis between 0.0V and 1.0V, Iout is increasing until it reaches 2V,

which is when it starts going into saturation mode. Even up to 12V for Vout, Iout is

still roughly the same and does not change much.

4)

Figure 2.3: Plot of

From the linear fit, we can see that the slope is 0.000541, therefore the output

impedance is . This is a great improvement of aroundan 18 times increase in output impedance.

5) The theoretical output impedance is given by: ( ) . This value is very close to our experimentallydetermined impedance and the discrepancy can easily be attributed to the relatively

small number of data points collected that limit the accuracy of our linear fit for the

saturation region of the graph.

Problems:

In this lab, there were very few errors that were made, and the errors were

easily fixable. The first one is mistakenly plotting the variables in the wrong axis,

which was definitely a crucial mistake. If graphs were plotted wrong, we would be

analyzing it incorrectly which means there was no way of getting the correct value

of the slope for saturation mode. Secondly, we were to reconnect Pin 14 to the

highest voltage in the circuit which we did not check until after a few data points.

That is also very important to the lab because once the voltage of pin 14 is no longer

the highest voltage in the circuit, the data became will wildly inconsistent. However,

this was not a problem in the analysis section, because we were able to simply use

our data that was in the saturation mode and analyze.

0

50

100

150

200

250

0 5 10 15

Iout[uA]

Vout [V]

Part 2: Iout(Vout)


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Conclusions:

In this lab, I felt like we had a successful lab which we completed our

purposes. We were able to familiar ourselves with the design of Current Mirrors and

Sinks and other similarly sources. We were also able to understand the purpose,

performance and design of cascade stages. Using our data, we can see that we wereon the right tracks, by proving that our experimental data does matches up when

compared to the theoretical data we calculated for. Overall, the lab went well; we

learned about build current mirror, sink, and source circuits as well as how they

behave.

Documents

EE100B Lab Report