EE 3110 Microelectronics I Practice Test (Midterm Exam 2 ...faculty.weber.edu/snaik/EE3110/PracticeTest2.pdf · EE 3110 Microelectronics I Practice Test (Midterm Exam 2 2014) Subject:

Weber State University EE3110 Microelectronics I Suketu Naik

EE 3110 Microelectronics I

Practice Test (Midterm Exam 2 2014)

Subject: MOSFETs

Instructions:

1) ALWAYS SHOW YOUR WORK!

2) Put a box or circle around your answers.

3) Open Notes, Open Book, Closed Multisim/LTSpice, Closed Internet. Any type of

calculator is allowed.

4) Numbers in the parentheses on the right indicate points for that particular

problem.

Name: ________________________________________________________

Date: _______________

Problem Points

1 (Transistor and its operation) /32

2 (VTC) /8

3 (Find ID and VD) /20

4 (Current Mirror) /10

5 (CS Amplifier) /20

6 (CS Amplifier) /10

6 (CG Amplifier) /10

Total /100


2

PROBLEM 1 (16)

Consider the transistor shown on the right.

(a) Name the transistor and label the nodes (i.e. G for Gate, D for Drain, S for Source) (2):

(b) Draw ID vs VDS characteristics for this device (8).

Assume that the overdrive voltage VOV = 0.5 V, Early voltage VA= 50 V, and maximum

saturation current ID = 10 mA. Clearly label (write numbers) the transition points (e.g. -VA, VOV,

IDSAT) on the plot. Draw the approximate boundaries between different regions of operation (i.e.

Triode, Saturation) and label the regions appropriately.

(c) In terms of the application of the device, why do we operate it in the Triode region and in the

Saturation region (Hint: look at the slope of the curve in each region) (2)?


3

(d) Draw the cross section of the device (which shows the three terminals, the induced channel,

and the substrate) and write the pertinent equation for the current ID for each of the following

portion of the ID vs VDS plot. Use λ to indicate channel length modulation.

Triode Region: Linear Operation

Cross section (3)

Equation (2): _______________________________________________________________

Triode Region: Bent Curve

Cross section (3)

Equation (2): ________________________________________________________________


4

Saturation Region: Constant Current Source

Cross section (3)

Equation (2): ________________________________________________________________

Saturation Region: Channel length modulation

Cross section (3)

Equation (2): ________________________________________________________________


5

PROBLEM 2 (8): Consider the amplifier shown below. Here VDD = 15 V, RD = 10 kΩ, kn = 1

mA/V2, and Vtn = 0.5 V.

(a) Draw the Voltage Transfer Characteristic (VTC) curve. Find the coordinates of the two end

points of the saturation region (linear portion), A and B. Label these points on the plot (4).

(b) Suppose that the amplifier is biased with an overdrive voltage VOV = 1.5 V. Find the

coordinates of the bias point Q on the VTC curve (4).


6

PROBLEM 3 (20): In the circuits below, find the current (ID) and voltages (VD) as labeled.

Here VDD = 10 V, VSS = -10 V, kn = kp = 1 mA/V2, Vtn = 1 V, Vtp = -1 V. Ignore channel-

length modulation.


7

PROBLEM 3 (Continued...)


8

PROBLEM 4 (10): A PMOS based current mirror circuit with two PMOS transistor P1 and P2 is

shown below. Here VDD = 2.5 V, kp = 0.5 mA/V2, Vtp = -1.2 V. You can assume that W/L ratio

is identical for the two transistors and that both the transistors are operating in saturation region.

Ignore channel-length modulation.

Design the circuit (find R1 and R2) that results in VD1 (DC voltage at the drain of P1) = 1 V.


9

PROBLEM 5 (20): A common-source amplifier circuit is shown below. Here VDD = 5 V, VSS =

-5 V, kn = 1.08 mA/V2, Vtn = 0.8 V, VA = 50 V, Rsig = RG = 100 kΩ, RL=100 kΩ, and

CG=CD=CS=100 μF. Assume that the DC bias current ID = 1 mA.

Design the circuit: (a) perform DC analysis and find RS, (b) use small-signal model, perform AC

analysis and find RD (don’t forget to include ro) if the overall voltage gain GV is required to be

-8 V/V.

(a) DC analysis:


10

(b) AC analysis (small-signal model) :


11

PROBLEM 6 (10): Please choose between either of the problems (see page 13).

A PMOS based common-source amplifier circuit is shown below. Here VDD = 2.5 V, kp = 6.7

mA/V2, Vtp = -0.7 V, Rsig = 500 Ω, RL = 10 kΩ, and CG=CD=CS=100 μF. The transistor has

very large |VA|.

(a) Perform DC analysis and find RS to bias the transistor at ID = 0.3 mA. Note: RG1= 100 kΩ.

and RG2= 50 kΩ .

(b) Draw the small-signal model and find the overall gain, GV if RD = 1 kΩ.


12


13

PROBLEM 6 (10): Please choose between either of the problems (see page 11).

Consider the NMOS Common-Gate amplifier below. Here VDD = 10 V, VSS = -10 V, RS = 200

kΩ, kn = 1.08 mA/V2, Vtn = 0.8 V, Rsig = 50 Ω, RL = 10 kΩ, and CD=CS=100 μF. Assume gm =

1 mA/V and RD = 15 kΩ. You can also assume that as you look down from the source terminal

towards Rs and Vss, very large resistance is present. Ignore channel length modulation.

Find Rin, Ro, and overall voltage gain GV (Hint: use T-model). What does the overall voltage

gain become for Rsig = 1 kΩ? 10 kΩ? 100 kΩ?


14

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EE 3110 Microelectronics I Practice Test (Midterm Exam 2 ...faculty.weber.edu/snaik/EE3110/PracticeTest2.pdf · EE 3110 Microelectronics I Practice Test (Midterm Exam 2 2014) Subject: