Editorial Selected Papers from the Symposium on Integrated ...InternationalJournalof Recongurable Computing In Modeling and implementation of a power estimation methodology for systemC

Hindawi Publishing CorporationInternational Journal of Reconfigurable ComputingVolume 2013, Article ID 942021, 2 pageshttp://dx.doi.org/10.1155/2013/942021

EditorialSelected Papers from the Symposium on Integrated Circuits andSystems Design (SBCCI 2011)

Massimo Conti,1 Elmar Melcher,2 Jürgen Becker,3 Alisson Brito,4 and Oliver Sander3

1 Dipartimento di Ingegneria dell’Informazione, Universita Politecnica delle Marche, Via Brecce Bianche, Ancona, Italy2 Centro de Engenharia Eletrica e Informatica, Universidade Federal de Campina Grande, Brazil3 Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), 76131 Karlsruhe, Germany4Centro de Informatica, Universidade Federal da Paraiba, Joao Pessoa, Brazil

Correspondence should be addressed to Massimo Conti; [email protected]

Received 13 May 2013; Accepted 13 May 2013

Copyright © 2013 Massimo Conti et al.This is an open access article distributed under the Creative Commons Attribution License,which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

SBCCI is an international forum dedicated to IntegratedCircuits and Systems Design, Test and CAD, held annuallyin Brazil, copromoted by SBC, SBMicro, IEEE CAS, ACMSIGDA, and IFIP WG 10.5. The 24th edition of the Sympo-sium on Integrated Circuits and SystemsDesign (SBCCI) washeld in Joao Pessoa, PB, Brazil, from August 30 to September2, 2011.

Track 2.1 of SBCCI 2011 was dedicated to ReconfigurableComputing. Some of the papers of this track have beenselected for this special issue.

This special issue presents some of the latest develop-ments in the area of design, specification, and modeling lan-guages and applications of reconfigurable computing; recon-figurable architectures and novel applications of FPGAs;hardware-software codesign and coverification; emulationand prototyping techniques.

Ten articles are in this issue.Themain disadvantages of the reconfigurable approaches

are still the costs in area and power consumption. In “Hon-eyComb: an application-driven online adaptive reconfigurablehardware architecture,” A.Thomas et al. present a solution forapplication driven adaptation of a reconfigurable architectureat register transfer level to reduce the resource requirementsand power consumption while keeping the flexibility andperformance for a predefined set of applications. A prototypechip of this architecture designed in 90 nm standard celltechnology manufactured by TSMC is presented.

Multiprocessor system-on-chip (MPSoC) security isbecoming an important requirement. The challenge is to

provide MPSoC security that makes possible a trustworthysystem thatmeets the performance and security requirementsof all the applications. The network-on-chip (NoC) can beused to efficiently incorporate security. In “QoSS hierarchicalNoC-based architecture for MPSoC dynamic protection,” J.Sepulveda et al. propose the implementation of Quality ofSecurity Service to overcome present MPSoC vulnerabilities.The paper presents the implementation of a layered dynamicsecurityNoC architecture to overcome actualMPSoC vulner-abilities.

Networked multiprocessor system-on-chips are used toimplement novel embedded applications characterized byincreasing requirements on processing performance as wellas the demand for communication between several devices.Such systems require a detailed exploration on both, architec-tures and system design. In “Efficient execution of networkedMPSoC models by exploiting multiple platform levels,” C. Rothet al. present a methodology that embeds previous work intoa simulation platform, which facilitates efficient executionof cross-domain simulation models on different abstractionlevels.

In “Open systemC simulator with support for power gatingdesign,” G. S. Silveira et al. present an open source SystemCsimulator with support to Power Gating design. This sim-ulator is an alternative to assist the functional verificationaccomplishment of systems modeled in RTL. The possibilityof controlling the retention and isolation of Power GatedFunctional Block is presented turning the simulations morestable and accurate.

2 International Journal of Reconfigurable Computing

In “Modeling and implementation of a power estimationmethodology for systemC,” M. Kuehnle et al. describe amethodology tomodel power consumption of logicmodules.A detailed mathematical model is presented and incorpo-rated in a tool for translation of models written in VHDL toSystemC.The power analysis is based on a statistical model ofthe underlying HW structure and an analysis of input data.

In “Development of a SoC for digital television set-topbox: architecture and system integration issues”, A. B. Soareset al. present the development of a set-top box for DigitalTelevision compliant to the SBTVD standard. It is a complexdigital system integrating audio and video decoders anda CPU to run user interface and applications. Practicalstrategies used to solve integration problems are discussed.The SoC architecture is validated and is prototyped using aXilinx Virtex-5 FPGA board.

In “Algorithm and hardware design of a fast intra-framemode decision module for H.264/AVC encoders,” D. Palominoet al. present a fast intra mode decision algorithm andits hardware architecture design for an H.264/AVC videoencoder. The proposed algorithm allows the complete elim-ination of the encoding loop present in Rate-Distortion-Optimization based mode decision, which is substituted bysimple distortion calculations and comparisons, decreasingthe complexity of the video encoder. The designed archi-tecture of the fast intradecision algorithm was describedin VHDL and synthesized targeting Stratix II FPGA andTSMC 0.18 𝜇m standard cell library. The motion estimationis the most complex module in a video H.264/AVC encoderrequiring a high processing throughput and high memorybandwidth, mainly when the focus is high definition videos.The throughput problem can be solved increasing the par-allelism in the internal operations. The external memorybandwidth may be reduced using a memory hierarchy. In“A memory hierarchy model based on data reuse for fullsearch motion estimation on high-definition digital videos”,A. S. B. Lopes et al. present a memory hierarchy modelfor a full search motion estimation core. The proposedmemory hierarchy expressively reduces the external memorybandwidth required for the motion estimation process andit provides a high data throughput. A case study for theproposed hierarchy was implemented and prototyped on aVirtex 4 FPGA.

In “An FPGA-based omnidirectional vision sensor formotion detection on mobile robots,” J. Y. Mori et al. presenta FPGA-based omnidirectional vision system for mobilerobotic applications. The proposed architecture is suitablefor robot localization, allowing to compute the distancebetween the robot and the surrounding objects. The overallarchitecture has been mapped onto a Cyclone II FPGAdevice, using a hardware/software codesign approach, whichcomprises a NIOS II embedded microprocessor and specificimage processing blocks implemented in hardware.

In “An optimization-based reconfigurable design for a 6-bit 11-MHz parallel pipeline ADCwith double-sampling S&H,”W. Carvajal and W. V. Noije present a 6 bit, 11MS/s time-interleaved pipeline A/D converter design. The specificationprocess, from block level to elementary circuits, is coveredto draw a design methodology. Prelayout simulations of the

complete ADC are presented to characterize the designedconverter, which consumes 12mWwhile sampling a 500 kHzinput signal.The circuit will be sent to fabrication in a CMOS0.35 𝜇m AMS technology, and some postlayout results areshown.

Massimo ContiElmar MelcherJurgen BeckerAlisson BritoOliver Sander

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Editorial Selected Papers from the Symposium on Integrated ...InternationalJournalof Recongurable Computing In Modeling and implementation of a power estimation methodology for systemC