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CHEMNITZ UNIVERSITY OF TECHNOLOGY
Chair for Circuit and System Design
Lecture EDA Tools
Tools, Methods and Algorithms used for Designing Circuits and Systems
CHEMNITZ UNIVERSITY OF TECHNOLOGY
Chair for Circuit and System Design
Introduction
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
3
Objectives
EDA Tools Lecture: Introduction to established methods, tools and languages used in different areas of IC Design
What does EDA stand for? – Electronic Design Automation
IC Design (Overview): – Specification – Design – Verification – Layout, Manufacturing, Test – Validation
Certain tools and methods exist for each step.
CHEMNITZ UNIVERSITY OF TECHNOLOGY
Chair for Circuit and System Design
Introduction -
Transistor History
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
The First Computer
© IEEE 2008 / Nile University
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
ENIAC - The _first_ electronic computer (1946)
© IEEE 2008 / Nile University
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
The Transistor Revolution
First bipolar transistor Bell Labs, 1948
© IEEE 2008 / Nile University
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
The First Integrated Circuits
First Integrated Cicuit, Jack Kilby, TI 1958
© IEEE 2008 / Nile University
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
The First Integrated Circuits
Bipolar logic 1960’s
ECL 3-input Gate Motorola 1966
© IEEE 2008 / Nile University
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Technology: MOS
© Lehrst. für Rechnergestützten Schaltungsentwurf EIS I 1. Einführung
Prof. Dr.-Ing. Wolfram H. Glauert
EIS_01_Einf_v1.fm 84 S. 18. 10. 04
1 - 8
Die Abkürzung MOS
steht für Metal-Oxide-Semiconductor;
sie wird weiterhin gebraucht, obwohl heute in der
Regel der Aufbau Polysilicium-Siliciumdioxid-
Halbleiter verwendet wird.
Früher benutzte man als Gate-Material Aluminium,
heute Polysilicium bzw. Polysilicid.
In der Zukunft können u.U. wieder Metalle als Gate-
Material Verwendung finden.
Meist verwendet man heute
CMOS- Technologien
mit Geometrien im Submikrometer-Bereich für
Logik- und Speicheranwendungen.
L= 100 nm
Spacer
n+n- n-
tox = 3 nm
xj = 45 nm
xj = 70 nm
Leff = 37 nm
p-substr.
n+
Gate
Querschnitt durch einen MOS-Transistor der 100 nm - Generation,adaptiert nach Yan et al.
What is: MOS acronym for Metal-Oxide-Semiconductor
today: Polysilicon-Silicondioxide-Semiconductor
past: Aluminium gate today: Polysilicon, Polysilicid
future: again metal as gate (better conductance)
usage: CMOS in deep submicro area for logic and storage applications
❒
❒
❒
❒
❒
10
deep submicro - Leff in nano meter
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Recall: Digital Logic - What is a „Bit“?
11
1 Transistor 1 Switch
open closed „OFF“„ON“
hole no hole
1 10 0
no holehole
Bit = Representation of an information with two possible values (0,1)
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Recall: Basic digital circuit elements
12
VDD
VSS
In Out
p
n
IN OUT1 00 1
A B OUT
0 0 1
0 1 1
1 0 1
1 1 0
InverterNAND-Gate
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
13
CMOS-Inverter
From this behaviour the transfer characteristic can be determined.
Current flows only at the moment of switching (Ideal behaviour).
Transfer characteristic Transverse current
Vout
VH
Vin
VL
V0L
V0H
VDD
P1
P2VDD
ID
VDD½0
V –VDD THVth
Vin
VDD
VSS
In Out
p
n
Schematic
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
CMOS -Inverter
14
Transfer of electrical circuit to a layout:
VDD
pn
X
Y
VSSSchematic
Y Metall
VDD
aktives Gebiet X aktivesGebiet
Wanne
Wp
Wn
VSS Ln Lp
Quer-schnitt
Top view on layout
The figure shows the correlations between schematic and geometrical structure.
Cross-section viewp-Substrat
n+ n+ p+ p+n-Wanne
n-Kanal-Transistor
p-Kanal-Transistor
Poly-Si MetallTEOS-Oxid
liegt auf VDD liegt auf VSSGateoxid
Feldoxid
Wp / Wn ∼ µn / µp
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Summary CMOS
15
• Broadly used in all the major digital IC’s(microprocessors, microcontrollers, static RAM…)
• The established manufacturing process
• Low power dissipation (no static cross current/flow)
• Uses complementary and symmetrical pairs of p-type and n-type MOSFETs
CHEMNITZ UNIVERSITY OF TECHNOLOGY
Chair for Circuit and System Design
Introduction -
Technology
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Semiconductor-Technology
Realisation of electrical functionality with integrated semiconductor structures using dedicated technological methods and processes applied to a silicon wafer:
• (Photo-)Resisting / Lithography • Oxidation • Etching • Doping (Ion-Implantation) • Chemical-mechanical planarization etc.
The collection of these steps is called “Technology”.
IC-Packaging • Bonding • Encapsulation
IC-Testing(!)
17
Image Source Wikipedia
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Technology nodes - Moore's Law
18
10 µm 19716 µm 19743 µm 19771.5 µm 19821 µm 1985800 nm 1989600 nm 1994350 nm 1995250 nm 1997180 nm 1999130 nm 200190 nm 200465 nm 200645 nm 200832 nm 201022 nm 201214 nm 201410 nm 2016 –20177 nm 2017 – 20185 nm 2020 – 2021
„Every 18 moths the integration density doubles.“
Gordon Moore, 1964/1975
1996
1 Chip
1999
4 Chips
2002
16 Chips
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
19
Technology nodes - Moore's Law and Cells
"Comparison semiconductor process nodes" by Cmglee (Wikipedia)
leukocyte, red blood cell ~ 7um
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
20
Moore's Law: INTEL Microprocessors
Moore's Law can also be applied to microprocessors:
• at first every 4 to 6 years • reduced to 2 years (number
of transistors doubles every 2 years)
Conclusion: – processing speed doubles every 18-20
months – memory density doubles every 18-20
months – the Intel P4 3 GHz CPU you buy today for
$250 will cost • $125 in eighteen months… $62.50 in
three years… $36.25 in four and a half years… $18.12 in six years… and free with your breakfast cereal 1.5 years later…
• … by that time your $250 will buy you a 96 GHz CPU
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Intel 4004 Micro-Processor
1971 1000 transistors 1 MHz operation
© IEEE 2008 / Nile University
Full-Custom design no design tools no description languages
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Example Full-Custom-Design
22
Transistorcircuit Layout
AND - Gate: 2-input-NAND
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Profile view of CMOS logic technologies
23
interconnect - 5 layers:
interconnect layer, consists of dielectric SiO2, plugs, wires (Al)
plugs (Wolfram)
silicon
Transistor, polysilicide gate with spacer
"deep sub - µm"
dielectric (low ε)
plugs (Cu)
wire (Cu)
interconnect - 10 layers:
0,350 µm technology > 0,1 µm technology
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
24
copper wire without isolation
CHEMNITZ UNIVERSITY OF TECHNOLOGY
Chair for Circuit and System Design
Introduction -
IC-Design
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
26
Market segments for large digital ICsLogic applications have become the technology driver, very large circuits are called „Systems on a Chip“, SoC. There are three different approaches for designing large digital ICs:
– Full Custom: mass products with high performance, large design efforts with a lot of manual steps in the design processe.g.: micro processors, memories, DSPs, consumer applications, often including analog circuits
– Semi Custom: medium number of application specific components, extensive use of automated design methods. e.g.: large logic components for complex systems (base stations for cellular phone networks)
– FPGA: small number of application specific components, logic behavior is programmed (e.g. Field Programmable Gate Arrays) rather than designing a set of masks for components e.g.: logic components for small number of complex systems and prototypes (e.g. measurement equipment) with considerably less performance (compared to Full and Semi Custom designs)
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
27
Classification of circuits - market based
Full custom design Semi Custom
Design
StandardCircuits ASIC
Integrated Circuits
Application Specific Standard Product (ASSP)
quantitysmallmediumhigh
FPGA
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
28
Classification of circuits - structure based
Integrated Circuits
optimized regular
using masks
electrical
by userby
manufacturer
hard wiredprogrammable
by software
cell based
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
29
Core
new logic
Core 2Cor
e 1
new logic
extern
IC yesterday / today IC today / tomorrow IC in the future
hardware
Development of IC structure
intra chip
software
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
30
Constraints that limit IC’s
–Size (mobile phone, smart card, sensor technology) –Reliability (automobile, other applications relevant to security) –Savings in IC costs (consumer) –Savings in Mounting and Connection technology (consumer) –Savings in Power Dissipation (heat! cooling! battery lifetime!) –Enhanced Functionality (number of inter-chip connections)
Functionality grows with shrinking design size
Remaining demand for using smaller technologies
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Fakultät für ET/ITProfessur Schaltkreis- und Systementwurf
Prof. U. HeinkelTECHNISCHE UNIVERSITÄT CHEMNITZ
Schaltkreis-Entwurf
87
Das Problem der Entwurfsproduktivität
(productivity gap)
© Lehrst. für Rechnergestützten Schaltungsentwurf EIS I 1. Einführung
Prof. Dr.-Ing. Wolfram H. Glauert EIS_01_Einf_v1.fm 84 S. 18. 10. 04 1 - 62
Das Problem der Entwurfsproduktivität
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
Logic Tr./Chip
Tr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsis
tor
per
Ch
ip(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
cti
vit
y(K
) T
ran
s./S
taff
- M
o.
Co
mp
lexit
yProblem: Design Gap
31
- automated design steps, standardised design tools- extensive library concepts (ReUse) + prefab (half-finished) chips ⇒ mask-programmable ASICs, Structured ASICs
Solution:- “programmable“ ICs (processors, µC, application specific: ASIC), FPGAs
Design Gap
Big Problem
Complexity outpaces design productivity
HDLs
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
32
How to design chips with more and more functions? Design engineering population does not double every two years…
• Hence, more efficient design methods are needed! - Productivity of development has to be raised, yet it stays behind the increase of chip complexity (21 %/year) - Efficient organisation of the development has top priority - Work on the highest level of abstraction - Automation by applying efficient algorithms
Use of structured computer-aided design processes: Hardware Description Languages
Problem: Design Productivity
Verilog, VHDL, SystemC
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Automated Design Process for Electronic
33Mit Hilfe eines Compilers wird die in einer höheren Programmiersprache beschriebene Software nun in der Regel vollautomatisch in die Maschinensprache des Prozessors übersetzt, so dass sie dort ausgeführt werden kann. Es liegt deshalb nahe, dieselbe Idee, auch für den Hardwareentwurf zu verwenden, und sich einen "Silicon-Compiler" vorzustellen, mit dessen Hilfe aus dem in der Hardware-Beschreibungssprache vorliegenden Entwurf ebenfalls vollautomatisch die für die Fertigung einer integrierten Schaltung erforderlichen Daten erzeugt werden. Tatsächlich ist dies - und wird es voraussichtlich auch bleiben - ein Traum. Der dazu erforderliche "Übersetzungsprozess" ist derartig komplex und aufwändig, dass er nur als Abfolge von zahlreichen unterschiedlichen Entwurfsschritten mit zunehmendem Detaillierungsgrad beherrscht werden kann. Viele dieser Schritte sind heute automatisiert bzw. teilautomatisiert. Wir sprechen dabei von Entwurfsautomatisierung (Electronic Design Automation, EDA) und sind damit beim eigentlichen Gegenstand dieser Vorlesung angelangt.
EDA als solches ist ein aktueller Forschungsgegenstand, dessen Status sich kontinuierlich verändert. In dieser Vorlesung wird der heutige Stand dargestellt, wobei der Schwerpunkt auf den grundsätzlichen Prinzipien und Algorithmen liegt. Der aktuelle Stand in der Praxis kann davon im Detail abweichen. Wichtig ist deshalb, die grundsätzliche Vorgehensweise und die zugrundeliegenden Zusammenhänge zu verstehen. Dies soll, anhand exemplarischer Beispiele vermittelt werden.
Seite 1 von 11.1.6 EDA - Electronic Design Automation
Application specific Circuit
Hardware Description Language
Design
EDA-Reality
EDA-Dream“Silicon Compiler”
Source: Prof. Barker Uni EDA-Skript (http://edascript.ims.uni-hannover.de/)
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Cope with Complexity — Divide & Conquer
34
Idea
Design Problem
divide& conquer
divide& conquer
Partitioning the Design Process
Partitioning the Object under design
(Circuit)
Part1 e.g. address decoder
Part1 e.g.ALU
Design Step 1 e.g. Synthesis
Design Step 2 e.g. Verification
Design Step 2 e.g. Placement
Source: Prof. Barker Uni EDA-Skript (http://edascript.ims.uni-hannover.de/)
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
EDA Tooling in IC Design
• Description/Specification
• Generation
• Synthesis
• Analysis/Simulation
• Optimisation
• Verification
35
System-LevelAlgorithmic LevelRegister-Transfer
Logic LevelTransistor
BehaviouralView Structural
View
Geometrical/Physical View
Electrical
Logic Optimisation
High-Level Synthesis
Logic Synthesis
Modul Generation
Layout VerificationSynthesis
Analysis
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
Circuit Design Process - Waterfall
36
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
37
• Hardware verification takes up 70-80% of ASIC design time
•Hardware has to be correct: Design errors are expensive!!! – Re-design: rising costs for masks >> 3 million USD per ASIC
•Hardware verification is costly: – Functional Simulation, Design Rule Check, Equivalence Checks,
Timing Analysis, Board Validation – “compute farms”: IBM 500 Workstations, Intel Pentium 4
>> 1000 Workstations
•Hardware design teams are big and spread
•Hardware design is entry for any software design activities
Specifics in Designing/Engineering Hardware
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
38
Hardware Complexity Example
Increasing Complexity: – Gate count: (2004)
• Lucent 40GBit/s Sonet/SDH/G709 processing >> 10 million gates
– Simulation time: • 1 Sonet/SDH frame >> 10 min sim time (real-time ca. 1 usec!!) • general testcase: 10 - 100 frames per simulation run • special testcase >> 300 frames • total >> 1000 testcases
about 350 days simulation time
verification team: 14 people, using parallelization, compute-farms - regression runs about 3 days
design team: 4 people!!
Department ET/ITChair for Circuit and System Design
Prof. U. HeinkelCHEMNITZ UNIVERSITY OF TECHNOLOGY
39
EDA is a partner in IC Design
EDA-Industry's to do: – Adjust algorithms (e.g. layout, calculation of conductor length/
capacity) – Adjust methods to new parameters/data sets (e.g. Physical
Synthesis, i.e. first perform pre-synthesis with approximated placing, then layout, to better estimate conductor length)
– Simulation/Verification methods (cycle-based, transaction-based, ability to simulate larger systems ( = more data) in the same amount of time)
– More formal methods!!!
Goal: able to handle the new and larger systems.