EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 0.1 Process: Focus on Change Challenges & Directions Technology Paradigm Shifts Market Segment Semiconductor

EDA Roadmap Taskforce Report Draft 2 2/9/99

Figure 0.1 Process: Focus on Change

Challenges& Directions

TechnologyParadigmShifts

MarketSegment

SemiconductorProcess

Design Methodology

ElectronicDesignAutomation

Research


Figure 0.2 Technology Trends

1998 2003

Feature Size

Interconnect Delays and Signal Integrity

Clock Freq

Power & Signal Integrity

Device Count

1998 2003

Designer Productivity

1998 2003


1u .8u .6u .35u .25u .18u .13u .1u

Clock Freq(MHz)

10

100

1000

10000

Process

Actual Freq

Design

chip

Process Min Geometry

Based on Information provided by Shakhar Borkar, Intel

Figure 0.3 Design Pushing Frequency Through Architecture and Circuit Changes


Figure 0.4 Power Rises Sharply

1u .8u .6u .35u .25u .18u .13u .1u

1

10

100

1000

Process Min Geometry

.1

AMPS

chip



Figure 1.1 Target Chip Data Sheet

Design Size:

Total Transistors 200 million

Total Logic Transistors 50 million

Chip I/Os 4000

Wiring levels 8

Scaling:

Target Process for Microprocessors 100nm (2003 Starts for 2005 Ship)

Chip Size 520 mm2

Frequency:

Local Clock Freq. 3.5 GHz

3rd Harmonic = 9GHz

Slew rate = 150Ghz

Chip Statistics

Chip I/Os: 4000

Wiring levels 8

Total Interconnect length 2840 m/chip


Figure 1.2 Global and Local Delays vs. Gate-Device Delays

Delay (ns)

.01

.1

1

Process Minimum Geometry (nm)130 100 70

Device Delay

1 mm Interconnect

1 cm Buffered Interconnect


Figure 1.3 Taskforce Objective

The Taskforce objectiveTaskforce objective is to find approaches to design larger chipslarger chips with fewer engineersfewer engineers while being concerned about more detailmore detail. This report identifiesreport identifies enhancements and modifications to semiconductor semiconductor processingprocessing, , design methodologydesign methodology and electronic design electronic design automationautomation that the Taskforce feels is necessary to reach this objective.


Figure 2.1 Growth in Active Capacitance

Process Minimum Geometry (nm)

130 100 70

.1

1

Active C nf/mm2



Figure 2.2 More Supply Current

Relative


130 100 70

1

2

3

Frequency

1

2

3

Density

1

2

3

Power



Figure 2.3 Power / Voltage = Current


130 100 70

10

100

1000

Power (watt)

.1

1

10

Vcc (volt)

10

100

1000

Current (Amp)



Figure 2.4 Increased Power / Current: Taskforce Recommendations

• Semiconductor Process Changes Required for Increased Power

– Additional Metal Layers for Power Planes

– Additional Metal Layers for Shielding

– On Chip Decoupling Capacitors

• Power Management Design Methodology

– Increase Usage of Gated Clocks

– Staggered Clock

– Self Timed and Asynchronous Design

• Design Automation Required for Increased Power

– Early Prediction of Power

– Self-Inductive and Mutual-Inductive Effects to Signal Line Avoidance Software.

– Power Dependent Timing Verification


Figure 3.1 Gate / Interconnect Delay


Figure 3.2 Delay and Signal Integrity Data

Gate Delay 3psOn Chip Parameter Variability +/-10%

Average Interconnect Delay 12ps

Time of Flight 5ps/mm

Interconnect Resistance 100 ohms/mm

Self Inductance Signal Lines 0.5nh/mm

Mutual Inductance signal to signal 0.3nh/mm

Crosscap 0.2pf/mm

Crosscap to Signal lines .6 Cinterconnect / Ctotal

Reflections Non--terminated long routes above 9Ghz

RF antenna 2.5mm


Figure 3.3 Delay VariationContributed by A Kahng

Delay Relative to Delay with no Crosstalk for different amounts of coupling

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

0.00 1.00 2.00 3.00 4.00 5.00

Relative Slope

50% coupling

100% coupling

10% coupling


a

b

ff

A

B

FF

... ...

Figure 3.4 Signal Interrelationships


Figure 3.5 Signal Integrity and Delay Uncertainty: Taskforce Recommendations

• Semiconductor Process Changes Required for Signal Integrity and Delay Uncertainty

– Additional Metal Layers for Shielding

– Low mutual capacitance and low mutual inductance between signals including power

• Signal Integrity Design Methodology

– Hierarchical Design that is Interconnect Centric

– Staggered Signals

• Design Automation Required for Signal Integrity

– Physical Design that is Signal Integrity Aware

– Multi-Port Delay Models

– Multi-Path Timing Analyzer

– Interconnect Centric Design Tools which emphasize High Level Physical Design.


Figure 4.1 Guiding Principles

•Avoid problems•Verify once•Interconnect centric design•Tether design changes


Figure 4.2 Meet in the Middle Design Approach

•After Architecture •Full Chip Layout •Forecast Block Specifications

•Create Blocks•Actively Avoid Problems

•Add Shielding•Add Buffers•Build / Backannotate Models•Verify Block

•Verify Chip Using Models


Figure 4.3 Interconnect Centric Design System

MODEL BUILDER

CHIP DESIGN

LIBRARY / PROTOTYPES/GENERATORS/EXPERIENCE

ARCHITECTURE

MICRO-ARCHITECTURE

TAPEOUT

FORECASTING

VERIFICATION

VERIFICATION


Figure 4.4 Forecasting

•Budgets / Specifications•Power Distribution•Built -in-Test•Dominant Signal (Such As Clock and Reset)•Block Delay Distribution•Signal Integrity•Soft Error Control•Area / Pinout•Function

•Audit Design vs. Budget


Figure 4.5 Automated Model Builder

•Estimates•Experience•History•Intellectual Property•Generators•Prototyping

•Model Building•In-place Models Including Interconnection•Backannotate Physical Design Characteristics•Full Range of Design Parameters


Fig 5.1 Test Cost Impact on Product Pricing

1.00 E+00

1.00 E-01

1.00 E-02

1.00 E-03

1.00 E-04

1.00 E-05

1.00 E-061982

1985

1988

1991

1994

1997

2000

2003

2006

2009

Co

st p

er t

ran

sist

or

(cen

ts)

Yeararr

Silicon manufacturingTest equipmentdepreciation

2012

Source: Gadi Singer, VTS ‘97 Keynote (Design & Test, Sept., 1997)


Fig 5.2 Yield Loss due to Guard Banding

1,000

Tim

e in

ns

yiel

d lo

ss in

per

cen

t

100

10

0.1

1

1980

1985

1990

1995

2000

2005

2010

2015

Year

Silicon speed

OTAPotential yieldloss

Source: Gadi Singer, VTS ‘97 Keynote (Design & Test, Sept., 1997)


Fig 5.3 Cost Per Burn-in Socket Position

Product - Source: Intel; from an MCC proposal

8086 286 386 486 386SL P5

$400

$300

$200

$100

$0


Fig 5.4 Time to Market and Volume Increasing

Time to volumerampTime to prod. tapeou

t

Time to market(weeks)

i486(

tm)processor

Pentium (r)processor

0 20

40

60

80

100

Source: Carbine and Feltman (Intel) at ITC‘97

Time to MarketTime to Volume


Fig 5.5 Temperature and Voltage Stress Identifies Faulty Behavior

23

27

31

35

110 100 90 80 70 60 50 40 30

Temperature (deg. C)

3.7 2.52.93.320

30

40

50

VDD Voltage (V)

La

tch

-latc

h m

inim

um

de

lay

(ns)

La

tch

-latc

h m

inim

um

de

lay

(ns)

Source: Sematech “Test Methods” Study

Good device

Delay test failures

Good device

Delay test failures

Delay vs. VDD Voltage: 5 delay fails, 1 controlDelay vs. VDD Voltage: 5 delay fails, 1 controlTemperature vs. Delay: 2 delay fails, 1 controlTemperature vs. Delay: 2 delay fails, 1 control


Fig 6.1 Current Systems

Tool 1

Database

Tool 2

DatabaseInterchangeFormat 1 Xlator 1 Tool 3

Database

InterchangeFormat 2

Xlator 2 Tool 4

Database

InterchangeFormat 3


Database

Tool 1

CO InterfaceDatabase

Tool 2

CO Interface

Database

Tool 3

CO Interface

Database

Tool 4

CO Interface

Fig 6.2 Component Object Systems


Figure 7.1 Process Modifications

•Power Delivery•Power and Ground Planes•On chip and/or On MCM Bypass Capacitors

•Signal Integrity Assurance•Shielding•Low mutual capacitance and mutual inductance materials


Figure 7.2 New Design Methodologies

•Signal Integrity Design Methodology•Meet-at-the-full-chip level Design Approach•Hierarchical Design that is Interconnect Centric•Staggered Signals and Asynchronous Logic

•Rules Based Design•Constraints•Top Down Forecasting•Bottom up Model Building


Figure 7.3 Interconnect Centric EDA

MODEL BUILDER

CHIP DESIGN

LIBRARY / PROTOTYPES/GENERATORS/EXPERIENCE

MICRO-ARCHITECTURE

FORECASTING

VERIFICATION


Figure 8.1 CMOS Charge is Decreasing

0

50

100

150

200

250

300

350

400

450

500

1997 1999 2001 2003 2006

YearF

ea

ture

Siz

e (

um

)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Vd

d (

Vo

lts

)

Features (um ) Relative Q V dd


Figure 8.2 Soft Errors in CMOS and SOI

Substrate

Bulk CMOS SOI

n+ n+ p+ p+ n+ n+ p+ p+

+-+-

+-

+- +-

+-+-

+-+-

+-

+-+-

+-

+-+-

+-+-

+-Oxide Insulator

Documents

EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 0.1 Process: Focus on Change Challenges & Directions Technology Paradigm Shifts Market Segment Semiconductor