ECSE-6680: Term Project

Advanced VLSI:Verilog Viterbi Decoder: Synopsis

Implementation

Dane KouttronMaxim TsupkoAlbert Barasa

Rensselaer Polytechnic Institute

December 18, 2009

Dane Kouttron Albert Barsa Maxim Tsupkokouttd@rpi.edu barsaa@rpi.edu tsupkm@rpi.edu6319781650 9142156041 9177339539

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Contents

1 Purpose 3

2 Background 32.1 Viterbi In Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 Viterbi Algorithm Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.3 Viterbi Decoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3.1 Branch Metric Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3.2 Decoding: Add-Compare-Select . . . . . . . . . . . . . . . . . . . . . 52.3.3 Traceback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Discussion of Synopsis Simulations 63.1 Synopsis VerSim Output for Branch Mertic Debugging . . . . . . . . . . . . 73.2 Synopsis VerSim Output for Traceback debugging . . . . . . . . . . . . . . . 83.3 Synopsis VerSim Output for Final Verilog Testbench . . . . . . . . . . . . . 93.4 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Conclusion 10

5 References 10

6 Appendix 116.1 A1: Verilog Test File 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116.2 A2: Viterbi Final Test Bench File . . . . . . . . . . . . . . . . . . . . . . . . 14

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Verilog Viterbi Decoder:Synopsis Implementation and Optimization

1 Purpose

This paper details the inner workings of the Viterbi algorithm, implemented in Verilog, oper-ating under the synopsis Verilog synthesis c 209.06 SP2 compilation and virsim simulationenvironment. The algorithm in general is used to find the most-likely state transition se-quence in a state diagram, given a sequence of input signals. Using recursion, the Viterbialgorithm finds the most likely transition for each state.

2 Background

2.1 Viterbi In Communications

The Viterbi algorithm is commonly used in a wide range of communications and data storageapplications. Its use range from baseband detection for wireless systems all the way todetection of recorded data in magnetic disk drives. The requirements for the Viterbi decoderdepend on the applications where they are used. This results in very wide range of requireddata throughputs and power or area requirements. On the low bandwidth portion of viterbiusage, cellular telephones, operating on the order below 1Mb/s, operate, while having tomaintain very low energy dissipation requirement. In this instance, the viterbi is used fortrellis code demodulation in telephone line modems, where the throughput is in the rangeof tens of kb/s, with very tight limits on power dissipation and reduced chip size. On theother end of the bandwidth spectrum, very high speed Viterbi detectors are used in magneticdisk drive read channels, with throughputs over 600Mb/s1Digital Integrated Circuits. Thealgorithm is very useful in a multitude of communication applications.

2.2 Viterbi Algorithm Operation

Viterbi algorithm operation is expressed in time-indexed state diagrams, termed trellis di-agrams. Trellis diagrams are arranged in states, each of which corresponds to a pattern ofreceived data and each branch of the trellis corresponds to the reception of the next input.2

1Digital Integrated Circuits – A Design Perspective 2/e: Wiley Printing2Parallel Logic Simulation of Million-Gate VLSI Circuits, C.Tropper, T. Zhang. IEEE 2005

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2.3 Viterbi Decoder Implementation

The viterbi decoder can be broken into 3 separate stages, Branch Metric Unit which calcu-lates all the branch metric distance, decoding, costing

2.3.1 Branch Metric Unit

At each recursion, there are 3 major steps in Viterbi detection, generation of branch metrics,updating survivor paths and path metrics to trace the most likely path. The branch metricunit, herein referred to as the BMU, is the squared distance between the received noisyinput Yn and the ideal noiseless output from that transition event 3. Thus, for the transitionfrom state i to state j at recursion n, the base (Equation 1) is listed below.

EQ: 1BranchMetric UnitCalculation

Bi,j,n = (Yn − Ci,j)2

Wherein Ci,j is defined as the output symbol of the transition state from i to j, for a point atrecursion state n. Furthermore, this branch metric, defined earlier as the squared distancebetween the noisy input and the output of the transition. We can define the output of thebranch metrics as in Equation 2:

EQ: 2BranchMetricTotal Rep-resentation

Bi,j,n = −2ynCi,j + (Ci,j)2

Ci,j , defined earlier as the output of the transition from state i to j, can be precomputedand squared [ (Ci,j)

2 ] for determining the branch metric state.

3Implementing The Viterbi Algorithm, IEEE 1995. HUI-Ling Lou

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2.3.2 Decoding: Add-Compare-Select

The second function is sometimes termed as the ‘add-compare-select’ unit, or ACS. Itspurpose is to select the optimal path to each state in the viterbi trellis. A simple exampleof an ACS block listed in figure a. Below, displayed in figure 1, is a state transition map fora constraint length of 3.

Fig: 1StateTransitionsfor L=3Add-Compare-Select

For the add-compare-select unit a new value of the state metric is computed at each step,and thus on every clock cycle. The ACS unit becomes rather large as it can not be pipelinedto increase throughput. For example, for a trellis with N states, a state-parallel decoderimplements N units that operate in parallel. Below is an excerpt from 4Digital IntegratedCircuits, displaying a block diagram of an ACS unit.

Fig: 2BlockDiagram ofAdd-Compare-Select

4Digital Integrated Circuits – A Design Perspective 2e Wiley Press

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As displayed, the ACS operates as the new branch metrics are added to the previous statemetrics to create the candidates for the new state metrics. The comparison can be done byusing the subtraction of the two candidate state metrics and the most significant bit of thedifference automatically directs to the larger of the two candidate states.

2.3.3 Traceback

The traceback function In the trace back function, the decision values and branch labels ofthe most recent trellis stages are stored, decoding is performed by starting at an arbitrarystate in stage and then tracing back from it, in order to reach the correct state, notablythe one with the shortest path. The tracing is then continued from this state. Finally, thebranch labels are read out as decoded data5Traceback Techniques. While this tracing backthough the trellis is being performed, the state metrics, decision values and branch metricsfor succeeding stages are being calculated and stored. 6Traceback Techniques

3 Discussion of Synopsis Simulations

There were some issues getting synopsis simulations to operate properly. On the providedTS Ecse systems, there was no library linked for synthesis of verilog code in Synopsys. Afterprolonged investigation we found that the was a library provided in /cad/tech/lib/TSMC 65ng. A local Synopsys dc.setup file was edited to include that library. However the synthesizedverilog file causes many ”Unresolved modules” errors during common elaboration. Due tothese errors, we were unable to preform accurate power and area estimations. Once thecause of these problems were determined, simulations were easier to complete.

5GENERALIZED TRACE BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT INTHE VITERBI ALGORITHM, R. Cypher, IBM RESEARCH. pp 4

6GENERALIZED TRACE BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT INTHE VITERBI ALGORITHM, R. Cypher, IBM RESEARCH. pp 8

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3.1 Synopsis VerSim Output for Branch Mertic Debugging

Using the verilog file listed in Appendix A.1, our output is displayed above. It was used todebug the Branch Metric Unit BMU. As displayed in 3.1, we managed to observe the n2

distance between states, as described and depicted in Equations 1 and 2. Once we ascertainedthat the distances were in fact squared, we moved on to getting the ACS to operate properly.

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3.2 Synopsis VerSim Output for Traceback debugging

Using the verilog file listed in Appendix A.1, our output is displayed above. This outputdepicts our debug process for having a working ACS. As shown, the system was incrementingthrough the computed branch metric units.

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3.3 Synopsis VerSim Output for Final Verilog Testbench

Using the verilog file listed in Appendix A.2, our output is displayed above. The abovedisplays the entire system simulated, with a functioning Branch Metric Unit that reliablycreated the required squared distance parameters. Our Add-Compare-Select unit also func-tioned, outputting the correct decision sequence for the design constraints.

3.4 Notes

Documentation for synopsis is lacking at best, lack of access to man pages, or Linux languagemanuals, was a severe setback to completing the project. Online information for synopsis isalso sparse, and tutorials were designed for a much older version, which no longer supportssome of the command-set. A good majority of information for verilog and synopsis usagewas found from 7MIT OpenCourseware, or other educational institutions online resources.

7www.ocw.mit.edu

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4 Conclusion

Given a sequence of inputs the viterbi algorithm computes the most likely sequence in thegiven trellis recursively. at each point in the recursion, the system runs through the afore-mentioned sections; Branch Metric Unit generation, Path Metrics, and Traceback ofthe most likely path. Path Metrics are recomputed by serialized Add-Compare-Select units.The ACS’s are connected according to the trellis diagram. Trackback only traces back 5 6times K, where it finds the node whithin the larges cost and again repeats the same processstarting at that node.

5 References

1. Implementing the Viterbi Algorithm, IEEE 1995. HUI-Ling Lou

2. High-Speed Parallel Viterbi Decoding: Algorithm and VLSI-Architecture: IEEE May1991 G. Fettweis.

3. Viterbi algorithm sample educational verilog file. lahtermaher.orghttp://ftp.lahtermaher.org/pub/hardware/opencores/ecc/VitK3/viterbi.v

4. Parallel Logic Simulation of Million-Gate VLSI Circuits, C.Tropper, T. Zhang. IEEE2005

5. Digital Integrated Circuits – A Design Perspective. Borivoje Nikolic. Prentice Hall2003

6. GENERALIZED TRACE BACK TECHNIQUES FOR SURVIVOR MEMORY MAN-AGEMENT IN THE VITERBI ALGORITHM, R. Cypher, IBM Research

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6 Appendix

6.1 A1: Verilog Test File 1

The following is a sample test run used to construct the branch metric portion of our Virtubidecoder simulation. Code excerpts were used from Tsinghua University’s Specification ofViterbi HDL Code.

// B=1, symbol num=2, W=4, V=1, U=1// para po ly s=91 121// Support Di rec t Traceback , Synchronous Ram

‘ inc lude ” g l b d e f . v”

‘ d e f i n e DEC NUM 32 // equal to 2ˆ(w+v )‘ d e f i n e RAM BYTE WIDTH 32 // DEC WIDTH∗DEC NUM‘ d e f i n e RAM ADR WIDTH 9 // the s i z e of ram i s 1024 b i t s , l e t t i n g i t be powof two makes address gene ra t i on work we l l .‘ d e f i n e OUT STAGE RADIX 6 // the number of s t a g e s of one tracebackoutput . I t should be pow of two . The s tage i s the s tage of encode l a t t i c e ofrad ix r .‘ d e f i n e OUT NUM RADIX 7 // rad ix of output number of DECS of one tracebackac t i on . I t i s equal U+OUT STAGE RADIX‘ d e f i n e OUT STAGE 64 // 2ˆOUT STAGE RADIX

‘ d e f i n e SLICE NUM 2 //2ˆu‘ d e f i n e CODE LEN 32768 // the l ength of the code source .‘ d e f i n e CLK TIME 1 // the c y c l e time of c l o ck mclk

module t e s t f i x d a t a ;reg unpunctured code [ ‘CODE LEN−1 : 0 ] ;reg mclk ;reg r s t ;reg v a l i d i n ;reg [ ‘ Bit Width −1:0 ] symbol0 , symbol1 ;reg [ ‘SYMBOLS NUM−1:0 ] pattern ;i n t e g e r i , j ;

i n i t i a l $readmemb ( ” . . / . . / t e s t v e c t o r /91 121 101 91 / code 8192 32768 . dat ” ,unpunctured code ) ;i n i t i a lbegin

mclk=1;r s t =1;pattern =‘SYMBOLS NUM’ b11 ;

v a l i d i n =0;# 50 r s t =1;# 5000 r s t =0;

end

i n i t i a l f o r e v e r # ‘CLK TIME mclk=˜mclk ;

always @( posedge mclk or posedge r s t )begin

i f ( r s t )begin

i =0;j =0;v a l i d i n <=0;

symbol0<=0;symbol1<=0;

pattern <=‘SYMBOLS NUM’ b11 ;

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endelsebegin

i f ( j==0) beginv a l i d i n <=1;

i f ( unpunctured code [ i +0]==1’b1 )symbol0<=‘Bit Width ’ b111 ;

elsesymbol0<=‘Bit Width ’ b000 ;

i f ( unpunctured code [ i +1]==1’b1 )symbol1<=‘Bit Width ’ b111 ;

elsesymbol1<=‘Bit Width ’ b000 ;

endj=j +1;

i f ( j ==‘SLICE NUM)begin

i=i +‘SYMBOLS NUM;j =0;

endi f ( i ==‘CODE LEN)

$ f i n i s h ;end

end

wire decoder out , decoder en ;

decoder d e c o d e r i(

. mclk ( mclk ) ,

. r s t ( r s t ) ,

. v a l i d i n ( v a l i d i n ) ,

. symbol0 ( symbol0 ) ,

. symbol1 ( symbol1 ) ,

. pattern ( pattern ) ,

. b i t o u t ( decoder out ) ,

. v a l i d o u t ( decoder en )) ;

i n t e g e r f decode r out , l i n e ;reg source data [ ‘CODE LEN−1 : 0 ] ;i n t e g e r data count ;i n i t i a lbeginl i n e =0;data count =0;f d e c o d e r o u t=$fopen ( ” f d e c o d e r o u t ” ) ;endi n i t i a l $readmemb ( ” . . / . . / t e s t v e c t o r /91 121 101 91 / data 8192 32768 . dat ” ,source data ) ;always @( posedge mclk or posedge r s t )begin

i f ( ! r s t ) // i t i s not r e s e tbegin

i f ( decoder en )begin

i f ( decoder out !==source data [ data count ] ) begin$d i sp l ay ( ”missmatch at l i n e %d\n” , data count ) ;$ f w r i t e ( f decode r out , ”missmatch ! %b , %b\n” , decoder out ,

source data [ data count ] ) ;end else begin

i f ( data count !=0 && data count%256==0) $d i sp l ay ( ” compare

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data i s c o r r e c t at %d\n” , data count ) ;$ f w r i t e ( f decode r out , ”%b” , { decoder out } ) ;$ f w r i t e ( f decode r out , ”\n” ) ;

enddata count=data count +1;

/∗$ f w r i t e ( f decode r out , ”%b” , { decoder out } ) ;i f ( l i n e %4==3)begin

$ f w r i t e ( f decode r out , ”\n” ) ;endi f ( l i n e %16==15)begin

$ f w r i t e ( f decode r out , ”\n” ) ;endl i n e=l i n e +1;∗/

endend

end

i n i t i a lbegin

$dumpfi le ( ” v i t e r b i d . dump” ) ;$dumpvars (0 , t e s t f i x d a t a ) ;

endendmodule

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6.2 A2: Viterbi Final Test Bench FileThe following is the final testbench file for our groups Viterbi simulation. Code excerpts were used from Tsinghua University’sSpecification of Viterbi HDL Code, and OPENCORES.ORG ’s data on verilog viterbi systems.

//BASED ON WORK FROM OPENCORES.ORG///

// B=1, symbol num=2, W=4, V=1, U=1// para po ly s=91 121// Support Di rec t Traceback , Synchronous Ram

‘ inc lude ” g l b d e f . v”

‘ d e f i n e DEC NUM 32 // equal to 2ˆ(w+v )‘ d e f i n e RAM BYTE WIDTH 32 // DEC WIDTH∗DEC NUM‘ d e f i n e RAM ADR WIDTH 9 // the s i z e of ram i s 1024 b i t s , l e t t i n g i tbe pow of two makes address gene ra t i on work we l l .

‘ d e f i n e OUT STAGE RADIX 6 // the number of s t a g e s of one traceback output .I t should be pow of two . The s tage i s the s tage of encode l a t t i c e of rad ix r .

‘ d e f i n e OUT NUM RADIX 7 // rad ix of output number of DECS of onetraceback ac t i on . I t i s equal U+OUT STAGE RADIX‘ d e f i n e OUT STAGE 64 // 2ˆOUT STAGE RADIX

‘ d e f i n e SLICE NUM 2 //2ˆu‘ d e f i n e CODE LEN 32768 // the l ength of the code source .‘ d e f i n e CLK TIME 1 // the c y c l e time of c l o ck mclk

module t e s t f i x d a t a ;reg unpunctured code [ ‘CODE LEN−1 : 0 ] ;reg mclk ;reg r s t ;reg v a l i d i n ;reg [ ‘ Bit Width −1:0 ] symbol0 , symbol1 ;reg [ ‘SYMBOLS NUM−1:0 ] pattern ;i n t e g e r i , j ;

i n i t i a l $readmemb ( ” . . / . . / t e s t v e c t o r /91 121 101 91 / code 8192 32768 . dat ” , unpunctured code ) ;i n i t i a lbegin

mclk=1;r s t =1;pattern =‘SYMBOLS NUM’ b11 ;v a l i d i n =0;

# 50 r s t =1;# 5000 r s t =0;

end

i n i t i a l f o r e v e r # ‘CLK TIME mclk=˜mclk ;

always @( posedge mclk or posedge r s t )begin

i f ( r s t )begin

i =0;j =0;v a l i d i n <=0;

symbol0<=0;symbol1<=0;

pattern <=‘SYMBOLS NUM’ b11 ;endelsebegin

i f ( j==0) beginv a l i d i n <=1;

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i f ( unpunctured code [ i +0]==1’b1 )symbol0<=‘Bit Width ’ b111 ;

elsesymbol0<=‘Bit Width ’ b000 ;

i f ( unpunctured code [ i +1]==1’b1 )symbol1<=‘Bit Width ’ b111 ;

elsesymbol1<=‘Bit Width ’ b000 ;

endj=j +1;

i f ( j ==‘SLICE NUM)begin

i=i +‘SYMBOLS NUM;j =0;

endi f ( i ==‘CODE LEN)

$ f i n i s h ;end

end

wire decoder out , decoder en ;

decoder d e c o d e r i(

. mclk ( mclk ) ,

. r s t ( r s t ) ,

. v a l i d i n ( v a l i d i n ) ,

. symbol0 ( symbol0 ) ,

. symbol1 ( symbol1 ) ,

. pattern ( pattern ) ,

. b i t o u t ( decoder out ) ,

. v a l i d o u t ( decoder en )) ;/MODIFIED TESTING FILE//i n t e g e r f decode r out , l i n e ;reg source data [ ‘CODE LEN−1 : 0 ] ;i n t e g e r data count ;i n i t i a lbeginl i n e =0;data count =0;f d e c o d e r o u t=$fopen ( ” f d e c o d e r o u t ” ) ;endi n i t i a l $readmemb ( ” . . / . . / t e s t v e c t o r /91 121 101 91 / data 8192 32768 . dat ” , source data ) ;always @( posedge mclk or posedge r s t )begin

i f ( ! r s t ) // i t i s not r e s e tbegin

i f ( decoder en )begin

i f ( decoder out !==source data [ data count ] ) begin$d i sp l ay ( ”missmatch at l i n e d\n” , data count ) ;$ f w r i t e ( f decode r out , ”missmatch ! b , b\n” ,decoder out , source data [ data count ] ) ;

end else begini f ( data count !=0 && data count%256==0) $$ f w r i t e ( f decode r out , ”b” , { decoder out } ) ;$ f w r i t e ( f decode r out , ”\n” ) ;

enddata count=data count +1;

/∗$ f w r i t e ( f decode r out , ”b” , { decoder out } ) ;

15

i f ( l i n e %4==3)begin

$ f w r i t e ( f decode r out , ”\n” ) ;endi f ( l i n e %16==15)begin

$ f w r i t e ( f decode r out , ”\n” ) ;endl i n e=l i n e +1;∗/

endend

endendmodule

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