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3. CMOS Inverters: Switching CharacteristicsThe switching characteristics combined with interconnect effects determine the overalloperating speed of digital systems. Therefore, the switch speed of gates and interconnecteffects must be estimated and optimized very early in the design phase to ensure circuitreliability and performance. This section investigates the dynamic (time domain)behaviour (switch speed) of the inverter.
Introduction
Consider the cascade connection of two CMOS inverter circuits shown in Fig. 3.1. Theparasitic capacitances associated with each MOSFET are:
gdC and gsC : The gate to drain and gate to source capacitance are primarily due to thegate overlap with diffusion.
dbC and sbC : The drain to body and source to body capacitances are voltagedependent junction capacitances.
gC : the gate capacitance is due to the thin-oxide capacitance over the gate area. intC : The interconnect capacitance represents the parasitic capacitance contribution of
the metal or polysilicon connection between the two inverters.
It is assumed that a pulse wave form is applied to the input of the first-stage inverter. Theobjective is to analyze the time-domain behaviour of the first-stage output outV .
Figure 3.1 Cascaded CMOS inverter stages
The problem of analyzing the output voltage waveform is fairly complicated, even forthis relatively simple circuit, since a number of nonlinear voltage dependent capacitancesare involved. To simplify the problem, the capacitances of Fig 3.1 are converted to alumped linear capacitance connected between the output node of the inverter to ground,as shown in Fig. 3.2, where loadC is defined as
gpdbndbpgdngdload CCCCCCC int,,,, (3.1)
Note some of the parasitic capacitance components shown in Fig. 3.1 do not appear inthis lumped capacitance expression. Since the source-to-substrate voltages of bothtransistors are always equal to zero, the capacitances nsbC , and psbC , are zero. Thecapacitances ngsC , and pgsC , are also not included because they are connected between theinput node and ground (or power supply).
Using Fig 3.2, the inverter transient response is reduced to finding the charge-up andcharge-down times of a single capacitance which is charged and discharged through onetransistor. The delay times calculated using a single using loadC may be slightlyoverestimate the actual inverter delay, but this is not considered a significant deficiency ina first-order approximation.
Figure 3.2 First stage CMOS inverter with lumped output load capacitance
Delay-Time Definitions
This section describes some commonly used delay definitions. The input and outputvoltage waveforms of a typical inverter are shown in Fig. 3.3. The propagation delaytimes PHL and PLH determine the input-to-output signal delay during high-to-low andlow-to-high transitions of the output, respectively. By definition, PHL is the time delaybetween the %50V -transition of the rising input voltage and the %50V -transition of thefalling output voltage. Similarly, PLH is defined as the time delay between the %50V -transition of the falling input voltage and the %50V -transition of the rising output voltage.
Figure 3.3 Input and output voltage waveforms of a typical inverter and the definitions ofpropagation delay times. The input voltage waveform is idealized as a step response.
To simplify the analysis of the delay expressions, the input voltage is usually assumedto be an ideal step pulse with zero rise and fall times. Under this assumption, PHL
becomes the time required for the output voltage to fall from OHV to %50V level, and PLH
becomes the time required for the output voltage to rise from OLV to %50V level. Thevoltage %50V is defined as
)(21)(
21
%50 OLOHOLOHOL VVVVVV (3.2)
The propagation delay times PHL and PLH labelled in Fig. 6.3 are defined as
01 ttPHL
23 ttPHL (3.3)
The average propagation delay P of the inverter characterizes the average time requiredfor the input signal to propagate through the inverter
2PLHPHL
P
(3.4)
Fig. 3.4 provides the definitions of the output voltage rise and fall times. The rise timerise is defined here as the time required for the output voltage to rise from the %10V level
to the %90V level. Similarly, the fall time fall is defined here as the time required for theoutput voltage to fall from the %90V level to the %10V level. The voltage levels %10V and
%90V are defined as
Figure 3.4 Output voltage rise and fall time
)(1.0%10 OLOHOL VVVV (3.5))(9.0%90 OLOHOL VVVV (3.6)
Thus the rise and fall times defined in Fig. 3.4 are obtained:
ABfall tt
CDrise tt (3.7)
Note that other delay definitions using 20% and 80% voltages levels have also been used.
Calculation of Delay Times
The section describes the average capacitance current method and the capacitance stateequation method to estimate the propagation delay times of PHL and PLH .
Average Current Method
A simple way to calculate the propagation delay times PHL and PLH is based onestimating the average capacitance current during charge down and charge up,respectively. Using the following relationship (i.e. )/( TVCI avg ), if the capacitancecurrent during an output transition is approximated by a constant average current avgI , thedelay times are found as
HLavg
OHload
HLavg
HLloadPHL I
VVCI
VC
,
%50
,
)(
(3.8)
LHavg
OLload
LHavg
LHloadPLH I
VVCI
VC
,
%50
,
)(
(3.9)
The average current during high-to-low transition and low-to-high transition can becalculated by using the current values at the beginning and end of the transitions as
),(),(21
%50, VVVViVVVViI outOHinCOHoutOHinCHLavg (3.10)
),(),(21
%50, VVVViVVVViI outOLinCOLoutOLinCLHavg (3.11)
While the average-current method is relatively simple and requires minimal
calculations, it neglects the variations of the capacitance current between the beginningand end points. Therefore, this approach provides a rough first-order estimates of thecharge-up and charge-down
Capacitance State Equation Method
The propagation delay times can be found more accurately by solving the state equationof the output node in the time domain. The differential equation associated with theoutput nodes is:
nDpDCout
load iiidt
dVC ,, (3.12)
For the rising input case, the output voltage is assumed to be OHV . When the inputvoltages switches from low OLV to high OHV , the nMOS transistor is turned on and itstarts to discharge the load capacitance. At the same time, the pMOS transistor isswitched off and
0, pDi (3.13) The circuit in Fig. 3.2 can now be reduced to Fig. 3.5. The differential equationdescribing the discharge event of Fig. 3.5 is
Figure 3.5 Equivalent circuit of the CMOS inverter during high to low output transition.
nDout
load idt
dVC , (3.14)
The input and output voltage waveforms during this high-to-low transition are illustratedin Fig. 3.6. When the nMOS transistor starts conducting, it initially operates in thesaturation region. When the output voltage falls below ( nTDD VV , ), the nMOS transistorstarts to conduct in the linear region (These two operating regions are labelled in Fig.3.6). First, consider the nMOS transistor operating in saturation.
2,
2,, )(
2)(
2 nTOHn
nTinn
nD VVK
VVK
i for OHoutnTOH VVVV )( , (3.15)
Since the saturation current is practically independent of the output voltage (neglectingchannel-length modulation), the solution of (3.14) is the time interval 0t to '
1t (labelled inFig. 3.6) is
nTOHout
OHout
nTOHout
OHout
VVV
VV outnTOHn
loadVVV
VV outnD
loadtt
ttdV
VVK
CdV
iCdt ,,
'1
0 2,, )(
21 (3.16)
Evaluating (3.16), yields
2,
,0
'1
)(
2
nTOHn
nTload
VVK
VCtt
(3.17)
Figure 3.6 Input and output voltage waveforms during high-to-low transition
At '1tt , the output voltage will be equal to ( nTOH VV , ) and the transistor will be at the
saturation-linear region boundary. Next, consider the nMOS transistor operating in thelinear region.
2,
2,, )(2
2)(2
2 outoutnTOHn
outoutnTinn
nD VVVVK
VVVVK
i for )( ,nTOHout VVV (3.18)
Substituting (3.18) into (3.14) for the time interval '1t and 1t , yields
%50
,
%50
,
1'1 2
,, )(211 VV
VVV outoutoutnTOHn
loadVV
VVV outnD
loadtt
ttout
nTOHout
out
nTOHoutdV
VVVVKCdV
iCdt
(3.19)
Evaluating (3.19), yields
%50
%50,
,
'11
)(2ln
)( VVVV
VVKC
tt nTOH
nTOHn
load (3.20)
The propagation delay time from high to low output ( PHL ) can be found by adding (3.17)and (3.20) and substituting 2/)(%50 OLOH VVV to obtain
1
)(4ln
2)(
,
,
,
, OLOH
nTOH
nTOH
nT
nTOHn
loadPHL VV
VVVV
VVVK
C (3.21)
For the CMOS inverter, DDOH VV and 0OLV , thus (3.21) can be written as
1
)(4ln
2)(
,
,
,
, DD
nTDD
nTDD
nT
nTDDn
loadPHL V
VVVV
VVVK
C (3.22)
When the input voltage switches from high OHV to low OLV , the nMOS transistor is cutoff, and the load capacitance is being charged up through the pMOS transitor. Followinga very similar derivation procedure, the propagation delay time PLH obtained is
1
|)|(2ln
||||2
|)|( %50
,
,
,
, VVVVV
VVVV
VVVKC
OH
pTOLOH
pTOLOH
pT
pTOLOHp
loadPLH (3.23)
Substituting 2/)(%50 OLOH VVV , DDOH VV and 0OLV , into (3.23) yields
1
|)|(4ln
||||2
|)|(,
,
,
, DD
pTDD
pTDD
pT
pTDDp
loadPLH V
VVVV
VVVK
C (3.24)
Comparing the delay equations of (3.22) and (3.24), the sufficient conditions requiredfor PLHPHL ,
|| ,, pTnT VV and pn KK or ( pnnp WW // ) (3.25)
RC Time Constant Method
The RC time constant method calculates the propagation delay by approximating thenMOS and pMOS transistors as resistors. To calculate the propagation delay time fromhigh to low output ( PHL ), the pMOS transistor is in cut off, while the nMOS transistoroperates first in the saturation region and then moves in the linear region. The inputvoltage of the inverter under this scenario is DDOHin VVV and the resistance of thenMOS transistor is approximated as
2
LIN
LIN
SAT
SAT
avIV
IV
R (3.26)
where SATV and LINV correspond to two points on the DI - DSV curve. For example, Fig3.7 selects the two points at
DDSAT VV (3.27)2/)( ,nTDDLIN VVV (3.28)
At SATout VV , the nMOS transistor is in saturation mode, while at LINout VV , the nMOStransistor is in linear mode. Thus, the currents SATI and LINI labelled in Fig 3.7 arecalculated as
Figure 3.7 How to approximate the MOS transistor as a resistor
Vout=VDS
ID Vin=VGS=VDD
VSAT=VDDVLIN=(VDD+VT,n)/2
ILIN
ISAT
2, )(
2 nTDDn
SAT VVK
I (3.29)
2,
2,,
, )(83
2)(
2)(
)(22 nTDD
nTDDnTDDnTDD
nLIN VV
VVVVVV
KI
(3.30)
The discharge of the load capacitance from high to low output voltage is obtained bysolving the RC circuit in which the resistor avR is connected with loadC to obtain
)/( loadav CRtDDout eVV (3.31)
To calculate the propagation delay (3.31) is set to 5.0/ DDout VV , as
)/(5.0 loadavPHL CRe
loadavloadavPHL CRCR 69.0)5.0ln( (3.32)
A similar approach can be developed to calculate the propagation delay from low to highoutput PLH .
Propagation Delay for Finite Rise/Fall Times of Input Signals
The exact calculation of the output voltage delay times is more complicated under themore realistic assumption that the input signal has a finite rise and fall times, r and f .To simplify the estimation of the actual propagation delays, the following empiricalexpressions can be used.
22)()( 2/rinputstepPHLactualPHL (3.33)
22)()( 2/finputstepPLHactualPLH (3.34)
The values )( inputstepPHL and )( inputstepPLH denote the propagation delay time valuescalculated assuming a step pulse input waveform at the input. While the expressions of(3.33) and (3.34) are purely empirical, they provide a simple estimation of how much thepropagation delays are increased as a result of nonzero input rise and fall times.
Methodologies to Improve Propagation Delay Calculations
The delay calculations of (3.8), (3.9), (3.22), (3.24) and (3.32) were derived using thesimple current-voltage relationships originally developed for long-channel transistors(shown below for the nMOS transistor).
2,, )(2
2 DSDSnTGSn
nD VVVVK
i (linear or triode region) tGS VV , tGSDS VVV
2,, )(
2 nTinn
nD VVK
i (saturation region) tGS VV , tGSDS VVV (3.35)
The equations of (3.35) can be replaced with more accurate current-voltage relationshipsto improve the propagation delay calculations; however this usually increases thecomputational complexity of the problem.
Calculation of Output Voltage Rise and Fall Times
The average current method, the differential equation method and the RC time constantmethod can also be used to calculate the output voltage rise and fall times (i.e. fall andrise ). The equations for the average current method are:
),(),(21
)(
%10%90
%10%90
VVVVIVVVVI
VVCI
VC
outOHinoutOHinavg
fall
(3.36)
),(),(21
)(
%10%90
%10%90
VVVVIVVVVI
VVCI
VC
outOLinoutOLinavg
rise
(3.37)
Next, the rise and fall time equations are derived using the differential equation approach.To calculate fall , the nMOS transistor operates in the saturation region for
%90,0 VVVV outnTOH and operates in the linear region for nTOHout VVVV ,0%10 . Following an approach similar to (3.16) and (3.19), the fall time fall is obtained by
solving the following integral
%10
,0
,0
%90
2,
2, )(2
2)(
2 VV
VVV outoutnTOHn
outload
VVV
VVout
nTOHn
loadfall
out
nTOHout
nTOHout
outVVVVK
dVCdV
VVKC
(3.38)
The solution of (3.38) yields
%10
%10,
,2
,
%90, )(2ln
)()(
)(2V
VVVVVK
C
VVK
VVVC nTOH
nTOHn
load
nTOHn
OHnTloadfall (3.39)
Using (3.5), (3.6) and setting 0OLV , DDOH VV (3.39) becomes
DD
nTDD
nTDDn
load
nTDDn
DDnTloadfall V
VVVVK
C
VVK
VVC1.0
29.1ln
)()(
)1.0(2 ,
,2
,
, (3.40)
Following a similar procedure, the rise time rise can be found as
%90
%90,
,2
,
%10, )(|)|(2ln
|)|(|)|(
)|(|2
VV
VVVVV
VVVKC
VVVK
VVVC
OH
OHpTOLOH
pTOLOHn
load
pTOLOHn
OLpTloadrise
(3.41)
Using (3.5), (3.6) and setting 0OLV , DDOH VV (3.41) becomes
OH
pTDD
pTDDn
load
pTDDn
DDpTloadrise V
VVVVK
CVVK
VVC1.0
||29.1ln
|)|(|)|(
)1.0|(|2 ,
,2
,
, (3.42)
The rise and fall times of the output voltage (i.e. fall and rise ) can also be calculatedusing the RC time constant method. Using (3.31), the transition time of fall is measuredbetween the time at which DDout VV 9.0 and DDout VV 1.0 as
loadavloadavfall CRCR
2.2
9.01.0
ln (3.43)
In (3.43), avR is obtained by selecting the two points on the DI - DSV curve to estimatethe average resistance of the transistor between DDout VV 9.0 and DDout VV 1.0 . Anequation similar to (3.43) can also be used to calculate rise .
Inverter Design with Delay Constraints
The design of CMOS logic circuits based on timing (delay) specifications is one of themost fundamental issues in digital circuit design which ultimately determines overallperformance of complex systems. In most cases, the delay constraints should beconsidered together with other design constraints such as noise margins, logic (inversion)threshold, silicon area, and power dissipation.
The goal in this section is to determine the channel dimensions ( nW , pW ) of the nMOSand pMOS transistors which satisfy certain timing requirements. The load capacitance
loadC in (3.1) consists of intrinsic components (parasitic drain capacitances which dependon transistor dimensions) and extrinsic components (interconnect/wiring capacitance andfan-out capacitances which are usually independent of transistor dimensions of theinverter under consideration).
When Cload Consists Mainly of Extrinsic Capacitance Components
If loadC mainly consists of extrinsic components, then the overall load capacitance doesnot significantly change by the transistor dimensions. Under this assumption, loadC istreated as a constant value, independent of the transistor dimensions. Given a required(target) delay value of *
PHL and using (3.22) and )/( nnoxnn LWCK , the require (W/L)-ratio of the nMOS transistor can be found as
1
)(4ln
2
)(,
,
,
,*
DD
nTDD
nTDD
nT
nTDDoxnPHL
load
n
n
VVV
VVV
VVC
CLW
(3.44)
Similarly, the (W/L)-ratio of the pMOS transistor to satisfy a given target value of *PLH
1
|)|(4ln
||||2
|)|(,
,
,
,*
DD
pTDD
pTDD
pT
pTDDoxpPLH
load
p
p
VVV
VVV
VVCC
LW
(3.45)
In most cases, the transistor sizes found from delay requirements must also meet otherdesign requirements such as noise margins and logic inversion threshold.
When Cload is Effected by Intrinsic Capacitance Components
For the case when the intrinsic capacitance causes significant change in the loadcapacitance loadC , increasing the device dimensions nW and pW increases the loadcapacitance loadC . Thus (3.1), which describes the components of the output loadcapacitances becomes
),()()()()( int,,,, pngppdbnndbppgdnngdload WWfCCWCWCWCWCC (3.46)
Note, that the fan-out capacitance gC is also a function of the device dimensions in thenext-stage gate(s). Note that any effort to increase the channel width of nMOS and pMOStransistors in order to reduce delay will inevitably increase the intrinsic components of theload capacitance.
To gain some insight into the transistor sizing problem under delay constraints, and tosimplify the analysis, the load capacitance of equation (3.46) is typically expressed as alinear function with respect to the device dimensions nW and pW , as
ppnnload WWC 0 (3.47)
where 0 , n and p are positive constant coefficients derived by technology-relatedparameters such as doping densities, minimum channel length and physical geometry(layout design rules). Using (3.47), the propagation delay expressions of (3.22) and (3.24)can be written as
n
npnnPHL W
WR )(0 (3.48)
p
ppnpPLH W
WR )/(0 (3.49)
where R is referred to as the transistor aspect ratio, defined as np WWR / , and
1
)(4ln
2)(
,
,
,
, DD
nTDD
nTDD
nT
nTDDoxn
nn V
VVVV
VVVC
L
(3.50)
1
|)|(4ln
||||2
|)|(,
,
,
, DD
pTDD
pTDD
pT
pTDDoxp
pp V
VVVV
VVVC
L
(3.51)
Note that the channel lengths nL and pL are usually fixed and equal to each other and areset by the process technology that is being used. Given the target delay values of *
PHL and*PLH , the minimum channel widths of the nMOS and pMOS transistors which satisfy
these delay constraints can be calculated from (3.48) and (3.49), by solving nW and pW ,respectively.
An important conclusion from (3.48) and (3.49), is that there exists an inherentlimitation to the switching speed in CMOS inverters, due to the parasitic capacitancesthat are functions of nW and pW . It can be seen that increasing nW and pW to reduce thepropagation delay times will have a diminishing influence upon delay beyond a certainvalue, and the delay values will asymptotically approach a limit value for large nW and
pW . From (3.48) and (3.49), the limit delay values are
pnnPHL R (3.52) pnpPLH R / (3.53)
To illustrate some of the fundamental issues of this section, consider the design of aCMOS inverter using 0.8m technology parameters (i.e. The channel lengths of thenMOS and pMOS transistors are mLL pn 8.0 ). The power supply voltage is 3.3V; theextrinsic capacitance component of the load is 100fF. The transistor aspect ratio is
75.2)/( np WWR . Fig. 3.8 shows the SPICE simulations when the transistor width isvaried from mWn 2 to mWn 20 . As expected, the inverter with the smallest transistordimensions ( mWn 2 and mW p 5.5 ) has the largest propagation delay. The delay isreduced by increasing the channel widths of both the nMOS and pMOS devices. Initially,the amount of delay reduction can be significant, however, the delay reduction graduallydiminishes when the transistor widths are further increased, and the delays approach limitvalues due to the technology-related parameters described by (3.52) and (3.53). Fig. 3.9shows the propagation delay PHL as a function of the nMOS channel width. The delayasymptotically approaches a limit value of about 0.2ns, which is mainly determined bytechnology-specific parameters.
Figure 3.8 Simulated output voltage waveforms of CMOS inverter obtained for fivedifferent designs
Figure 3.9 Propagation delay PHL as a function of the nMOS channel width (obtained bySPICE simulation)
Calculating the Parasitic Capacitances
This section describes how to calculate the load capacitance components of (3.46) interms of the width nW and pW
Gate to drain capacitance: ngdC , and pgdC , : nDnoxngd LWCC ,, and pDpoxpgd LWCC ,,
Drain to body capacitance: ndbC , and pdbC , :
neqnjswnnneqnjnnndb KCWXKCXWC ,,,,0, )2( peqpjswpppeqpjpppdb KCWXKCXWC ,,,,0, )2(
Gate capacitance is a function of the device dimensions in the next gate and is equalto.
pgbngbg CCC ,, where nmasknoxngb LWCC ,, and pmaskpoxpgb LWCC ,,
intC : The interconnect capacitance represents the parasitic capacitance contribution ofthe metal or polysilicon connection between the two inverters.
where
oxC is the oxide capacitance defined as oxoxox tC / ( mFeoox /1145.39.3 is thepermittivity of silicon and oxt is the thickness of the oxide layer)
0jC is the zero-bias junction capacitance per unit area jswC is the zero-bias sidewall junction capacitance per unit length eqK is the voltage equivalent factor and ranges from 10 eqK
W, L and X are defined in Fig. 3.10
Figure 3.10 Layout of nMOS transistor used to calculate parasitic capacitancesL
W
X
Lmask
LD
Propagation Delay versus Area
The propagation delay due to the sizing of transistors is inherently limited by the parasiticcapacitance. In fact, the increase in silicon area can be viewed as a design trade-off fordelay reduction, since the circuit speed improvements are typically obtained at theexpense of increased transistor dimensions. Figure 3.11 shows the (Area x Delay) productof the previous example. Based on these results, it can be argued that increasing nW
beyond about 4-5 m will result in a waste of valuable silicon area, since the obtainabledelay reduction is very small beyond that point.
A practical measure used for quantifying design quality is (Area x Delay) product,which takes into account the silicon-area cost of transistor sizing for delay reduction.While the propagation delay asymptotically approaches a limit value for increasingchannel widths, the (Area x Delay) product exhibits a clear minimum around mWn 4 ,indicating the optimum choice both in terms of speed and overall silicon area.
Figure 3.11 Area x delay product of CMOS inverter
Switching Power Dissipation of CMOS Inverters
It was shown in the previous chapter that the DC static power dissipation of a CMOSinverter is quite negligible. However, during switching events, where the output loadcapacitance is charged up or charged down, the CMOS inverter inevitably dissipatespower. This section will derive the expressions for dynamic power consumption of theCMOS inverter.
Consider the CMOS inverter of Fig. 3.2. It is assumed that the input voltage waveformis an ideal step waveform with negligible rise and fall times. The typical input and outputvoltage waveforms and the expected load capacitor current waveforms are shown in Fig.3.12. When the input switches from low to high, the pMOS transistor is turned off andthe nMOS transistor starts conducting. This causes loadC to discharge through the nMOStransistor. When the input switches from high to low, the nMOS transistor is turned off
and the pMOS transistor starts conducting. This causes loadC to charge through the pMOStransistor.
Assuming periodic input and output waveforms, the average power dissipated by anydevice over one period T, is:
T
avg dttitvT
P0
)()(1 (3.54)
During switching, the nMOS and pMOS transistors in a CMOS inverter conduct currentfor one-half period each. The average power dissipated by the CMOS inverter iscalculated as
T
T
outloadoutDD
Tout
loadoutavg dtdt
dVCVVdt
dtdV
CVT
P2/
2/
0
)(1
(3.55)
Evaluating (3.55), yields
221DDloadDDloadavg VfCVC
TP (3.56)
Figure 3.12 Typical input output voltage and the capacitor current waveform duringswitching of the CMOS inverter
where Tf /1 . The average power dissipation of a CMOS inverter is proportional to theswitching frequency f. Therefore, the low power advantage of CMOS circuits becomesless prominent in high-speed operation, where the switching frequency is high.Furthermore, the average power dissipation is independent of all transistor characteristicsand transistor sizes.
The switching power expression derived for the CMOS inverter also applies to generalCMOS circuits as shown in Fig 3.13. For an ideal step waveform with negligible rise andfall times, it is assumed that either the pMOS block or nMOS block can conductdepending on the input voltage combination. Thus, for general CMOS circuits, switchingpower is dissipated mainly for charging and discharging the output capacitance.
Figure 3.13 Generalized CMOS logic circuit
Measuring Power using SPICE Simulation
The following technique can be used to estimate the average power dissipation ofarbitrary circuits (including the effects of short circuit and leakage currents). Consider thecircuit shown in Fig. 3.14. The additional circuitry consists of a zero volt independentvoltage source connected in series with the power supply voltage, a linear current-controlled current source, a capacitor and a resistor. The current equation at voltage nodeyV (Fig. 3.14) is expressed as
y
ys
yy R
Vi
dt
dVC (3.57)
The time domain solution of yV for an initial condition of 0)0( yV is
Figure 3.14 The power meter circuit used for the simulation of average dynamic powerdissipation of an arbitrary circuit
dieC
tV DD
tCR
t
yy
yy )()(0
(3.58)
Setting the resistance and capacitance values to satisfy TCR yy and settingTCV yDD / , reduces (3.58) reduces to
diT
VtVt
DDDDy 0
)(1)( (3.59)
Note that (3.59) corresponds to the average power drawn from the power supply sourceover one period. Thus the voltage yV at t=T gives the average power dissipation.
The power meter circuit of Fig. 3.14 can easily be implemented in SPICE to calculatethe average power dissipation of arbitrary circuits. In addition, this technique takes intoaccount the additional power dissipation due to short-circuit currents, which may arisebecause of nonideal input conditions as well as leakage currents.
Power-Delay Product
The power delay product is the average energy required for a gate to switch its outputvoltage from low to high and from high to low and is defined as
0
)()( dttitvEPDP average (3.60)
Following the analysis of (3.55)-(3.56), the amount of energy required to switch theoutput is
2DDloadVCPDP (3.61)
The energy of (3.61) is mainly dissipated as heat when the nMOS and pMOS transistorsconduct current during switching.
Note that calculating PDP using (3.61) and average power using (3.56) may result in amisleading interpretation of the amount of energy/power used by the circuit (due toleakage and short-circuit currents) . Thus design engineers often use (3.56) and (3.61) forperformance comparisons.
