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ECE 260B – CSE 241A Partitioning & Floorplanning 1 http:/ /vlsicad.ucsd.edu
ECE260B – CSE241AWinter 2005
Partitioning & Floorplanning
Website: http:/ /vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B – CSE 241A Partitioning & Floorplanning 2 http:/ /vlsicad.ucsd.edu
Key Design Stages
Synthesis
Partitioning
Floorplanning
Power/ground Generation
Clock Generation
Placement
Routing
ECE 260B – CSE 241A Partitioning & Floorplanning 3 http:/ /vlsicad.ucsd.edu
Floorplanning
ECE 260B – CSE 241A Partitioning & Floorplanning 4 http:/ /vlsicad.ucsd.edu
Floorplanning Input
Design netlist (required)
Area requirements (required)
Power requirements (required)
Timing constraints (required)
Physical partitioning information (required)
Die size vs. performance vs. schedule trade-off (required)
I/O placement (optional)
Macro placement information (optional)
ECE 260B – CSE 241A Partitioning & Floorplanning 5 http:/ /vlsicad.ucsd.edu
Floorplanning Output
Die/block area
I/Os placed
Macros placed
Power grid designed
Power pre-routing
Standard cell placement areas
Design ready for standard cell placement
ECE 260B – CSE 241A Partitioning & Floorplanning 6 http:/ /vlsicad.ucsd.edu
Floorplanning Output
ECE 260B – CSE 241A Partitioning & Floorplanning 7 http:/ /vlsicad.ucsd.edu
Floorplan
data path
RAMstd cell
blocks
I/O pads
Routing channels
Blocks inside a pad frame
Routing inside, between blocks
Different-sized blocks more difficult than standard cells to place and route
Blocks● Hard, soft, semi-soft
● Rectangular, L-shaped, T-shaped, rectilinear
● Can rotate, mirror, …
Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Partitioning & Floorplanning 8 http:/ /vlsicad.ucsd.edu
Design Styles
Full Customized● Analog / RF
● CPU design
ASIC (Application Specific IC)● Gate array / sea of gate / standard cells
● Via programmable
● Structured ASICs
Programmable Logics● PLA
● FPGA
Software implementation● Micro-code
Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Partitioning & Floorplanning 9 http:/ /vlsicad.ucsd.edu
Size Estimation
Why we care: ● If area is too small: P&R will not finish or meet timing, will run too long
● Schedule and die size inversely related
● Performance and die size have complex relationship
Rule of thumb (must correct for power, clock, etc.):- 3LM: Cell utilization 65 percent / / what is utilization?
- 4LM: Cell utilization 70 percent
- 5LM: Cell utilization 75 percent
- 6LM: Cell utilization 80 percent
Floorplan metrics● Low interconnect density Cell util (standard cell area/standard cell row area)
● High interconnect density “Net util” (number of nets/standard cell area)
Die size
Physical Design SchedulePerf
Die size
ECE 260B – CSE 241A Partitioning & Floorplanning 10 http:/ /vlsicad.ucsd.edu
Channels
Channels end at block boundaries
Alternate channel definitions possible, depending on position of blocks A
B C
channel 1
ch 2
ch 1 ch 2ch 3
A
B C
A
B C
Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Partitioning & Floorplanning 11 http:/ /vlsicad.ucsd.edu
Channel Intersection Graph
Nodes are channels, edges correspond to pairs of channels that touch
Channel graph shows paths between channels
Channel graph can be used to guide global routing
A BC
D
E
Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Partitioning & Floorplanning 12 http:/ /vlsicad.ucsd.edu
Channel Ordering
Wire out end of one channel creates pin on side of next channel
“Wheel” = Circular constraints that create an unroutable configuration of channels
channel A
channel B
constraint
A B
CD
Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Partitioning & Floorplanning 13 http:/ /vlsicad.ucsd.edu
Slicing Floorplan Represented by Binary Tree
A slicing floorplan can be recursively cut in two without cutting any blocks
A slicing floorplan is guaranteed to have no “wheels”, therefore guaranteed to have a feasible order of routing for the channels
A slicing floorplan can be represented as a binary tree, with internal nodes representing slices in the floorplan and leaves representing blocks.
Courtesy K. Yang, UCLA
A
B
C
D
E
1
23
4
12 3
4A B C
D E
ECE 260B – CSE 241A Partitioning & Floorplanning 14 http:/ /vlsicad.ucsd.edu
O-Tree
Partial ordering based on projection overlapping (with given physical locations)
Transforming into binary trees by pivoting, etc.
Coded in a node sequence given a tree traversal algorithm
● E.g., OACBDEF for DFS
Condensed solution spaceB
C
D E
F
Courtesy K. Yang, UCLA
A
O
ECE 260B – CSE 241A Partitioning & Floorplanning 15 http:/ /vlsicad.ucsd.edu
Sequence Pair
Based on layout partitions by non-overlapping ascending/descending staircases
Coded in two node sequences ● E.g., CEDFAB for descending
staircases and
● ABCDEF for ascending staircases
Larger solution space, finer representation
B
C
D E
F
Courtesy K. Yang, UCLA
A
ECE 260B – CSE 241A Partitioning & Floorplanning 16 http:/ /vlsicad.ucsd.edu
Partitioning
ECE 260B – CSE 241A Partitioning & Floorplanning 17 http:/ /vlsicad.ucsd.edu
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)
ECE 260B – CSE 241A Partitioning & Floorplanning 18 http:/ /vlsicad.ucsd.edu
Partitioning
Decomposition of a complex system into smaller subsystems
● Done hierarchically
● Partitioning done until each subsystem has manageable size
● Each subsystem can be designed independently
Interconnections between partitions minimized● Less hassle interfacing the subsystems
● Communication between subsystems usually costly● Time-budgeting
ECE 260B – CSE 241A Partitioning & Floorplanning 19 http:/ /vlsicad.ucsd.edu
Example: Partitioning of a Circuit
Input size: 48
Cut 1=4Size 1=15
Cut 2=4Size 2=16 Size 3=17
ECE 260B – CSE 241A Partitioning & Floorplanning 20 http:/ /vlsicad.ucsd.edu
Hierarchical Partitioning
Levels of partitioning:● System-level partitioning:
Each sub-system can be designed as a single PCB
● Board-level partitioning:Circuit assigned to a PCB is partitioned into sub-circuitseach fabricated as a VLSI chip
● Chip-level partitioning:Circuit assigned to the chip is divided into manageable sub-circuitsNOTE: physically not necessary
ECE 260B – CSE 241A Partitioning & Floorplanning 21 http:/ /vlsicad.ucsd.edu
Delay at Different Levels of Partitions
AB
C
PCB1
D
x
10x
20xPCB2
ECE 260B – CSE 241A Partitioning & Floorplanning 22 http:/ /vlsicad.ucsd.edu
Partitioning: Formal Definition
Input:● Graph or hypergraph
● Usually with vertex weights
● Usually weighted edges
Constraints● Number of partitions (K-way partitioning)
● Maximum capacity of each partitionORmaximum allowable difference between partitions
Objective● Assign nodes to partitions subject to constraints
s.t. the cutsize is minimized
Tractability● Is NP-complete
ECE 260B – CSE 241A Partitioning & Floorplanning 23 http:/ /vlsicad.ucsd.edu
Hypergraphs in VLSI CAD
Circuit netlist represented by hypergraph
Slides Courtesy Kia Bazargan, U. Minn
ECE 260B – CSE 241A Partitioning & Floorplanning 24 http:/ /vlsicad.ucsd.edu
Hypergraph Partitioning in VLSI
Variants● directed/undirected hypergraphs
● weighted/unweighted vertices, edges
● constraints, objectives, …
Human-designed instances
Benchmarks● up to 4,000,000 vertices
● sparse (vertex degree » 4, hyperedge size » 4)
● small number of very large hyperedges
Efficiency, flexibility: KL-FM style preferred
ECE 260B – CSE 241A Partitioning & Floorplanning 25 http:/ /vlsicad.ucsd.edu
Some Notations
A net n is cut by a cluster C if at least one, but not all, pins of n is in C.
We use E(C) to denote the set of nets cut by a cluster C.
We use E(P) to denote the set of nets cut by at least one cluster of a partition P.
We use w(C) to denote the no. of cells assigned to a cluster C.
ECE 260B – CSE 241A Partitioning & Floorplanning 26 http:/ /vlsicad.ucsd.edu
Some Bipartitioning Formulations
Min-Cut Bipartitioning:● Objective : Minimize F(P2) = |E(C1)| = |E(C2)|
Min-Cut Bisection:● Objective : Minimize F(P2) = |E(C1)| = |E(C2)|
● Constraint : |w(C1) - w(C2)| ≤ ε
Size-Constrained Min-Cut Bipartitioning:● Objective : Minimize F(P2) = |E(C1)| = |E(C2)|
● Constraint: L ≤ w(C1), w(C2) ≤ U
Minimum Ratio Cut Bipartitioning:● Objective :
Minimize F(P2) = |E(C1)|/ (w(C1)×w(C2))
ECE 260B – CSE 241A Partitioning & Floorplanning 27 http:/ /vlsicad.ucsd.edu
Some Multi-Way Partitioning Formulations
Size-Constrained Min-Cut k-Way Partitioning:● Objective : Minimize F(Pk)
● Constraint: L ≤ w(Ci) ≤ U ∀ Ci ∈ Pk
Many other complicated formulations
k-way partitioning: Formulation Given a netlist of n cells V = {v1, v2, …, vn}, assign the
cells to k clusters Pk = {C1, C2, …, Ck} satisfying some given constraints such that an objective function F(Pk) is optimized.
Partitioning: k is small O(1)
Clustering: k is large O(n)
Technology Mapping: Constraints on the clusters
ECE 260B – CSE 241A Partitioning & Floorplanning 28 http:/ /vlsicad.ucsd.edu
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)
ECE 260B – CSE 241A Partitioning & Floorplanning 29 http:/ /vlsicad.ucsd.edu
Kernighan-Lin (KL) Algorithm
On non-weighted graphs
An iterative improvement technique
A two-way (bisection) partitioning algorithm
The partitions must be balanced (of equal size)
Iterate as long as the cutsize improves:● Find a pair of vertices that result in the largest decrease in
cutsize if exchanged
● Exchange the two vertices (potential move)
● “Lock” the vertices
● If no improvement possible, andstill some vertices unlocked, thenexchange vertices that result in smallest increase in cutsize
W. Kernighan and S. Lin, Bell System Technical Journal, 1970.
ECE 260B – CSE 241A Partitioning & Floorplanning 30 http:/ /vlsicad.ucsd.edu
Kernighan-Lin (KL) Algorithm
Initialize● Bipartition G into V1 and V2, s.t., |V1| = |V2| ± 1
● n = |V|
Repeat● for i=1 to n/2
- Find a pair of unlocked vertices vai∈ V1 and vbi∈ V2 whoseexchange makes the largest decrease or smallest increasein cut-cost
- Mark vai and vbi as locked
- Store the gain gi.
● Find k, s.t. ∑ i=1..k gi=Gain k is maximized
● If Gain k > 0 then move va1,...,vak from V1 to V2 and vb1,...,vbk from V2 to V1.
Until Gain k ≤ 0
ECE 260B – CSE 241A Partitioning & Floorplanning 31 http:/ /vlsicad.ucsd.edu
An Example
a b c d
a
b
c
d
0 1 2 3
1 0 1 4
2 1 0 3
3 4 3 0
a
b d
c
1
2
31
4
3
Slides courtesy F. Y. Young, U. Hong Kong
ECE 260B – CSE 241A Partitioning & Floorplanning 32 http:/ /vlsicad.ucsd.edu
An Example - Pass One
a
b d
c
1
2
31
4
3
g(a,c) = -1+3-3+1 = 0g(a,d) = -1+2-3+4 = 2g(b,c) = -1+4-3+2 = 2g(b,d) = -1+1-3+3 = 0
g1 = 2
d
b a
c
4
3
31
1
2
g(b,c) = -4+1-2+3 = -2g2 = -2
d
c a
b
3
4
31
2
1
∴ G = g1 = 2 (k = 1)
ECE 260B – CSE 241A Partitioning & Floorplanning 33 http:/ /vlsicad.ucsd.edu
An Example - Pass Two
d
b a
c
4
3
31
1
2
g(a,b) = -2+3-4+1 = -2g(a,d) = -2+1-4+3 = -2g(c,b) = -2+3-4+1 = -2g(c,d) = -2+1-4+3 = -2
g1 = -2
b
g(a,b) = -3+2-1+4 = 2g2 = 2
G = g1 + g2 = 0 (k = 2)STOP!
a
dc
1
3
4 2 31
dc
a b1
3
31 42
ECE 260B – CSE 241A Partitioning & Floorplanning 34 http:/ /vlsicad.ucsd.edu
Cut During One Pass (Bipartitioning)
Moves
Cut
ECE 260B – CSE 241A Partitioning & Floorplanning 35 http:/ /vlsicad.ucsd.edu
Kernighan-Lin (KL) : Analysis
Time complexity?● Inner (for) loop
- Iterates n/2 times
- Iteration 1: (n/2) x (n/2)
- Iteration i: (n/2 – i + 1) (n/2 – i + 1).
● Passes? Usually independent of n
● O(n3)
Drawbacks?● Local optimum
● Balanced partitions only
● No weight for the vertices
● High time complexity
● Only on edges, not hyper-edges
ECE 260B – CSE 241A Partitioning & Floorplanning 36 http:/ /vlsicad.ucsd.edu
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)
ECE 260B – CSE 241A Partitioning & Floorplanning 37 http:/ /vlsicad.ucsd.edu
Fiduccia-Mattheyses Algorithm: Basic Ideas
Differences from KL:● Move only one cell each time.
● Cells can have different sizes.
● Nets can be multi-terminal.
● Maintain a balanced partition after every move.
ECE 260B – CSE 241A Partitioning & Floorplanning 38 http:/ /vlsicad.ucsd.edu
FM Algorithm
Start with a balanced partition P = {X,Y}.
Repeat● For i = 1 to n:
- Choose a free cell b ∈ X∪Y s.t. moving b to the other side gives the highest gain, gain(b), and moving b preserves balance in P.
- Move and lock b.
- Let gi = gain(b).
● Find k s.t. G = g1 + g2 + ….. + gk is maximized and shuffle the cells up to this kth step.
Until G = 0.
ECE 260B – CSE 241A Partitioning & Floorplanning 39 http:/ /vlsicad.ucsd.edu
An Example
abc
def
ac
defb
locked
ac
df
be
ac f
be
d
g1
g2
g3
g4
ECE 260B – CSE 241A Partitioning & Floorplanning 40 http:/ /vlsicad.ucsd.edu
An Example
cf
be
dg5
a
fb
e
d g6
ac
be
d a
cf
If G = g1 + g2 + g3 + g4 is the largest partial sum,the partition after this pass is:
cde
afb
ECE 260B – CSE 241A Partitioning & Floorplanning 41 http:/ /vlsicad.ucsd.edu
Balanced PartitionA partition P = (X,Y) is balanced iff:
for some constant r ≤ 1 where w(X) is the total size of the cells in X. To preserve balance, a cell b is moved in a pass only if:
after moving b where W = w(X∪Y) and Smax is the maximum cell size
w X w X ∪Y
≈r
rW −S max≤w X ≤rW S max
ECE 260B – CSE 241A Partitioning & Floorplanning 42 http:/ /vlsicad.ucsd.edu
KL and FM Extensions: Tie-Breaking Strategy
When picking the highest gain move, break ties by looking ahead a certain number of steps.
If ties still occur, some researchers observe that LIFO order improves solution quality.
ECE 260B – CSE 241A Partitioning & Floorplanning 43 http:/ /vlsicad.ucsd.edu
Ratio of #edges to #vertices
Solution quality of KL and FM depends on the ratio of #edges to #vertices: good if ratio > 5 and bad if ratio < 3. VLSI circuits have ratio 1.8-2.5 typically.
Goldberg and Burstein suggested contracting edges to increase the ratio:
A B AB
ECE 260B – CSE 241A Partitioning & Floorplanning 44 http:/ /vlsicad.ucsd.edu
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)
ECE 260B – CSE 241A Partitioning & Floorplanning 45 http:/ /vlsicad.ucsd.edu
Network Flow Technique
s t
a b
c d
16
13
10 4 9 7
12
20
4
11
s t
a b
c d
11/16
12/13
10 1/4 9 7/7
12/12
19/20
4/4
11/11
min-cut = max-flow
The network flow technique can find the min-cut bipartition optimally, but not necessarily balanced.
Apply the algorithm repeatedly to obtain a balanced bipartition.
ECE 260B – CSE 241A Partitioning & Floorplanning 46 http:/ /vlsicad.ucsd.edu
Network Flow Technique
The network flow technique is very useful in many different research areas.
Many sophisticated improvements have been made to the original algorithm.
Ford & Fulkerson: O(|E||f|) where |f| is the size of the total flow. Note that for unit capacity, |f| ≤ |E|, so O(|E|2) time.
ECE 260B – CSE 241A Partitioning & Floorplanning 47 http:/ /vlsicad.ucsd.edu
Circuit Partitioning
We can apply the network flow algorithm in partitioning circuits.
The biggest problem is that the two partitions may not be balanced.
The problem of obtaining two balanced partitions with minimum cut is NP-complete.
However we can apply some heuristics to balance the two partitions.
ECE 260B – CSE 241A Partitioning & Floorplanning 48 http:/ /vlsicad.ucsd.edu
Flow-Balanced-Bipartition (FBB)
Find a min-cut C = (X,Y) in the network N
If (1-ε)W/2 ≤ w(X) ≤ (1+ε)W/2, stop and return C
If w(X) < (1-ε)W/2 then● Collapse all nodes in X to s
● Collapse to s a node v∈Y incident on a net in C
● Go to to step 1
If w(X) > (1+ε)W/2 … (similarly) ...
Why do we needthis step?
ECE 260B – CSE 241A Partitioning & Floorplanning 49 http:/ /vlsicad.ucsd.edu
Circuit Representation
Another problem in applying the network flow technique in circuit partitioning is how to represent a circuit correctly by a graph.
A B C D
How to represent this netlist by a simple graph?
ECE 260B – CSE 241A Partitioning & Floorplanning 50 http:/ /vlsicad.ucsd.edu
Hypergraph
A B C D
H(V,E) whereV = {A, B, C, D}E = {n1, n2, n3}n1 = {A, B, C, D}n2 = {A, B}n3 = {C, D}
In hypergraph, an edge is a set of vertices.
Circuits can be represented by hypergraphs, but the net-work flow method can only be used in simple graphs.
ECE 260B – CSE 241A Partitioning & Floorplanning 51 http:/ /vlsicad.ucsd.edu
Weighted Undirected Graph
Use a clique to model a net:
A B C D
What should be the edge weights?
“A proper model for the partitioning of electrical circuits”,Schweikert and Kernighan, DAC, 1972.
ECE 260B – CSE 241A Partitioning & Floorplanning 52 http:/ /vlsicad.ucsd.edu
Weighted Undirected Graph
A B C D
1/4
1/4 1/4
1/41/41/4
1/2 1/2
Cut size = 4*1/4 = 1 (Actual cut size = 1)
Cut size = 3*1/4+1/2 = 5/4 (Actual cut size = 2)
edge weight =
n(k) = no. of cells in net k
1n i
ECE 260B – CSE 241A Partitioning & Floorplanning 53 http:/ /vlsicad.ucsd.edu
Weighted Undirected Graph
A B C D
1/3
1/3 1/3
1/31/31/3
1 1
Cut size = 4*1/3 = 4/3 (Actual cut size = 1)
Cut size = 3*1/3+1 = 2 (Actual cut size = 2)
edge weight = 1n i −1
ECE 260B – CSE 241A Partitioning & Floorplanning 54 http:/ /vlsicad.ucsd.edu
Circuit Representation
It is proved that exact modeling of a hypergraph by a graph with positive weights is impossible. [Ihler, Wagner & Wager, 1993]
However, we can model a hypergraph H by a simple graph G such that when we apply the network flow algorithm, the min-cut in G is equal to the min-cut in H.
ECE 260B – CSE 241A Partitioning & Floorplanning 55 http:/ /vlsicad.ucsd.edu
Weighted Directed Graph
A
B
C
A
B
C
∞
∞
∞
∞∞
∞
1
What will happen when we apply the max-flow min-cutalgorithm to the graph G?
Original circuit C: G:
ECE 260B – CSE 241A Partitioning & Floorplanning 56 http:/ /vlsicad.ucsd.edu
Weighted Directed Graph
A B C D
∞∞ ∞
∞
1
∞ ∞∞
∞
1
∞ ∞∞
∞ ∞∞ ∞ ∞
1
ECE 260B – CSE 241A Partitioning & Floorplanning 57 http:/ /vlsicad.ucsd.edu
Modeling a Circuit
d
ab
c
e
f
g
d
s
b
c
e
f
t
C: G:
ECE 260B – CSE 241A Partitioning & Floorplanning 58 http:/ /vlsicad.ucsd.edu
Modeling a CircuitLemma: If C has a cut (X,Y) of size K, G has a cut (X’,Y’) of
size K. If G has a cut (X’,Y’) of size K, C has a cut (X,Y) of size less than or equal to K
Corollary: If (X’,Y’) is the min-cut of G of size K, the corresponding cut (X,Y) in C is also a min-cut of C of size K
Let G = (V’,E’) be the flow network modeling the circuit C = (V,E):
A
B
C
∞
∞
∞
∞∞
∞
1
C: G:
AB
C
|V’| = ?|E’| = ?
ECE 260B – CSE 241A Partitioning & Floorplanning 59 http:/ /vlsicad.ucsd.edu
Efficient Implementation
Repeatedly computing max-flow is time consuming. No need to compute max-flow from scratch in every iteration.
Retain the flow function computed in the previous iteration. Find additional flow to saturate the bridging edges from one iteration to another.
Total time taken for all the iterations is O(|E’||V’|).
ECE 260B – CSE 241A Partitioning & Floorplanning 60 http:/ /vlsicad.ucsd.edu
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)
ECE 260B – CSE 241A Partitioning & Floorplanning 61 http:/ /vlsicad.ucsd.edu
Clustering
Clustering● Bottom-up process
● Merge heavily connected components into clusters
● Each cluster will be a new “node”
● “Hide” internal connections (i.e., connecting nodes within a cluster)
● “Merge” two edges incident to an external vertex, connecting it to two nodes in a cluster
Can be a preprocessing step before partitioning
● Each cluster treated as a single node
3
416
25
64
3
1
1
1
3
46
1,2
5
43
12
3,46
1,2
5
3
12
ECE 260B – CSE 241A Partitioning & Floorplanning 62 http:/ /vlsicad.ucsd.edu
Ratio Cut Objective
It is not desirable to have a pre-defined ratio on the partition sizes.
Wei and Cheng proposed the ratio cut objective ( CXY/ (|X|×|Y|) where CXY is the cut size ). Try to locate natural clusters in the circuit.
A heuristic based on FM was proposed.
ECE 260B – CSE 241A Partitioning & Floorplanning 63 http:/ /vlsicad.ucsd.edu
Multi-Level Partitioning
Clustering
Clustering
Clustering
Applying FM
Unclustering
Unclustering
Unclustering
Refining by FM
ECE 260B – CSE 241A Partitioning & Floorplanning 64 http:/ /vlsicad.ucsd.edu
hMETIS
Freely available at http:/ /www-users.cs.umn.edu/~karypis/metis/hmetis/
Extension of METIS graph hierarchical partitioning tool● Coarsening phase● Refinement phase
See also UCLA MLParthttp:/ /vlsicad.ucsd.edu/GSRC/Slots/Partitioning/MLPart/
initialhypergraph
coarsening phase
refin
emen
t ph
ase
projectedpartition
refinedpartition
randompartition
ECE 260B – CSE 241A Partitioning & Floorplanning 65 http:/ /vlsicad.ucsd.edu
Coarsening
Goal: create a smaller hypergraph such that a good bisection is not significantly than one on the original
How to select the vertices to condense?● edge coarsening
- best matching pairs of hyperedge vertices are collapsed
● hyperedge coarsening- independent set of hyperedges are collapsed
- preference given to maximum weights and small sizes
● modified hyperedge coarsening- hyperedge coarsening followed by collapse of the remaining
vertices that do not belong to another hyperedge
ECE 260B – CSE 241A Partitioning & Floorplanning 66 http:/ /vlsicad.ucsd.edu
Coarsening (cont’d)
edge coarsening hyperedge coarseningmodified hyperedge
coarsening
3 hyperedges12 vertices5.3 pins / hyperedge
3 hyperedges6 vertices3.3 pins / hyperedge
1 hyperedge5 vertices5 pins / hyperedge
1 hyperedge3 vertices3 pins / hyperedge
ECE 260B – CSE 241A Partitioning & Floorplanning 67 http:/ /vlsicad.ucsd.edu
Uncoarsening
Initial partition is a balanced random bisection
Partition is refined at this level● Fiduccia-Mattheyses (FM-EE)
- constrained to only two passes
- each pass is stopped after k zero-gain moves (early-exit)
- Hyperedge Refinement (HER)
– entire hyperedges are moved across the cut
Projection of cut onto more complete hypergraph
ECE 260B – CSE 241A Partitioning & Floorplanning 68 http:/ /vlsicad.ucsd.edu
Outline
Introduction
Kernighan-Lin Algorithm
Fiduccia-Mattheyses Algorithm
Partitioning by Network Flow
Clustering
End-case Partitioning (and Placement)