PowerPoint Presentation

ECE 7366 Advanced Process Integration

Beyond Planar CMOS

Dr. Wanda Wosik

Text Book: B. El-Karek, Silicon Devices and Process Integration11Vds dependenceScaling of Bulk Planar DevicesL dependencelong channelVdsshort channelsource/channel barrierlong channelshort channelVds=0Vds=VddVds=VddVds=0Ioff is determined only by Vt and subthreshold swing SS (~Ctotal/Cox).The electrostatic control of the drain current by the gate gets lostUse additional (double) gate to recover the gate control over IdsEliminate the path of the bulk leakage current use oxide under the channel => SOI

2D retrograde well for Vt control 2Vgslog(Ids)Vds VddIonIoff

Reduce DIBLImprove Ion/Ioff Reduce the short channel effectsThe subthreshold swing S = d(Vgs)/d(log(Id)) = 2.3 KT/q( 1+ Cdep/Cox) Thinner Tox => larger Coxe=> further Cox by high k dielectric Lower substrate doping (less dopant fluctuation) => smaller Cdep Lower temperatureThreshold voltage roll-offLeakage currents including GILD and substrate currents

Use oxide at the substrate and thin channel region above => SOI Use Double (or Multi-) Gate to recover the control over the drain current Electrostatic EffectBulk Planar Devices in the SOI Version

Rotate the gate and obtain FinFet3Current direction

4From Planar Bulk to SOI (Flat) Improvement in Performance and Vt VariabilityIn SOI use:Decreased channel thickness TSi< Lg/4 (fully depleted MOS FETs, Ultra Thin Body &Box); very low Ioff Low doping levels Reduce random dopant fluctuation (RDF) in the channel and at the S/D edgesIncrease carrier mobility5

Skotnicki, Future Fab, 2012Electrostatics of FETsBoth in UTBB and FinFET xj and Tdep determined by geometry not by dopingchannel can be left undopedBOX contributes to Tdep so make ultra thinUTBB allow the substrate (high doped) to be a second gate Vt reductionUltra-Thin-Body SOI MOSFET The subthreshold leakage is reduced as the silicon film is made thinner. Tox=1.5nm, Nsub=1e15cm-3, Vdd=1V, Vgs=0

6C. Hu

ETSOI, IBM K. Cheng et al, IEDM, 2009 State-of-the-Art 5nm Thin-Body SOI 7

Many Challenges of each ot these designs

Thickness uniformity on the SOI wafers must be controlled preciselySmart-Cut process gives 0.5 nm control Device Architecture Options => 3D Planar SOI, FinFET SOI and FinFET bulk.

Planar FDSOIFinFET SOIFinFET bulkPlanar: Ultra thin body UTB (channel thickness) with raised S/DLow doped channel (no RDF)S/D optimization still neededFinFET on silicon bulkFinFET on SOI 8Producing Silicon-on-Insulator (SOI) Substrates

Initial Silicon wafer A and B

Oxidize wafer A to grow SiO2

Implant hydrogen into wafer A

Flip wafer A and place it on wafer B. Anneal at low temperature to fuse both wafers together.

Use a second annealing step to form H2 bubbles and split wafer A.

Polish the surface of the SOI wafer and use it as the substrate.

Wafer A can be reused in the next SOI steps.The challenge is in the thin and uniform Si layer fabrication SOITEC9

Device Architecture and Fabrication10

Hisamoto, 2000

11Drain Current increases with # of fins Fabrication using SOI wafer

FinFETs are 3D Devices

12First FinFET in 1990 on SOI Wg