ECE 555 Digital Circuits & Components ECE555 Lecture 3 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1

ECE 555 Digital Circuits & Components

ECE555ECE555Lecture 3Lecture 3

Nam Sung KimUniversity of Wisconsin – Madison

Dept. of Electrical & Computer Engineering

1

IMPLEMENTATION STRATEGY IMPLEMENTATION STRATEGY FOR DIGITAL ICSFOR DIGITAL ICS

2


Impact of Implementation ChoicesImpact of Implementation Choices

3

Ene

rgy

Eff

icie

ncy

(in

MO

PS

/mW

)

Flexibility

(or application scope)

0.1-1

1-10

10-100

100-1000

None Fully

flexible

Somewhat

flexible

Har

dwire

d cu

stom

Con

figur

able

/Par

amet

eriz

able

Dom

ain

-spe

cific

pro

cess

or

(e.g

. D

SP

)

Em

bedd

ed m

icro

proc

ess

or


Implementation ChoicesImplementation Choices

4

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches


The Custom Approach The Custom Approach

5

Intel 4004

Courtesy Intel


Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

6

Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel


Cell-based Design (or standard cells)Cell-based Design (or standard cells)

7

Routing channel

requirements are

reduced by presence

of more interconnect

layers

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cellR

ow

s o

f ce

lls


Standard Cell — ExampleStandard Cell — Example

8

[Brodersen92]


Standard Cell – The New GenerationStandard Cell – The New Generation

9

Cell-structure

hidden under

interconnect layers


Standard Cell - ExampleStandard Cell - Example

10

3-input NAND cell

(from ST Microelectronics):

C = Load capacitance

T = input rise/fall time


Automatic Cell GenerationsAutomatic Cell Generations

11

Initial transistor

geometries

Placed

transistors

Routed

cell

Compacted

cell

Finished

cell


A Historical Perspective: the PLAA Historical Perspective: the PLA

12

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1


Two-Level LogicTwo-Level Logic

13

Inverting format (NOR-

NOR) more effective

Every logic function can be

expressed in sum-of-products

format (AND-OR)

minterm


PLA Schematics (Logic-level)PLA Schematics (Logic-level)

14


PLA Schematic (Transistor-level)PLA Schematic (Transistor-level)

15


PLA Layout – Exploiting RegularityPLA Layout – Exploiting Regularity

16


Breathing Some New Life in PLAsBreathing Some New Life in PLAs River PLAs

• A cascade of multiple-output PLAs.

• Adjacent PLAs are connected via river routing.

• No placement and routing needed and output buffers and the input buffers of the next stage are shared.

17

PRE-CHARGE

PR

E-

CH

AR

GE

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BUFFER

BU

FF

ER

BU

FF

ER

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BU

FF

ER

PRE-CHARGE

PR

E-

CH

AR

GE

BUFFERB

UF

FE

R

Courtesy B. Brayton


Macro ModulesMacro Modules

18

25632 (or 8192 bit) SRAM

Generated by hard-macro module generator


““Soft” MacroModulesSoft” MacroModules

19


““Intellectual Property”Intellectual Property”

20

A Protocol Processor for Wireless


Semicustom Design FlowSemicustom Design Flow

21

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout

Simulation

Pre-Layout

Simulation

Post-Layout

Simulation

Post-Layout

Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Iter

atio

nD

esig

n It

erat

ion


The “Design Closure” ProblemThe “Design Closure” Problem

22

Iterative Removal of Timing Violations (white lines)


Integrating Synthesis w/ Physical DesignIntegrating Synthesis w/ Physical Design

23

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-Route

Optimization

Place-and-Route

Optimization

Artwork

Netlist with

Place-and-Route Info

Macromodules

Fixed netlists


Late-Binding ImplementationLate-Binding Implementation

24

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based


Gate Array — Sea-of-gatesGate Array — Sea-of-gates

25

rows of

cells

routing channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

Uncommited

Cell

Committed

Cell

(4-input NOR)


Sea-of-gate Primitive CellsSea-of-gate Primitive Cells

26

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation


Sea-of-gatesSea-of-gates

27

Random Logic

Memory

Subsystem

LSI Logic LEA300K

(0.6 m CMOS)

Courtesy LSI Logic


The return of gate arrays?The return of gate arrays?

28

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array(VPGA)

[Pileggi02]

Exploits regularity of interconnect


Prewired ArraysPrewired Arrays Classification of prewired arrays (or field-

programmable devices):• Based on Programming Technique

Fuse-based (program-once) Non-volatile EPROM based RAM based

• Programmable Logic Style Array-Based Look-up Table

• Programmable Interconnect Style Channel-routing Mesh networks

29


Fuse-Based FPGAFuse-Based FPGA

30

antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2 l

Open by default, closed by applying current pulse


Array-Based Programmable LogicArray-Based Programmable Logic

31

PLA PROM PAL

I 5 I 4

O0

I 3 I 2 I 1 I 0

O1O2O3

Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O0

I3 I2 I1 I0

O1O2O3

Fixed AND array

ProgrammableOR array


Programming a PROMProgramming a PROM

32

f0

1 X 2 X 1 X 0

f1NANA

: programmed node


More Complex PALMore Complex PAL

33

From Smith97

programmable AND array (2i 3 jk) k macrocells

j -wide OR array

j

macrocell

productterms

D Q

A

1

j

B

CLK

OUT

C i i inputs

i inputs, j minterms/macrocell, k macrocells


Programmable Logic BlockProgrammable Logic Block 2-input mux

34

FA 0

B

S

1

Configuration

A B S F=

0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X 1 Y1 0 X1 0 Y1 1 1 1

XYXY

XY


Logic Cell of Actel Fuse-Based FPGALogic Cell of Actel Fuse-Based FPGA

35

A

B

SA Y

1

C

D

SB

1

S0S1

1


Look-up Table Based Logic CellLook-up Table Based Logic Cell

36

Out

ln1 ln2

Me

mory In Out

00 00

01 1

10 1

11 0


Array-Based Programmable WiringArray-Based Programmable Wiring

37

Input/output pinProgrammed interconnection

InterconnectPoint

Horizontaltracks

Vertical tracks

Cell

M


Mesh-based Interconnect NetworkMesh-based Interconnect Network

38

Switch Box

Connect Box

Interconnect

Point


Transistor Implementation of MeshTransistor Implementation of Mesh

39


RAM-based FPGA RAM-based FPGA

40

Xilinx XC4000ex

Courtesy Xilinx


Design at a Crossroad: Design at a Crossroad: System-on-a-ChipSystem-on-a-Chip

Embedded applications Embedded applications where cost, performance, where cost, performance, and energy are the real and energy are the real issues!issues!

DSP and control intensiveDSP and control intensive

Mixed-modeMixed-mode

Combines programmable Combines programmable and application-specific and application-specific modulesmodules

Software plays crucial roleSoftware plays crucial role

41

RA

M

500

k G

ates

FP

GA

+ 1

Gbi

t DR

AM

Pre

proc

essi

ng

Mu

lti-

Sp

ectr

alIm

ager

Csy

stem

+2

Gb

itD

RA

MR

ecog

-

niti

on

Analog

64 S

IMD

Pro

cess

orA

rray

+ S

RA

M

Imag

e C

ond

itio

nin

g10

0 G

OP

S

BACKUPBACKUP

42


ProductivityProductivity

43

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

200

3

198

1

198

3

198

5

198

7

198

9

199

1

199

3

199

5

199

7

199

9

200

1

200

5

200

7

200

9

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty


A Simple ProcessorA Simple Processor

44

MEMORY

DATAPATH

CONTROL

INP

UT

/OU

TP

UT


A System-on-a-Chip: ExampleA System-on-a-Chip: Example

45

Courtesy: Philips


Design MethodologyDesign Methodology

Design process traverses iteratively between three abstractions: behavior, structure, and geometry

More and more automation for each of these steps

46


PLA Layout – Exploiting RegularityPLA Layout – Exploiting Regularity

47

f0 f1x0 x0 x1 x1 x2 x2

Pull-up devices Pull-up devices

VDD GNDAnd-Plane Or-Plane

Documents

ECE 555 Digital Circuits & Components ECE555 Lecture 3 Nam Sung Kim University of Wisconsin – Madison Dept. of Electrical & Computer Engineering 1