ECE 497 JS Lecture - 12 Device Technologiesjsa.ece.illinois.edu/ece497js/Lect_12.pdf · BJT vs MOS • Matching –V BEon for bipolar is determined by bandgap –V T on MOS is determined

1Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004

ECE 497 JS Lecture - 12Device Technologies

Spring 2004

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]


NMOS Transistor


Source Drain

Electricfield

inversion layer

y

ρ

chan

nel c

harg

e de

nsity

Source Drain

Electricfield

y

ρ

c han

nel c

h arg

e d e

nsity

L

Source Draindepletionregion

y

ρ

chan

nel c

harg

e de

nsity

L- d d0, GT DS GTV V V> ≥

0, =GT DS GTV V V>

0, smallGT DSV V>

Resistive Region

Nonlinear Region

Saturation Region

MOS Regions of Operation


Capacitance• Gate Capacitance

– CG determines the amount of charge to switch gate– Several distributed components– Large discontinuity as device turns on– At saturation capacitance is entirely between gate

and source22 11

3 2gs gso oxXC C WLCX

− = + − −

22 113 2gd gdo oxC C WLC

X = + − −


CGDO

n+source

n+drain

p-

gate

CGDO

n+source

n+drain

p-

gate

CGDO

n+source

n+drain

p-

gate

0GTV < 0, smallGT DSV V>

0, largeGT DSV V>

Gate Capacitance


MOS Regions of Operation• Resistive Region

– For small VDS, FET is a linear resistor

• Nonlinear Region– Charge distribution nonuniform across channel– Less charge induced in proximity of drain

• Saturation Region– Channel is pinched off– Increase in VDS has little effect– Square-law behavior (wrt VGT)– Acts like a current source

Copyright © by Jose E. Schutt-Aine , All Rights ReservedECE 497-JS, Spring 2004

DS n ox GT DSWI C V VL

µ =

for DS GTV V<<

2

2DS

DS n GT DSVI V Vβ

= −

2

2GT

DS nVI β=

for DS GTV V<

for DS GTV V≥

Resistive Region

Saturation Region

MOS Current-Voltage Equations


• Threshold voltage– Depends on equilibrium potential– Controlled by inversion in channel

• Body Effect– VT varies with bias between source and body– Leads to modulation of VT

Current-Voltage Characteristics


Body Effect

1/ 2 1/ 20( ) (2 ) (2 )T SB T F SB FV V V Vγ φ φ = + + −

ln aBF

i

Nk Tq n

φ

=

( )1/ 22 a

ox

qNC

γ =

Fermi potential of material

Body bias coefficient

Potential on substrate affects threshold voltage


0

100

200

300

400

500

600

700

0 0.5 1 1.5 2 2.5

NMOS

VGS=1.0VGS=1.5VGS=2.0VGS=2.5

IDS

Vds

NMOS IV Curves


nMOS Devices

• Enhancement Mode– Normally off & requires positive potential on gate– Good at passing low voltages– Cannot pass full VDD (pinch off)

• Depletion Mode– Normally on (negative threshold voltage)– Channel is implanted with positive ions (→VT )– Provides inverter with full output swings


Ω/square4Source and drain sheet resistanceRdiff

Ω/square4Gate sheet resistanceRpoly

fF/µm0.2Junction sidewall capacitanceCJSW

fF/µm20.5Junction capacitanceCJ

fF/µm0.1Gate source and drain overlap capacitanceCGSO,CGDO

fF/µm25Gate oxide capacitance per unit areaCox

µA/V250PFET process transconductancekp

µA/V2200NFET process transconductancekn

cm2/Vs100Hole mobilityµp

cm2/Vs400Electron mobilityµn

m/s1.7 × 105Saturation velocityVsat

V1/20.3Body effect parameterγ

V-10.1 Channel modulation parameterλ

V-0.5PFET threshold voltageVTp

V0.5NFET threshold voltageVTn

cm-32.5 × 1017Density of donor ions in PFET channelNd

cm-31.0 × 1017Density of acceptor ions in NFET channelNa

A70Gate oxide thicknesstox

µm0.25Device length (effective)Leff

µm0.35Device length (drawn)Ldrawn

UnitsValueDescriptionSymbolMOS SPICE Parameters


Body

CSB

CGS CGD CGB

CDB

RG

Gate

DrainSourceRS

MOS Parasitics

- Capacitance from gate to other 3 terminals- Diodes to body- Series resistance- Wiring parasitics


-700

-600

-500

-400

-300

-200

-100

0

-2.5 -2 -1.5 -1 -0.5 0

PMOS

VGS=-1.0VGS=-1.5VGS=-2.0VGS=-2.5

VG

S=-

1.0

Vds

PMOS IV Curves


p-

p+ p+

Gate oxideGateSource Drain

Field oxide

n+Channel

Well

PMOS Transistor

-700

-600

-500

-400

-300

-200

-100

0

-2.5 -2 -1.5 -1 -0.5 0

PMOS

VGS=-1.0VGS=-1.5VGS=-2.0VGS=-2.5

VG

S=-

1.0

Vds

- All polarities are reversed from nMOS- Hole mobility is lower ⇒ low transconductance- nMOS favored over pMOS


p-

p+ p+n+

n+n+

inGND VDD

out

p-

Complementary MOS

in out


CMOS• Advantages

– Virtually, no DC power consumed– No DC path between power and ground– Excellent noise margins (VOL=0, VOH=VDD)– Inverter has sharp transfer curve

• Drawbacks– Requires more transistors– Process is more complicated– pMOS size larger to achieve electrical symmetry– Latch up


1 2V V V∆ = − 1 2I I I∆ = −

1 2

2CV VV +

= 1 2

2 2S

CII II +

= =

( )2

2 21 / 4

2 CTCT CTVI V V V V Vβ β∆ = + = + ∆ + ∆

( )2

2 22 / 4

2 CTCT CTVI V V V V Vβ β∆ = − = − ∆ + ∆

2 CTI V Vβ∆ = ∆

Source Coupled Pair


( ) ( )2

0 0 2

DD DDV VDD

sw DD C DD C CCVE V V Idt V V CdV= − = − =∫ ∫

2sig cy sig DD sigP E f CV f= =

2 2DD tog DD D ckP CV f CV K f= =

C

Rn

RP

Power Dissipation in Static CMOS Gate Switching energy dissipated in 0-1 transition

Power dissipation

In terms of duty factor


Bipolar Junction Transistor


Peo

Pco

Wb0

nb(W)

nb(0)

nb

nbo

E B C

' '(0) ( )b b bC b

b

n n WI qADW−

=

q: electron chargeA: Effective area of E-B junctionDb: diffusion constant of electrons in base

BJT – Operating Principle


CMOS vs Bipolar

• Current– Collector current inversely proportional to Wb– Drain current inversely proportional to L

• Topology– Base width is vertical defined by lithography– Channel length is horizontal defined by diffusion

• Behavior– Bipolar current is exponential– MOS current obeys square law


BJT vs MOS

• Matching – VBEon for bipolar is determined by bandgap– VT on MOS is determined by tox and implant

⇒BJTs have superior current drive⇒BJTs switch faster than MOS⇒BJTs dissipate more power⇒BJTs have lower yield⇒BJTs are more costly


• Speed– High electron mobility– Saturation velocity is reached at lower power

• Substrate– Larger bandgap than Si ⇒ semi insulating– SOI, Lower parasitics

• Optical Properties– Direct bandgap ⇒ LED, lasers– Integrate digital and optics on same IC

Gallium Arsenide Transistors


• Physics– Low hole mobility– Low thermal conductivity– More defects and more fragile

• Process– No oxide ⇒ more complex process– Lower level of integration

• Cost– More expensive– Less mature technology

GaAs Limitations


Product

TechnologyToday

TechnologyFuture

Criterion

PA LNA Mixer VCO Filter Switch

SiGaAs

SiSiGe

SiSi

GaAs Si SiGaAs

InPGaAsSiGe

InPGaAs

InPGaAs

InPGaAs MEMS

InPGaAsMEMS

PAE,linearity

Low power Linearity,1/f noise 1/f noise High Q

Isolation,Insertion loss

RF Front End Technologies


Device Technologies for RF ApplicationsDevice Technologies for RF Applications

?858Max resolution (bits)

160???fT (GHz)

low> 10 V> 8 V< 10 Vbreakdown voltage

mediumlowhighdevice scaling

?negligible> 10 mVnegligiblehysteresis or backgating

?1 mV> 10 mV< 1 mVdevice matching

?50X150Xtransconductance

mediumlow?highthermal conductivity

0.31.4-0.8turn on voltage

mediumlow?highlinearity of DC current gain

lowlow-highcol-subst capacitance

highhigh?lowbeta-Early voltage product

lowlow?hightransit time

lowlow-highbase resistance

InP HBTGaAs HBTGaAs MESFETSi Bipolar

Documents

ECE 497 JS Lecture - 12 Device Technologiesjsa.ece.illinois.edu/ece497js/Lect_12.pdf · BJT vs MOS • Matching –V BEon for bipolar is determined by bandgap –V T on MOS is determined