ECE 4401 Digital Design Laboratory Lecture 4 Bus Design ...chandy/courses/4401f08/4401ln04.pdf · •Control logic on all modules. ECE4401 Digital Design Laboratory September 18,

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ECE 4401ECE 4401Digital Design LaboratoryDigital Design LaboratoryLecture 4Lecture 4

Bus Design and MemoriesBus Design and Memories

ECE4401 Digital Design LaboratorySeptember 18, 2008

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Bus StructureBus Structure


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Bus StructureBus Structure


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BusesBuses

•• There are a number of possible interconnection systemsThere are a number of possible interconnection systems

•• Single and multiple bus structures are most commonSingle and multiple bus structures are most common

•• ExamplesExamples–– ISA (Early PCs)ISA (Early PCs)–– PCI (PCs - 1993 and later)PCI (PCs - 1993 and later)–– PCMCIA (Laptops)PCMCIA (Laptops)–– NuBus NuBus ((MacII MacII series)series)–– MicroChannel MicroChannel (IBM PS/2)(IBM PS/2)–– Sbus Sbus (Sun)(Sun)


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BusesBuses

•• AdvantagesAdvantages–– Allows movement of peripheral devices fromAllows movement of peripheral devices from

one system to anotherone system to another–– Easy expandability of systemEasy expandability of system–– Cheaper than point to point connectionsCheaper than point to point connections

•• Sharing of multiple wiresSharing of multiple wires


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BusesBuses

•• DisadvantagesDisadvantages–– Communication bottleneckCommunication bottleneck–– Throughput limited byThroughput limited by

•• Length of busLength of bus•• Number of devices on busNumber of devices on bus•• Slowest device on bus (e.g. PCI-X)Slowest device on bus (e.g. PCI-X)


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A bus transaction includes two parts:Issuing the command (and address) – requestTransferring the data – action

Master (Initiator) is the one who starts the bus transaction by:issuing the command (and address)

Slave (Target) is the one who responds to the address by:Sending data to the master if the master ask for dataReceiving data from the master if the master wants to send data

BusMaster

BusSlave

Master issues command

Data can go either way

Master versus SlaveMaster versus Slave


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Bus DesignBus Design

•• ComponentsComponents–– Data BusData Bus–– Address BusAddress Bus–– Control SignalsControl Signals–– Power/GroundPower/Ground


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Single Bus ProblemsSingle Bus Problems

•• Lots of devices on one bus leads to:Lots of devices on one bus leads to:–– Propagation delaysPropagation delays

•• Long data paths mean that co-ordination of bus use canLong data paths mean that co-ordination of bus use canadversely affect performanceadversely affect performance

•• If aggregate data transfer approaches bus capacityIf aggregate data transfer approaches bus capacity

–– Multiple bus masters can cause contention delaysMultiple bus masters can cause contention delays

•• Most systems use multiple buses to overcome these problemsMost systems use multiple buses to overcome these problems


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Traditional Bus ArchitectureTraditional Bus Architecture


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High Performance BusHigh Performance Bus


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Bus TypesBus Types

•• Processor-Memory Bus (design specific)Processor-Memory Bus (design specific)–– Short and high speedShort and high speed–– Only need to match the memory systemOnly need to match the memory system

•• Maximize memory-to-processor bandwidthMaximize memory-to-processor bandwidth–– Connects directly to the processorConnects directly to the processor–– Optimized for cache block transfersOptimized for cache block transfers

•• I/O Bus (industry standard)I/O Bus (industry standard)–– Usually is lengthy and slowerUsually is lengthy and slower–– Need to match a wide range of I/O devicesNeed to match a wide range of I/O devices–– Connects to the processor-memory bus or backplane busConnects to the processor-memory bus or backplane bus


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North/South Bridge architectures: North/South Bridge architectures: separate bussesseparate busses

•• Separate sets of pins for different functionsSeparate sets of pins for different functions–– Memory busMemory bus–– CachesCaches–– Graphics bus (for fast frame buffer)Graphics bus (for fast frame buffer)–– I/O busses are connected to the backplane busI/O busses are connected to the backplane bus

•• Advantage:Advantage:–– Busses can run at different speedsBusses can run at different speeds–– Much less overall loading!Much less overall loading!

Processor MemoryProcessor Memory Bus

BusAdaptor

BusAdaptor

I/O BusBackplane Bus

I/O Bus

“backsidecache”


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Northbridge and SouthbridgeNorthbridge and Southbridge


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Bus ArbitrationBus Arbitration

•• Only a single device may Only a single device may ““drivedrive”” the bus the bus

•• Many devices can Many devices can ““listenlisten””

•• Must request the busMust request the bus

•• Wait until the request is grantedWait until the request is granted


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•• One of the most important issues in bus design:One of the most important issues in bus design:–– How is the bus reserved by a device that wishes to use it?How is the bus reserved by a device that wishes to use it?

•• Chaos is avoided by a master-slave arrangement:Chaos is avoided by a master-slave arrangement:–– Only the bus master can control access to the bus:Only the bus master can control access to the bus:

It initiates and controls all bus requestsIt initiates and controls all bus requests

–– A slave responds to read and write requestsA slave responds to read and write requests

•• The simplest system:The simplest system:–– Processor is the only bus masterProcessor is the only bus master–– All bus requests must be controlled by the processorAll bus requests must be controlled by the processor–– Major drawback: the processor is involved in every transactionMajor drawback: the processor is involved in every transaction

BusMaster

BusSlave

Control: Master initiates requests

Data can go either way


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•• Bus arbitration scheme:Bus arbitration scheme:–– A bus master wanting to use the bus asserts the bus requestA bus master wanting to use the bus asserts the bus request–– A bus master cannot use the bus until its request is grantedA bus master cannot use the bus until its request is granted–– A bus master must signal to the arbiter the end of the busA bus master must signal to the arbiter the end of the bus

utilizationutilization•• Bus arbitration schemes usually try to balance two factors:Bus arbitration schemes usually try to balance two factors:

–– Bus priority: the highest priority device should be serviced firstBus priority: the highest priority device should be serviced first–– Fairness: Even the lowest priority device should neverFairness: Even the lowest priority device should never

be completely locked out from the bus be completely locked out from the bus


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•• Bus arbitration schemes can be divided into fourBus arbitration schemes can be divided into fourbroad classes:broad classes:–– Daisy chain arbitrationDaisy chain arbitration–– Centralized, parallel arbitrationCentralized, parallel arbitration–– Distributed arbitration by self-selection: each deviceDistributed arbitration by self-selection: each device

wanting the bus places a code indicating its identity on thewanting the bus places a code indicating its identity on thebus.bus.

–– Distributed arbitration by collision detection:Distributed arbitration by collision detection: Each device just Each device just ““goes for itgoes for it””. Problems found after. Problems found afterthe fact.the fact.


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Daisy Chain ArbitrationDaisy Chain Arbitration

BusArbiter

Device 1HighestPriority

Device NLowestPriority

Device2

Grant Grant GrantRelease

Request

wired-OR•• Advantage: simpleAdvantage: simple

•• Disadvantages:Disadvantages:–– Cannot assure fairness:Cannot assure fairness:

A low-priority device may be locked out indefinitely A low-priority device may be locked out indefinitely–– The use of the daisy chain grant signal also limits the busThe use of the daisy chain grant signal also limits the bus

speedspeed


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Centralized ArbitrationCentralized Arbitration

•• Single hardware device controlling busSingle hardware device controlling busaccessaccess–– Bus ControllerBus Controller–– ArbiterArbiter

•• May be part of CPU or separateMay be part of CPU or separate


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Centralized ArbitrationCentralized Arbitration

BusArbiter

Device1

Device NDevice2

Grant Req


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Distributed ArbitrationDistributed Arbitration

•• Each module may claim the busEach module may claim the bus

•• Control logic on all modulesControl logic on all modules


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Bus Transaction ProtocolBus Transaction Protocol

•• Simplest ParadigmSimplest Paradigm

•• All agents operate synchronouslyAll agents operate synchronously

•• All can source / sink data at same rateAll can source / sink data at same rate

•• => simple protocol=> simple protocol–– just manage the source and targetjust manage the source and target


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Bus Transaction ProtocolBus Transaction Protocol

BReq

BG

Cmd+AddrR/WAddress

Data1 Data2Data

•• What if the target takes longer to respond?What if the target takes longer to respond?


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Bus Transaction ProtocolBus Transaction Protocol•• Slave indicates when its ready to transfer dataSlave indicates when its ready to transfer data

•• Data transfer proceeds at bus rateData transfer proceeds at bus rate

BReq

BG

Cmd+AddrR/WAddress

Data1 Data2Data Data1

Wait


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•• Separate versus multiplexed address and data lines:Separate versus multiplexed address and data lines:–– Address and data can be transmitted in one bus cycleAddress and data can be transmitted in one bus cycle

if separate address and data lines are availableif separate address and data lines are available–– Cost: (a) more bus lines Cost: (a) more bus lines vsvs. increased complexity. increased complexity

•• Data bus width:Data bus width:–– By increasing the width of the data bus, transfers of multipleBy increasing the width of the data bus, transfers of multiple

words require fewer bus cycleswords require fewer bus cycles–– Example: SPARCstation 20Example: SPARCstation 20’’s memory bus is 128 bit wides memory bus is 128 bit wide–– Cost: more bus linesCost: more bus lines


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•• Block transfers:Block transfers:–– Allow the bus to transfer multiple words in back-to-Allow the bus to transfer multiple words in back-to-

back bus cyclesback bus cycles–– Only one address needs to be sent at the beginningOnly one address needs to be sent at the beginning–– The bus is not released until the last word isThe bus is not released until the last word is

transferredtransferred–– Cost: (a) increased complexityCost: (a) increased complexity

(b) decreased response time for request (b) decreased response time for request


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Bus PerformanceBus Performance

•• Overlapped arbitrationOverlapped arbitration–– perform arbitration for next transaction during currentperform arbitration for next transaction during current

transactiontransaction

•• Bus parkingBus parking–– master holds onto bus and performs multiple transactionsmaster holds onto bus and performs multiple transactions

as long as no other master makes requestas long as no other master makes request

•• Overlapped address / data phasesOverlapped address / data phases–– requires one of the above techniquesrequires one of the above techniques


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Bus PerformanceBus Performance

•• Split-phase (or packet switched) busSplit-phase (or packet switched) bus–– completely separate address and data phasescompletely separate address and data phases–– arbitrate separately for eacharbitrate separately for each–– address phase yield a tag which is matched with dataaddress phase yield a tag which is matched with data

phasephase

•• Most modern memory and I/O buses use one orMost modern memory and I/O buses use one ormore of these techniquesmore of these techniques


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PCI BusPCI Bus

•• Peripheral Component InterconnectionPeripheral Component Interconnection

•• Intel released to public domainIntel released to public domain

•• 32 or 64 bit32 or 64 bit

•• 49 lines49 lines


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PCI BusPCI Bus


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PCI Bus Lines (required)PCI Bus Lines (required)

•• Systems linesSystems lines–– Including clock and resetIncluding clock and reset

•• Address & DataAddress & Data–– 32 time 32 time mux mux lines for address/datalines for address/data–– Interrupt & validate linesInterrupt & validate lines

•• Interface ControlInterface Control

•• ArbitrationArbitration–– Not sharedNot shared–– Direct connection to PCI bus arbiterDirect connection to PCI bus arbiter

•• Error linesError lines


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PCI CommandsPCI Commands

•• 4 bits of control signals encode the4 bits of control signals encode thecommandcommand–– I/O Read and WriteI/O Read and Write–– Memory Read and WriteMemory Read and Write–– Memory Read MultipleMemory Read Multiple–– Configuration Read and WriteConfiguration Read and Write–– Interrupt AcknowledgeInterrupt Acknowledge


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PCI ProtocolPCI Protocol

•• Basic bus transfer mechanism is a burstBasic bus transfer mechanism is a burst

•• A burst is one address phase followed by one or more dataA burst is one address phase followed by one or more dataphasesphases

•• Three primary signalsThree primary signals–– FRAME# - driven by master to indicate start of transactionFRAME# - driven by master to indicate start of transaction–– IRDY# - driven by master when ready to transfer dataIRDY# - driven by master when ready to transfer data–– TRDY# - driven by target when ready to transfer dataTRDY# - driven by target when ready to transfer data


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PCI Read Timing DiagramPCI Read Timing Diagram


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PCI Write TransactionPCI Write Transaction


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PCI Bus ArbitrationPCI Bus Arbitration

•• Access-BasedAccess-Based

•• Central ArbitrationCentral Arbitration

•• Fairness in ArbitrationFairness in Arbitration–– Each requester is guaranteed accessEach requester is guaranteed access–– But not necessarily equal accessBut not necessarily equal access

•• Master requests bus by asserting REQ# signalMaster requests bus by asserting REQ# signal

•• Arbiter grants bus by asserting GNT# signalArbiter grants bus by asserting GNT# signal


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PCI Bus ArbitrationPCI Bus Arbitration


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PCI Bus ParkingPCI Bus Parking

•• Master can leave REQ# signal assertedMaster can leave REQ# signal asserted

•• Arbiter can leave GNT# signal assertedArbiter can leave GNT# signal asserted

•• Avoids bus arbitration cycleAvoids bus arbitration cycle

•• In most cases, there is only a single masterIn most cases, there is only a single masterso there is no need to do arbitrationso there is no need to do arbitration


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On-Chip BusesOn-Chip Buses

•• Used inUsed in–– FPGAsFPGAs–– SOCsSOCs

•• AMBA (Advanced Microprocessor Bus Architecture)AMBA (Advanced Microprocessor Bus Architecture)

•• CoreConnectCoreConnect

•• WishboneWishbone


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•• How do you connect from the FPGA to theHow do you connect from the FPGA to theoutside world?outside world?

•• Interface logicInterface logic–– Glue logic that connects your system to theGlue logic that connects your system to the

external bus - PCI, ISA, etc.external bus - PCI, ISA, etc.–– Requires that your circuitry understands theRequires that your circuitry understands the

external busexternal bus


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•• Bridge logicBridge logic–– Provides a mapping from internal busProvides a mapping from internal bus

(AMBA, Wishbone, etc.) to external bus(AMBA, Wishbone, etc.) to external bus–– Less efficient in terms of areaLess efficient in terms of area–– Allows internal logic to use a higherAllows internal logic to use a higher

performance busperformance bus


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VHDL for BusesVHDL for Buses

•• OpencoresOpencores.org has a Wishbone to PCI.org has a Wishbone to PCIbridge controllerbridge controller

•• CoreConnect CoreConnect available as an IP core foravailable as an IP core forXilinx Xilinx devicesdevices

•• Altera Altera uses AMBA bus in Excaliburuses AMBA bus in Excaliburprocessor coreprocessor core


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Lab 4Lab 4entity wb_intercon is

generic (num_addr_bits : positive := 32; num_data_bits : positive := 32);port ( ACK_I_M: out std_logic_vector(3 downto 0);

ACK_O_S: in std_logic_vector(3 downto 0); ADR_O_M0: in std_logic_vector( num_addr_bits-1 downto 0 ); ADR_O_M1: in std_logic_vector( num_addr_bits-1 downto 0 ); ADR_O_M2: in std_logic_vector( num_addr_bits-1 downto 0 ); ADR_O_M3: in std_logic_vector( num_addr_bits-1 downto 0 );

ADR_I_S: out std_logic_vector( num_addr_bits-1 downto 0 ); CYC_O_M: in std_logic_vector(3 downto 0); DAT_O_M0: in std_logic_vector( num_data_bits-1 downto 0 ); DAT_O_M1: in std_logic_vector( num_data_bits-1 downto 0 ); DAT_O_M2: in std_logic_vector( num_data_bits-1 downto 0 ); DAT_O_M3: in std_logic_vector( num_data_bits-1 downto 0 ); DWR: out std_logic_vector( num_data_bits-1 downto 0 ); DAT_O_S0: in std_logic_vector( num_data_bits-1 downto 0 ); DAT_O_S1: in std_logic_vector( num_data_bits-1 downto 0 );

DAT_O_S2: in std_logic_vector( num_data_bits-1 downto 0 ); DAT_O_S3: in std_logic_vector( num_data_bits-1 downto 0 ); DRD: out std_logic_vector( num_data_bits-1 downto 0 );

STB_I_S: out std_logic_vector(3 downto 0); STB_O_M: in std_logic_vector(3 downto 0); WE_O_M: in std_logic_vector(3 downto 0); WE: out std_logic;

CLK: in std_logic; RST: in std_logic );end entity wb_intercon;


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Lab 4Lab 4

entity master isPort ( clk_i : in std_logic;

rst_i : in std_logic;adr_o : out std_logic_vector(31 downto 0);

dat_i : in std_logic_vector(31 downto 0); dat_o : out std_logic_vector(31 downto 0); ack_i : in std_logic; cyc_o : out std_logic; stb_o : out std_logic; we_o : out std_logic);end master;


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Lab 4Lab 4

entity wb_slave isPort ( clk_i : in std_logic;

rst_i : in std_logic; adr_i : in std_logic_vector(31 downto 0); dat_i : in std_logic_vector(31 downto 0); dat_o : out std_logic_vector(31 downto 0); ack_o : out std_logic; stb_i : in std_logic; we_i : in std_logic

);end wb_slave;


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Lab 4Lab 4

From Wishbone specFrom Wishbone spec


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Lab 4Lab 4

From Wishbone specFrom Wishbone spec


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MemoriesMemories

Mask-Programmed ROM

Non-volatileMemoryVolatile Memory

EPROMEEPROMFLASHDRAMSRAM

RandomAccess

Read-Write Memory

FIFOLIFO

SequentialAccess

Read-Only Memory


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VHDL code for ROMVHDL code for ROMARCHITECTURE behav OF rom8x4 ISBEGIN

PROCESS(addr)BEGIN

CASE addr IS when "000" => q <= "0001"; when "001" => q <= "0000"; when "010" => q <= "0111"; when "011" => q <= "1101"; when "100" => q <= "1000"; when "101" => q <= "1100"; when "110" => q <= "0110"; when "111" => q <= "1011"; when others => NULL; END case; END process;END behav;

library IEEE;use IEEE.std_logic_1164.all;

ENTITY rom8x4 IS PORT ( addr: in std_logic_vector(2 downto 0); q: out std_logic_vector(3 downto 0));END rom8x4;


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ROMS inROMS in Xilinx Xilinx librarylibrary

•• ROM16x1ROM16x1






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ROMS inROMS in Xilinx Xilinx librarylibrarycomponent ROM16X1-- synthesis translate_off generic (INIT : bit_vector := X"16");-- synthesis translate_on port (O : out STD_ULOGIC;

A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC);end component;

architecture beh of rom isbeginROM16X1_INSTANCE_NAME : ROM16X1-- synthesis translate_off generic map (INIT => hex_value )-- synthesis translate_on port map (O => user_O, A0 => user_A0 , A1 => user_A1, A2 => user_A2, A3 => user_A3 );end architecture


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How do we use ROMHow do we use ROM•• VHDL components in a VHDL designVHDL components in a VHDL design•• Graphical components in a schematicGraphical components in a schematic•• Example using VHDLExample using VHDL

architecture beh of proc is signal ABUS : std_logic_vector(3 downto 0); signal DBUS : std_logic_vector(1 downto 0);beginbit0 : ROM16X1-- synthesis translate_off generic map (INIT => ”1010 1110 0001 0001” )-- synthesis translate_on port map (O => DBUS(0), A0 => ABUS(0), A1 => ABUS(1), A2 => ABUS(2), A3 => ABUS(3) );bit1 : ROM16X1-- synthesis translate_off generic map (INIT => X”1101 1010 1111 0101” )-- synthesis translate_on port map (O => DBUS(1), A0 => ABUS(0), A1 => ABUS(1), A2 => ABUS(2), A3 => ABUS(3) );


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How do we use ROMHow do we use ROM rom_inc : process(CLK) is begin if (CLK’event and CLK=‘1’) then ABUS <= ABUS + 1; end if; end process;

jump : process(DBUS) is begin if (DBUS=“11”) then ABUS <= “0000”; end if; end;

end architecture


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Random Access Memories (Random Access Memories (RAMsRAMs))•• Read/Write memoryRead/Write memory•• Types:Types:

–– Static RAM (SRAM):Static RAM (SRAM):•• Once a word is written at a location, it remains stored asOnce a word is written at a location, it remains stored as

long as power is applied to the chip, unless the samelong as power is applied to the chip, unless the samelocation is written again.location is written again.

•• Fast speed, but their cost per bit higher.Fast speed, but their cost per bit higher.•• Application: Cache memories in MicroprocessorApplication: Cache memories in Microprocessor

–– Dynamic RAM (DRAM):Dynamic RAM (DRAM):•• The data stored at each location must be periodicallyThe data stored at each location must be periodically

refreshed by reading it and then writing it back again, orrefreshed by reading it and then writing it back again, orelse it disappears.else it disappears.

•• Their density is greater and their cost per bit lower, butTheir density is greater and their cost per bit lower, butthe speed is slower.the speed is slower.


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RAMS in RAMS in Xilinx Xilinx librarylibrary

•• Static Block Static Block RAMsRAMs•• Single portSingle port

–– RAMB4_S1, RAMB4_S2, RAMB4_S8,RAMB4_S1, RAMB4_S2, RAMB4_S8,RAMB4_S16RAMB4_S16

•• Dual portDual port–– RAMB4_S1_S1, RAMB4_S1_S2, RAMB4_S1_S1, RAMB4_S1_S2, ……

RAMB4_S16_S16RAMB4_S16_S16


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RAMS in RAMS in Xilinx Xilinx librarylibrarycomponent RAMB4_Sn-- synthesis translate_off generic ( INIT_00 : bit_vector :=

X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector :=

X"0000000000000000000000000000000000000000000000000000000000000000"; . . . );-- synthesis translate_on port (DO : out STD_LOGIC_VECTOR (0 downto 0); ADDR : in STD_LOGIC_VECTOR (11 downto 0); CLK : in STD_ULOGIC; DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; RST : in STD_ULOGIC; WE : in STD_ULOGIC);end component;


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RAMS in RAMS in Xilinx Xilinx librarylibrary

RAMB4_Sn_INSTANCE_NAME : RAMB4_Sn-- synthesis translate_off generic map ( INIT_00 => 64bit_hex_value, INIT_01 => 64bit_hex_value,

. . .INIT_0F => 64bit_hex_value)

-- synthesis translate_on port map (DO => user_DO ,

ADDR => user_ADDR , CLK => user_CLK , DI => user_DI , EN => user_EN , RST => user_RST , WE => user_WE );


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Memory DesignMemory Design

•• DRAM read cycleDRAM read cycle–– Activate RAS, and place row address on busActivate RAS, and place row address on bus–– Row decoders select appropriate rowRow decoders select appropriate row–– Activate CAS, and place column address onActivate CAS, and place column address on

busbus–– Sense amps are activated and data is placedSense amps are activated and data is placed

on the data buson the data bus


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Memory DesignMemory Design

•• DRAM extensionsDRAM extensions–– FPMFPM–– EDOEDO–– SDRAMSDRAM–– DDRDDR–– Rambus Rambus XDRXDR


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SRAM Memory CycleSRAM Memory Cycle


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SRAM Memory CycleSRAM Memory Cycle


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Lab 4 Part 2Lab 4 Part 2

•• 3 modules3 modules–– SRAM interfaceSRAM interface–– ReaderReader–– WriterWriter

Documents

ECE 4401 Digital Design Laboratory Lecture 4 Bus Design ...chandy/courses/4401f08/4401ln04.pdf · •Control logic on all modules. ECE4401 Digital Design Laboratory September 18,