Lecture 11:

Spring 2018

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ECE 2300Digital Logic & Computer Organization

Timing Analysis

Lecture 11:Lecture 11: 2

Announcements

• Lab report guidelines are uploaded on CMS– As part of the assignment for Lab 3 report

• Lab 4(A) prelab due tomorrow

Lecture 11: 3

Synchronous Circuitscombinational

logic

CLOCK

• The changes in the state of the memory elements are synchronized by a clock signal– All flip-flops (FFs) are synchronized to capture the

inputs “simultaneously” on the clock tick

• Must ensure the output of the combinational logic has settled before the next clock tick

Lecture 11: 4

Review: Glitches in Synchronous Circuits XYS

S•YS’•X

F

S’

CLOCK

CLOCK

X

Y

S FS’•X

S•Y

Lecture 11:

tsetup thold

tffpd

tclk

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Stable FF Situation

stable stable

Flip-flop propagation delay (or clock-to-Q delay): the time it takes for the FF output to be stable after the clock edge

Lecture 11:

What if This Happens?

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D Q

CLK

D Q

CLK

combinational logic

IN Q1 D2

CLK1 CLK2

IN

Q1

CLK2

D2

CLK1

D2 input still transitioning

May capture neither HIGH nor LOW

Lecture 11: 7

Metastable State

tsetup thold

unstable

metastable

• Q stuck in the undefined region between 0 and 1

• Eventually moves to a stable state, but may take a while (metastable resolution time)

Lecture 11: 8

But What About This Situation?XYS

S•YS’•X

F

S’

CLOCKWrong value captured

CLOCK

X

Y

S FS’•X

S•Y

Lecture 11:

Avoiding Timing Failure• Possible causes of metastability and wrong

value capture– Clock pulse that is too narrow– Input changes too soon before a clock edge– Input changes too soon after a clock edge

• Avoid by meeting setup time, hold time, and minimum clock pulse width specifications

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Lecture 11:

Sequential Circuit Timing Analysis

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• Timing analysis involves calculating the time delays between all FF pairs within the circuit

• To determine the maximum operating frequency and ensure that setup time requirements are met– The clock cannot be too fast

• To ensure that hold time requirements are met– The minimum propagation delay of the combinational

logic (contamination delay) cannot be too small– Independent of clock frequency

Lecture 11: 11

Important Timing Parameterscombinational

logic

CLOCK

tsetup thold

tcomb

tffpd

tclk

Lecture 11:

Setup Time Constraint• tsetup is the minimum amount of time before

the triggering edge during which FF input must be stable

12tsetup thold

tcomb

tffpd

tclk

Lecture 11: 13

Determining Clock Cycle Time

• tffpd(max) + tcomb(max) + tsetup ≤ tclkEvery circuit path between every pair of FFs must satisfy the above equation to run the circuit at a frequency of 1/tclk

• The longest timing path (worst case) determines the maximum clock frequency– Worst case temperature and voltage – Worst case manufacturing variations

combinationallogic

CLOCK

FF1 FF2

Lecture 11: 14

Example: Setup Time Calculations

Prop Delay (ns) Setup Time (ns)

Hold Time (ns)

min max

FF 1 7 3 1

Comb 3 9 - -

• What’s the best achievable cycle time?

combinationallogic

CLOCK

FF1 FF2

Lecture 11: 15

Example: Setup Time Calculationscombinational

logic

CLOCK

FF1 FF2

Prop Delay (ns) Setup Time (ns)

Hold Time (ns)

min max

FF 1 7 3 1

Comb 3 9 - -

• tclk >= tffpd(max) + tcomb(max) + tsetup = 7 + 9 + 3 = 19ns

Lecture 11: 16

Hold Time Constraint

• thold is the minimum amount of time after the triggering edge during which FF input must remain stable– Otherwise, the receiving flip-flop may be contaminated with an

unexpected value

• Need to consider minimum propagation delays (contamination delays) for hold time calculations

tffpd(min) + tcomb(min) ≥ thold

combinationallogic

CLOCK

FF1 FF2

Lecture 11: 17

Example: Hold Time ConstraintIN Q1 Q2

CLOCK

very short wire (assume negligible delay)

tffpd(min) + tcomb(min) = tffpd(min)+0 ≥ thold

D2

IN

CLOCK

Hold time windows (thold) D2 must be held stable for FF2

Q2

D2

Q1

tffpdtffpd

FF2FF1

Lecture 11: 18

Example: Hold Time Calculationscombinational

logic

CLOCK

FF1 FF2

Prop Delay (ns) Setup Time (ns)

Hold Time (ns)

min max

FF 1 7 3 1

Comb 3 9 - -

• Hold time at FF2 met?

Lecture 11: 19

Clock Skew Complicates Matters Further

• Clock may not reach all flip-flops simultaneously

combinationallogic CLK2

CLK1[long wire]

CLK2

CLK1

tskew

CLOCK(assume nontrivial delay)

(delayed)

FF2FF1

tskew(max) : Maximum clock skew

tskew(min) : Minimum clock skew

Lecture 11: 20

Cycle Time With Clock SkewCombinational

logicIN

Q1 D2

[long wire]

CLK1

CLOCK

CLK2FF2FF1

tsetup

(delayed)

(delayed)

(delayed)

tskew

IN

Q1

CLK2

D2

CLK1

Lecture 11: 21

Negative Clock Skew

Sending FF receives clock later than receiving FF

tsetup

(delayed)

(delayed)

(delayed)

tskew

IN

Q1

CLK2

D2

CLK1

Harmful skew for meeting setup time constraint

Combinational logic

INQ1 D2

[long wire]

CLK1

CLOCK

CLK2FF2FF1

tffpd

tcomb

tffpd(max) + tcomb(max) + tsetup ≤ tclk – tskew(max)

Lecture 11: 22

Positive Clock Skew

Receiving FF receives clock later than sending FFtffpd(max) + tcomb(max) + tsetup ≤ tclk + tskew(min)

tsetup

(delayed)

tskew

IN

Q1

CLK2

D2

CLK1

Beneficial skew for meeting setup time constraint

Combinational logic

INQ1 D2

[long wire]

CLK1

CLOCK

CLK2FF2FF1

Lecture 11: 23

Hold Time With Positive Clock Skew

IN

Q1

CLK1

CLK2

thold

(delayed)

tskew

D2

Receiving FF receives clock later than sending FFtffpd(min) + tcomb(min) ≥ thold + tskew(max)

Harmful skew for meeting hold time constraint

(hold time window effectively widened)

Combinational logic

INQ1 D2

[long wire]

CLK1

CLOCK

CLK2FF2FF1

Lecture 11: 24

Hold Time With Negative Clock Skew

What if sending FF receives clock later than receiving FF?

D Q

CLK

D Q

CLK

Combinational logic

INQ1 D2

[long wire]

CLK1

CLOCK

CLK2

tffpd(min) + tcomb(min) ≥ thold - tskew(min)

Beneficial skew for meeting hold time constraint

Lecture 11: 25

combinationallogic

CLOCK

FF1 FF2

Clock may arrive at FF1 up to 1ns later than FF2

Example: Setup Analysis with Clock Skew

Prop Delay (ns) Setup Time (ns)

Hold Time (ns)min max

FF 1 7 3 1

Comb 3 9 - -

• What’s the best achievable cycle time?tffpd(max) + tcomb(max) + tsetup <= tclk - tskew(max)

tclk >= 7 + 9 + 3 + 1 = 20ns

Lecture 11:

Before Next Class • H&H 5.1-5.2.3, 5.5

Next Time

Binary Arithmetic

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