E3LIM E3 Line Interface Module NRZ Clock/Data Output ... converts HDB3-encoded line signals, in E3 asynchronous format, to and from NRZ data and clock signals. Sensitive analog circuitry

• Complete HDB3 analog to NRZ digital E3 (34368 kbit/s) line interface unit in a compact 2.6 square inch, 50-pin DIP module

• Single +5 V power supply

• Analog inputs and outputs are transformer coupled

• Meets ITU-T Rec. G.703 pulse mask requirements

• Equalizer and AGC provided for receiver input

• Input dynamic range of 17 dB (150 mV - 1.1 V)

• Meets E3 jitter requirements of ITU-T Rec. G.823

• Full loopback capability

• Coding violation and loss of signal detection for received signal

• Speeds time to market for prototype development

• Eases parts inventory and acquisition

• Eases field maintenance

The E3 Line Interface Module (E3LIM) is a completeand compact full duplex analog line to digital terminalinterface. It converts HDB3-encoded line signals, in E3asynchronous format, to and from NRZ data and clocksignals.

Sensitive analog circuitry meets E3 performancerequirements for signal recovery and transmission, withdirect line connection via on-board transformers. Inte-gration of functions into a single Module frees the userfrom complex printed circuit board design layouts andtesting for the E3 analog section, reducing the timerequired for applications development and productintroduction.

• E3 interface for quick “time to market” products

• Digital cross-connect equipment

• Remote terminals

• Terminal interface for multiplexers/demultiplexers

• Switching systems

• CSU/DSU

E3LIME3 Line Interface Module

NRZ Clock/Data OutputTXC-20163

Document Number: TXC-20163-MBEd. 1, June 1998

Copyright 1998 TranSwitch CorporationTranSwitch and TXC are registered trademarks of TranSwitch Corporation

E3LIMTXC-20163

E3 Line Interface Module

NRZ data andclock out

NRZ data andclock in

LINE SIDE TERMINAL SIDE

HDB3 analog input(from BNC connector)

HDB3 analog output(to BNC connector)

Status

Coding Violation

Control

External reference clock:34.368 MHz (E3)

DATA SHEET

APPLICATIONS

DESCRIPTIONFEATURES

TranSwitch Corporation • 3 Enterprise Drive • •••

Shelton, Connecticut 06484 USATel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com

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E3LIMTXC-20163

TABLE OF CONTENTS

SECTION PAGEProduct Overview ..................................................................................................3Block Diagram .......................................................................................................3Block Diagram Description ....................................................................................4Pin Diagram ..........................................................................................................5Pin Descriptions ....................................................................................................5Absolute Maximum Ratings and Environmental Limitations .................................9Power Requirements ............................................................................................9Input and Output Parameters ..............................................................................10Timing Characteristics ........................................................................................12Operation ...................................................................................................... 15-20

Receiver Input Requirements ......................................................................15Interfering Tone Tolerance ...........................................................................15Transmitter Specifications ............................................................................16AIS and Loopback Control Signal Arbitration ...............................................16Jitter Transfer ...............................................................................................17Jitter Generation ..........................................................................................17Jitter Tolerance ............................................................................................ 17Interference Margin Test ..............................................................................18Physical Design of Motherboard ..................................................................18Compatibility with other TranSwitch Devices ...............................................20

Circuit Diagram ...................................................................................................20Package Information ...........................................................................................22Ordering Information ...........................................................................................24Related Products ................................................................................................24Standards Documentation Sources ....................................................................25Documentation Update Registration Form * ..................................................29

* Please note that TranSwitch provides documentation for all of its products. Customers who are using aTranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department toreceive relevant updated and supplemental documentation as it is issued. They should also contact theApplications Engineering Department to ensure that they are provided with the latest available informationabout the product, especially before undertaking development of new designs incorporating the product.

LIST OF FIGURES

Figure 1. E3LIM TXC-20163 Block Diagram .....................................................3Figure 2. E3LIM TXC-20163 Pin Diagram ........................................................5Figure 3. Pulse Mask at the 34368 kbit/s Interface .........................................12Figure 4. NRZ Transmit Input Timing...............................................................13Figure 5. NRZ Receive Output Timing ............................................................14Figure 6. Coding Violation Pulse Timing .........................................................14Figure 7. E3LIM Input Jitter Tolerance at 34368 kbit/s ...................................17Figure 8. Interference Margin Test Configuration ...........................................18Figure 9. Power Supply and Ground Connections ..........................................19Figure 10. E3LIM TXC-20163 Circuit Diagram .................................................21Figure 11. E3LIM TXC-20163 Simplified Outline Drawing ................................22Figure 12. Installation Without Motherboard Socket .........................................23Figure 13. Installation With Motherboard Socket ..............................................23

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E3LIMTXC-20163

PRODUCT OVERVIEW

The E3LIM Module employs TranSwitch’s MRT Multi-rate Receive/Transmit VLSI device (TXC-02050) on asmall printed circuit board assembly with line-coupling transformers and dual-port terminal interface circuits.

The E3LIM is mechanically compatible with the DS3LIM and DS3LIM-SN Modules. It is designed so that anyof these three Modules may be used on a customer’s communications line interface board with the sameprinted wiring layout, by changing only the reference clock frequency (although the operation of the EQ0 andEQ1 input pins is different). The E3LIM interfaces directly to the TranSwitch E2/E3F VLSI device for operationat 34368 kbit/s with either G.751 or G.752 E3 formats. Use of the E3LIM Module in applications designsassures the achievement of the precise power line filtering, preferred grounding techniques, optimum compo-nent and conductor layout, and transformer coupling required for best performance of the TranSwitch MRTdevice.

BLOCK DIAGRAM

Figure 1. E3LIM TXC-20163 Block Diagram

MU

XReceive Line Receive Terminal

Interface Interface

XFMR EqualizationNetwork

ClockRecovery

DCK

RxD2

EQ0

+

-

Transmit Line Transmit Terminal Interface Interface

RxD1

DI1

DI2

EQ1

clk

AGC HDB3Decoder

CVError

Detector

HDB3Encoder

I/OCircuits

XFMRTPOTxD2

TxD1

TNO

TR

RT CV

OutputDriver

TxLOC

ReceiveTerminalInterface

Mux

RxAIS SLCT

RC1

RD1

RC2

RD2

TP/TD

TN

CLKI

TransmitTerminalInterface

Mux

TC1

TD1

TC2

TD2

RP/RD

RN

CLKO

CLKO

RXLOS

T21:1

T11:2

TXAIS34.368MHz

Receive

Transmit

Tx-Rx(Terminal)Loopback

MRT Device

Rx-Tx(Line)

Loopback

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E3LIMTXC-20163

BLOCK DIAGRAM DESCRIPTIONA block diagram for the E3LIM Module is shown in Figure 1, which is explained below.

In the receive direction, the E3LIM receives a bipolar HDB3-encoded E3 signal from the line via a BNC or otherconnector. The received HDB3 signals (RxD1, RxD2) are AC-coupled to the E3LIM through a 1:1 transformer(XFMR T2). From the transformer, the signal is terminated into a 75Ω load and presented to the DI1 input ofthe MRT’s Equalization network. This equalizer compensates for various lengths of cable having a √f charac-teristic. Two E3LIM pins (EQ0, EQ1) provide selection of four different equalizer settings. The equalizer outputdrives an Automatic Gain Control (AGC) circuit which provides a constant signal level to the Clock Recoveryblock.

The Clock Recovery block provides loss of signal (RXLOS) detection by monitoring the received bipolar signalfor transitions. It requires an external 34.368 MHz (E3) clock (DCK) with a stability of ± 200 ppm. The stabilityof DCK must be increased to ± 20 ppm if the transmit or receive AIS features are used. The average time torecover the clock is approximately one millisecond when the line signal is applied.

The HDB3 (high density bipolar with 3-zero substitution) line coded data is decoded by the HDB3 Decoderblock. Indications of coding violation errors, other than the normal HDB3 coding substitutions, are provided onthe signal pin CV. Bipolar coding errors can occur because of noise and other impairments on the line. Theapplication that uses the E3LIM can count the CV pulses over a known time interval to calculate a close esti-mate for the Bit Error Rate (BER) performance of the line.

The E3LIM provides the capability to generate and insert an E3 Alarm Indication Signal (AIS) into the NRZreceive data signal at the RD1 or RD2 pins. A low placed on the RXAIS pin enables the E3 AIS insertion froman internal E3 AIS Generator circuit (not shown). This pin may be connected to the receive loss of signal(RXLOS) output pin to generate AIS.

The decoded signal is processed by the Receive I/O Circuits and Receive Terminal Interface Multiplexerblocks. Two receive output ports consisting of a clock and data signal are provided. The first receive output porthas pins labelled RC1 and RD1; the second is labelled RC2 and RD2. Only one port can be active at a time.Data (RD1/RD2) is clocked out of the E3LIM with respect to the falling edge of the receive clock (RC1/RC2).The selection of the receive output port is controlled by the state of the select pin (SLCT, high for port 1). Theunused port is forced into a high impedance state.

In the transmit direction, two transmit ports consisting of clock and data are provided. The first transmit porthas pins labelled TC1 and TD1; the second is labelled TC2 and TD2. Transmit input data (TD1/TD2) is clockedinto the E3LIM on positive transitions of the clock signal (TC1/TC2). As in the receiver section, the SLCT pindetermines the transmit input port selection (high for port 1).

The transmit input clock and data signals are processed by the Transmit Terminal Interface Multiplexer andTransmit I/O Circuits blocks. The incoming data is encoded by the HDB3 encoder. In the HDB3 line code, eachblock of four consecutive zeros is removed and replaced by either of two codes that contain bipolar violations.These replacement codes are B00V and 000V, where B represents a pulse that conforms to the bipolar ruleand V represents a pulse violating the rule. The choice of these codes is made so that an odd number of bipo-lar conforming pulses (B) is transmitted between consecutive bipolar violation pulses (V). The encoded data isconnected to the Output Driver block, which contains the formatting circuitry to transform the HDB3-encodeddata into pulses that meet the requirements for the E3 line rates and a driver for the 2:1 output transformer(XFMR T1) that drives a 75Ω load. This block also provides the capability to transmit a E3 Alarm Indication Sig-nal (AIS), which is independent of the transmit data. A low placed on the TXAIS pin enables the transmit E3AIS insertion.

In addition to the alarms and control signals, the E3LIM provides two loopback capabilities for testing transmitand receive loopback. Transmit-to-Receive (terminal) loopback connects the data path from the output driverblock output to the clock recovery block input, and disables the external receiver input. Transmit-to-Receiveloopback is activated by placing a low on the TR signal pin. Receive-to-Transmit (line) loopback connects theClock Recovery Block data outputs to the transmit Output Driver Block and disables the NRZ transmit input.The Receive-to-Transmit Loopback bypasses the HDB3 Decoder and Encoder Blocks. Receive-to-Transmitloopback is activated by placing a low on the RT pin. Terminal and line loopbacks may not be applied togetherbecause invalid outputs would result.

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E3LIMTXC-20163

PIN DIAGRAM

Figure 2. E3LIM TXC-20163 Pin Diagram

PIN DESCRIPTIONS

Symbol Pin No. I/O/P * Type ** Name/Function

TxD1TxD2

1,2

O Analog Transmit E3 HDB3 Output: These pins are AC-cou-pled, HDB3-encoded E3 output signals. They may be applied directly to a 75Ω BNC connector. TxD2 should be connected to the center conductor when this module is connect directly to the line. Under normal operation, this output has a 75Ω source impedance.

TGND 3, 4, 5, 6, 7 P Transmit Ground: Ground pin for transmit side circuitry.

NC 8, 9, 10, 18, 19, 20, 25, 26, 38, 42,

43, 46

- No Connect: These pins are not to be connected and should be left floating.

+5VDCT 11, 12, 13 P Transmit +5VDC: +5 V, ±5 % DC power supply for trans-mit side circuitry.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

RxD

1

RxD

2

RG

ND

RG

ND

NC

RG

ND

RG

ND

NC

NC

+5V

DC

R

+5V

DC

R

+5V

DC

R

NC

SLC

T

RX

LOS

CV

RC

2

RC

1

TX

LOC

RX

AIS

TX

AIS

RD

1

RD

2

DC

K

TxD

1

TxD

2

TG

ND

TG

ND

TG

ND

TG

ND

TG

ND

NC

NC

NC

+5V

DC

T

+5V

DC

T

+5V

DC

T

EQ

0

EQ

1

RT

TR

NC

NC

NC

TC

1

TC

2

TD

1

TD

2

NC

NC

TRANSWITCH

TXC-02050

T1

C16

T2 R25

D1

L1

C18

C20

R20

C9

R19

C12

R24 C11

L4

R23 C13

U4C15

C21

C5

U2

U1

* Note: I=Input; O=Output; P=Power** Note: See the Input and Output Parameters section below for digital input and output Type definitions.

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E3LIMTXC-20163

EQ0EQ1

14,15

II

CMOSrCMOSr

Equalizer Bit 0: LSB of equalizer setting.Equalizer Bit 1: MSB of equalizer setting. Equalization is as follows:EQ1 EQ0 CABLE EQUALIZATION

1 1 0 dB<cable<3.5 dB1 0 2.6 dB<cable<8 dB0 0 6 dB<cable<9.9 dB0 1 8.6 dB<cable<13.2 dB

RT 16 I CMOSr Receive-To-Transmit Loopback: An active low enables the receive (line) loopback feature. This loop-back connects receive data and clock to the transmit data and clock path, and disables the NRZ transmit data and clock inputs. Receive data and clock are also sent to the Receive terminal outputs during loopback. (SeeNote 1.)

TR 17 I CMOSr Transmit-To-Receive Loopback: An active low enables the transmit (terminal) loopback feature. This loopback connects the transmit line output to the receive line input path, and disables the E3 receive line signal input. The transmit signal is also sent to the Transmit line outputs during loopback. (See Note 1.)

TC1 21 I TTLr Transmit Input Clock #1: When a high is placed on the SLCT lead, TC1 is the input pin for the NRZ transmit clock. This clock has a (50 ± 5) % duty cycle and a fre-quency of 34.368 MHz ± 20 ppm.

TC2 22 I TTLr Transmit Input Clock #2: When a low is placed on the SLCT lead, TC2 is the input pin for the NRZ transmit clock. This clock has a (50 ± 5) % duty cycle and a fre-quency of 34.368 MHz ± 20 ppm.

TD1 23 I TTL Transmit Input Data Port 1: Data is clocked in on posi-tive transitions of TC1. This port is enabled by placing a high on the SLCT lead.

TD2 24 I TTL Transmit Input Data Port 2: Data is clocked in on posi-tive transitions of TC2. This port is enabled by placing a low on the SLCT lead.

DCK 27 I TTL External Clock : An external 34.368 MHz clock having a stability of ± 200 ppm (± 20 ppm if the AIS feature is used), and a duty cycle of (50 ± 5) %. If the duty cycle is relaxed, the transmitted mask may not meet pulse mask requirements.

RD2 28 O TTL4mA Receive Output Data Port 2: Data is clocked out on negative transitions of RC2. This port is enabled by plac-ing a low on the SLCT lead. When this port is disabled,by placing a high on SLCT, the output goes to a high impedance state.


Note 1: An external 10kΩ pull-up resistor to +5 V is required to disable loopback. RT and TR should not both be set low atthe same time, since this will cause the MRT device on the E3LIM module to enter an invalid state.

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E3LIMTXC-20163

RD1 29 O TTL4mA Receive Output Data Port 1: Data is clocked out on negative transitions of RC1. This port is enabled by plac-ing a high on the SLCT lead. When this port is disabled,by placing a low on SLCT, the output goes to a high impedance state.

TXAIS 30 I CMOSr Transmit AIS: An active low placed on this pin disables the transmit data input, and causes an AIS (all ones sig-nal) to be generated and sent as transmitted data on the transmit line output. (See Note 1.)

RXAIS 31 I CMOSr Receive AIS: An active low placed on this pin disables the receive data input, and causes an AIS (all ones sig-nal) to be generated and sent on the RD1 or RD2 outputpins. (See Note 1.)

TXLOC 32 O TTL2mA Transmit Loss of Clock: Active low output. A transmit loss of clock alarm occurs when the transmit clock input (TC1 or TC2) is stuck high or low for 20-32 clock cycles. Recovery occurs on the first input clock transition.

RC1 33 O CMOS8mA Receive Output Clock Port 1: This port is enabled by placing a high on the SLCT lead. When this port is dis-abled by placing a low on SLCT, the output goes to a high impedance state.

RC2 34 O CMOS8mA Receive Output Clock Port 2: This port is enabled by placing a low on the SLCT lead. When this port is dis-abled by placing a high on SLCT, the output goes to a high impedance state.

CV 35 O TTL2mA Coding Violation: A positive pulse having a duration of one clock cycle is provided on this pin whenever an HDB3 coding violation is detected on the receive line data.

RXLOS 36 O TTL2mA Receive Loss of Signal: An active low alarm is generated when 20-32 consecutive zeros appear in the incoming data stream. It is cleared when the receive signal returns.


Note 1: An external 10kΩ pull-up resistor to +5 V is required to enable data and disable the AIS.

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E3LIMTXC-20163

SLCT 37 I CMOSr Select Port 1 or 2: The ports are enabled and disabled according to the following table:

+5VDCR 39, 40, 41 P Receive +5 VDC: +5 V, ±5 % DC power supply input for receive side circuitry.

RGND 44, 45, 47, 48 P Receive Ground: Ground pins for receive side circuitry.

RxD1RxD2

50,49

I Analog Receive E3 HDB3 Input: These pins are the AC-coupled HDB3-encoded E3 input signals. They may come directly from a 75 ohm BNC connector. RxD1 should be connected to the center conductor when this module is connected directly to the line.


Select High Low

RD1 Enabled High Z

RC1 Enabled High Z

TD1 Enabled Disabled

TC1 Enabled Disabled

RD2 High Z Enabled

RC2 High Z Enabled

TD2 Disabled Enabled

TC2 Disabled Enabled

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E3LIMTXC-20163

ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS

Notes:1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min

or Max values for extended periods may impair device reliability.2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the

"CAUTION" label on the drypack bag in which the modules are supplied.

POWER REQUIREMENTS

Parameter Symbol Min Max Unit Conditions

+5 V supply voltages VDD +7.0 V Note 1

DC input voltage VIN -0.5 VDD + 0.5 V Note 1

Storage temperature range TS -55 150 oC Note 1

Ambient operating temperature TA 0 70 oC 0 ft/min linear airflow

Moisture Exposure Level ME 5 Level per EIA/JEDECJESD22-A112-A

Relative Humidity, in-circuit RH 0 100 % Non-condensing.Note 2

Parameter Min Typ Max Unit Test Conditions

VDD 4.75 5.0 5.25 V

IDD 150 mA VDD = 5.25 V

PDD 0.79 W VDD = 5.25 V

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E3LIMTXC-20163

INPUT AND OUTPUT PARAMETERS

Input Parameters For CMOSr

Note: Input has a 100kΩ (nominal) internal pull-up resistor.

Input Parameters For TTL

Input Parameters For TTLr

Note: Input has a 100kΩ (nominal) internal pull-up resistor.

Output Parameters For CMOS8mA


VIH 2.0 V 4.75 <VDD < 5.25

VIL 0.8 V 4.75 <VDD < 5.25

Input leakage current 50 120 µA VDD = 5.25

Input capacitance 5.5 pF


VIH 2.0 V 4.75 <VDD < 5.25

VIL 0.8 V 4.75 <VDD < 5.25

Input leakage current 10 µA VDD = 5.25



VIH 2.0 V 4.75 <VDD < 5.25

VIL 0.8 V 4.75 <VDD < 5.25

Input leakage current 50 120 µA VDD = 5.25



VOH VDD - 0.5 V VDD = 4.75; IOH = -8.0 mA

VOL 0.4 V VDD = 4.75; IOL = 8.0 mA

IOL 8.0 mA

IOH -8.0 mA

tRISE 1.3 2.4 3.8 ns CLOAD = 25 pF

tFALL 1.1 1.8 2.5 ns CLOAD = 25 pF

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E3LIMTXC-20163

Output Parameters For TTL2mA

Output Parameters For TTL4mA

Receiver Sensitivity

Input Parameters For Transformer Coupling

Output Parameters For Transformer Coupling

* Line side: Module side** Line side


VOH 2.4 V VDD = 4.75; IOH = -1.0 mA

VOL 0.4 V VDD = 4.75; IOL = 2.0 mA

IOL 2.0 mA

IOH -1.0 mA

tRISE 5.5 12.5 18.2 ns CLOAD = 15pF

tFALL 2.3 4.4 6.5 ns CLOAD = 15pF


VOH 2.4 V VDD = 4.75; IOH = -2.0 mA

VOL 0.4 V VDD = 4.75; IOL = 4.0 mA

IOL 4.0 mA

IOH -2.0 mA

tRISE 2.8 6.5 9.2 ns CLOAD = 15 pF

tFALL 1.3 2.3 3.4 ns CLOAD = 15 pF


Dynamic Range 150 1100 mVp


Return Loss 26 dB

Isolation Voltage 300 Vrms

Turns Ratio 1:1

Input Impedance 67.5 75 82.5 ohms


Isolation Voltage 300 Vrms

Turns Ratio * 1:2

Output Impedance ** 67.5 75 82.5 ohms

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E3LIMTXC-20163

TIMING CHARACTERISTICS

Detailed timing diagrams for the E3LIM are illustrated in Figures 3 through 6. All output times are measuredwith the load capacitance indicated for the pin type. Timing parameters are measured at (VOH + VOL)/2 (i.e.,the 50 % amplitude point) for outputs and at 1.4V for inputs, unless otherwise specified.

Line Side Timing Characteristics

The line side signal characteristics are designed so that the output meets the requirements of ITU-T recom-mendation G.703. When terminated into a test load of 75Ω ± 5 % using ATT 734A coaxial cable the E3LIMModule will meet the E3 interface isolated pulse mask defined below in Figure 3. The pulse mask is measuredat the output port of the module.

Figure 3. Pulse Mask at the 34368 kbit/s Interface

17 ns

(14.55 + 2.45)V

1.0

0.5

0

8.65 ns

(14.55 - 5.90)

14.55 ns

12.1 ns

(14.55 - 2.45)

24.5 ns

(14.55 + 9.95)

29.1 ns

(14.55 + 14.55)

Nominal pulse

0.1

0.1

0.1

0.1

0.1

0.1

Reference: ITU-T Recommendation G.703

0.2

0.2

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E3LIMTXC-20163

Terminal Side Timing Characteristics

Figure 4. NRZ Transmit Input Timing

Note: TC1, TC2 symmetry is measured about the 1.4 VDC threshold in order to assure symmetric output waveforms.

Parameter Symbol Min Typ Max Unit

TC1, TC2 E3 input clock period tCYC 29.09 ns

TC1, TC2 duty cycle (tPWH/tCYC) -- 45 55 %

TD1, TD2 set-up time to TC1↑, TC2↑ tSU 4.0 ns

TD1, TD2 hold time after TC1↑, TC2↑ tH 3.0 ns

DATAVALID

DATAVALID

DATAVALID

TC1,TC2

TD1,TD2

tSU

tPWH

tH

tCYC

(Input)

(Input)

1.4 V

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E3LIMTXC-20163

Figure 5. NRZ Receive Output Timing

Note: RC1, RC2 symmetry is measured about the 50 % amplitude point.

Figure 6. Coding Violation Pulse Timing

*Note: UI = 1 / (System Clock Frequency) = 29.097 ns

Parameter Symbol Min Typ Max Unit

RC1, RC2 E3 output clock period tCYC 29.09 ns

RC1, RC2 duty cycle (tPWH/tCYC) -- 45 55 %

RD1, RD2 output delay after RC1↓, RC2↓ tOD(1) -5.5 5.5 ns

CV output delay after RC1↓, RC2↓ tOD(2) -5.0 5.0 ns

Parameter Symbol Min Typ Max Unit*

CV pulse width (measured at 1.4 V) tPW 0.8 1.0 1.2 UI

CV delay from occurrence of violation tD 3.0 UI

RC1,RC2

RD1,RD2

CV

tPWH

tCYC

tOD(1)

tOD(2)

(Output)

(Output)

(Output)

tPWCV(Output)

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E3LIMTXC-20163

OPERATION

Receiver Input Requirements

*Note: Refer to the Operation-Jitter Tolerance subsection below.

Interfering Tone Tolerance

The E3LIM will properly recover clock and present error-free output to the receive terminal side interface* inthe presence of a PRBS interfering tone signal at the following line rates:

Interfering Tone Tolerance

*Note: See Figure 8 below, “Interference Margin Test Configuration”.

Parameter Value

Interface Cable AT&T 728A/734A coaxial (or equivalent)

Bit Rate:

E3 34.368 Mbit/s ± 20 ppm

Line Code HDB3

Input Signal Amplitude: 150 mVp - 1.1 Vp AC

Cable Loss 0 - 12 dB (with suitable settings of EQ0 and EQ1 pins)

Input Return Loss:

E3 > 12 dB at 860 kHz to 1.72 MHz> 18 dB at 1.72 MHz to 34.368 MHz> 14 dB at 34.368 MHz to 51.550 MHz

Signal-to-Noise Toler-ance

No greater than either the value produced by adjacent pulses in the data stream or ±10 % of the peak pulse amplitude, whichever is greater.

Input Jitter Tolerance As defined by Figure 7: “E3LIM Input Jitter Tolerance at 34368 kbit/s”*

Data Rate (Mbit/s) Tone Rate (Mbit/s) Maximum Tone Level

34.368 34.368 -20 dB

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E3LIMTXC-20163

Transmitter Specifications

*Note: UI = 1 / (System Clock Frequency) = 29.097 ns

AIS and Loopback Control Signal Arbitration

The response of the Module to combinations of the RXAIS, TXAIS, RT and TR input signals is tabulatedbelow:

Note: X = Don’t Care

Parameter Value

TxD1, TxD2 Output Characteristics:

The pulse shape shown in Figure 3 and specified below is to be measured at the output of the E3LIM Module, terminated by a 75Ω ±5 % resistor.

Pulse Shape (E3) As defined by Figure 17 in ITU-T Recommendation G.703

Amplitude 1.0 Volt(p) ±10 %

Output jitter 0.05 UI* maximum over a frequency range of 100 Hz to 800 kHz with jitter-free transmit input clock (TC1 or TC2)

RXAIS TXAIS RT (line) TR (term.) Terminal Output Line Output

1 1 1 1 Normal Normal

1 1 1 0 Terminal Loopback Normal

1 X 0 1 Normal Line Loopback

1 0 1 1 Normal AIS

1 0 1 0 Terminal Loopback AIS

0 1 1 X AIS Normal

0 X 0 1 AIS Line Loopback

0 0 1 X AIS AIS

X X 0 0 Invalid State Invalid State

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E3LIMTXC-20163

Jitter Transfer

Transfer of jitter through an individual unit of digital equipment is characterized by the relationship between theapplied input jitter and the resulting output jitter as a function of frequency.

For E3, ITU-T Recommendation G.823 further describes and defines jitter transfer.

In a looped back configuration (through the receive path and externally looped back through the transmit path),in the absence of applied input jitter the maximum amount of jitter introduced by the E3LIM is 0.18 Unit Inter-vals (UIs, where UI is 1 / System Clock Frequency, or 29.097 ns) of peak-to-peak jitter.

With applied input jitter, the maximum output jitter is the applied input jitter plus the above jitter introduced bythe E3LIM.

Jitter Generation

Jitter generation is the process whereby jitter appears at the output port of an individual unit of digital equip-ment in the absence of applied input jitter.

In the absence of applied input jitter, the transmit path of the E3LIM introduces a maximum of 0.05 UIs of peak-to-peak jitter over the frequency range from 100 Hz to 800 kHz.

Jitter Tolerance

ITU-T Recommendation G.823 specifies that network equipment must be able to accommodate and toleratelevels of jitter up to certain specified limits. The E3LIM accommodates and tolerates more input jitter than thelevel of input jitter specified by the ITU-T Recommendation.

With input jitter applied to the line side receive input, the E3LIM properly recovers clock, decodes the HDB3,and outputs error-free NRZ data over (and beyond) the ITU-T specified jitter input and frequency ranges. Per-formance characteristics are shown below in Figure 7.

Figure 7. E3LIM Input Jitter Tolerance at 34368 kbit/s

10.0

0.1

10 Hz 100 Hz 1 kHz 100 kHzLog Scale

30kHz

Measured

Minimum Requirement

Log Scale

AcceptanceRange

1 MHz10 kHz

1.0

ITU-T Rec. G.823 Limit

Sin

usoi

dal

Inpu

tJitt

erA

mpl

itude

Frequency

UI(

Pea

k-P

eak)

Note: UI = 29.097 ns. VDD = 5.0 V, TA = 25oC.

1.5

0.15

- 18 - TXC-20163-MBEd. 1, June 1998

E3LIMTXC-20163

Interference Margin Test

Figure 8. Interference Margin Test Configuration

Physical Design of Motherboard

High-frequency design techniques must be employed for layout of the printed circuit board on which the E3LIMModule is mounted. The following guidelines and suggestions should be adhered to for a successful boarddesign. At the E3 frequency it is important to use high-frequency layout techniques. The techniques discussedbelow are the bare minimum set that should be used.

A 'solid' ground plane should be used for designs at this frequency.

‘Solid’ in this instance means that the impedance from any point in the plane to the board ground connection should be low. This is very important in regards to the location of the analog E3LIM device since its SNR can be severely degraded by I*R drops in these planes. If a solid, low impedance plane is not feasible, then the grounds should be divided into the following regions as shown in Figure 9.

1. E3LIM Receiver ground, RGROUND2. E3LIM Transmitter ground, TGROUND3. Board Logic ground

These ground regions should be connected in a star pattern. In other words, each region should have a separate path to a common connection point. The connection point should be as close as possible to the point where ground comes onto the board. Under no circumstances should a ground region be connected to the common point through a trace. The trace has a finite impedance at high frequencies; it is not a short. Ground currents through the trace impedance will cause voltage noise. Use as wide a path to the connection point as is possible.

Do not use a solid power plane. Break the +5 V power plane into regions corresponding to the ground regions and make connections to the E3LIM Module as shown in Figure 9. The power regions should be mirror images of the ground regions to minimize capacitive noise coupling. If the power and ground planes are placed in adjacent layers there will be an additional noise reduction due to capacitive coupling. For example, a six-layer board could be signal-signal-power(ground)-ground(power)-signal-signal. The passive components should be connected to the indicated ground planes. Connecting the components to the wrong plane will inject a noise signal into that part of the transceiver. Do not use a long trace to connect the components to ground for either a solid or regionalized ground plane; use as short a trace as possible. The decoupling capacitors should be placed as close as feasible to their associated chip pins on the same board side as the Module. Placing the capacitors on the other side of the board will have a measurable impact on device performance. Again, it should be pointed out that a board trace is an impedance, not a short.

PRBS Generator

Digital Transmission

E3LIMRX In

TX OutLine Out

Line InTest Set

E3

Passive

RX Out

TX In

ATTN#2

ATTN#1

34.368 Mb/sCombiner

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E3LIMTXC-20163

Figure 9. Power Supply and Ground Connections

For the input and output signal connections of the E3LIM Module a board trace at high frequencies is not azero-impedance metal interconnection. It is a distributed L/C network. The values of the L and C parasitic com-ponents are determined by trace geometry (width and height) and the surrounding material. Component layoutshould be arranged to permit the use of short traces, especially for the analog inputs. These input tracesshould be restricted to one side of the motherboard, since vias have been found to cause degraded perfor-mance due to output signal coupling. A trace with a given geometry will have a different impedance if it is on anoutside board layer from the same trace placed instead in an internal layer. Large branches off a main tracewill change the impedance at the branch point due to the effect of impedances in parallel, so branch lengthsshould be kept to a minimum (less than a quarter wavelength). This is very important for clock lines whereload/source impedance mismatches can cause severe ringing, which leads to timing problems. Use clock buff-ers to reduce the difficulty of distributing a clock with many loads.

If relays are used to switch the transceivers in and out, use the 50 ohm shielded variety to minimize crosstalk,especially from the power used to energize the relay. Match the impedance of the board traces of the transmit-ter outputs and receiver inputs to the transmission line impedance (75 ohms if a 1:1 transformer is used) tominimize reflections, and do not use vias in these signal paths. Physically separate the analog signal linesfrom the digital lines. Route the differential receiver lines side by side to make coupled noise common-mode.Avoid ninety-degree corners in the board lands; keep lands as straight and short as possible. Use terminating(i.e., 51 ohm series-damping) resistors in the digital signals lines where appropriate (i.e., if the line is longerthan a quarter wavelength of the highest signal frequency of importance, reflections will start causing prob-lems).

The above comments are guidelines only. High-frequency board layout is difficult and must be done with care.A bad board layout will reduce the SNR of the transceiver and cause timing problems with the board logic, per-haps to the point of requiring a complete board redesign.

123456789

10111213141516171819202122232425

50494847464544434241403938373635343332313029282726

TGROUND

0.1µF10µF +

+5VDCT

TxD1TxD2TGNDTGNDTGNDTGNDTGNDNCNCNC+5VDCT+5VDCT+5VDCTEQ0EQ1RTTRNCNCNCTC1TC2TD1TD2NC

RxD1RxD2

RGNDRGND

NCRGNDRGND

NCNC

+5VDCR+5VDCR+5VDCR

NCSLCT

RXLOSCV

RC2RC1

TXLOCRXAISTXAIS

RD1RD2DCK

NC

RGROUND

0.1µF 10µF+

+5VDCR

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E3LIMTXC-20163

Compatibility with other TranSwitch Devices

The E3LIM was designed to be pin compatible with the DS3LIM and DS3LIM-SN Modules. The E3LIM pro-vides many of the same controls and functions as the DS3LIM and DS3LIM-SN Modules. Due to the matchingassignment of module pins a board may be designed which could be assembled with the E3LIM or one of theDS3LIMs using the same printed wiring footprint.

CIRCUIT DIAGRAM

The circuit diagram for the E3LIM Module is provided in Figure 10.

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TX

C-20163-M

BE

d.1,June 1998

E3LIM

TX

C-20163

Figure 10.

Figure 10. E3LIM TXC-20163 Circuit Diagram

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E3LIMTXC-20163

PACKAGE INFORMATION

The E3 Line Interface Module consists of a 2.6 x 1.0 inch multi-layer printed circuit board with surface mountedcomponents on both sides and 50 signal/power pins at 0.1 inch spacing on the two long edges to provide aDIP configuration. Figure 11 is a simplified drawing that shows three views of the Module. All dimensions are ininches and are nominal unless otherwise indicated.

Figure 11. E3LIM TXC-20163 Simplified Outline Drawing

TOP

VIE

W

2.600 ± .005

0.900 ± .0201.000 ± .005

0.120 MAX

0.062 ± .005

0.10 TYP ± .010

0.30

0.210

Notes:1. Module is shown approximately twice full size.2. All dimensions are in inches, and are nominal unless otherwise indicated.3. R2, R5, R6, R14 and R28 are not installed.4. The axis of each pin is located within 0.010 inch vertically and 0.005 inch horizontally from its nominal position.

MAX

TRANSWITCH

TXC-02050

T1

C16

T2 R25

D1

L1

C18

C20

R20

C9

R19

C12

R24 C11

L4

R23 C13

U4C15

C21

C5

U2

U1

(see Note 4)

L3 C10

C17

R27

C19 C2

R14

R13 R4

R1

R6

R5

C3R11

R12

R9

R8

C4

R7

C14

C6

R15 R

3

R10

C1

1

1

0.30

R2

R28

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E3LIMTXC-20163

The E3LIM can be installed without or with a socket on the motherboard, as shown in Figures 12 and 13,respectively. All dimensions are shown in inches and are nominal unless otherwise indicated.

Figure 12. Installation Without Motherboard Socket

Figure 13. Installation With Motherboard Socket

Notes for Figures 12 and 13:1. All dimensions are in inches and are nominal unless otherwise indicated.2. Drawings not to scale.3. SAMTEC, Inc. P.O. Box 1147 New Albany, Indiana 47151-1147 USA Phone: 812-944-6733 Fax: 812-948-5047 TWX: 810-540-4095 Telex: 333-918

Module PC Board

XFMRModule

0.250

Motherboard PC Board

L or CModule

0.120 MAX0.070

0.125

0.108

Connector (one pin of 25-pin strip)SAMTEC, Inc. #BBL-125-T-E, see Note 3

0.060

0.060 Pin 0.018 DIA

orFilter

Module PC Board

XFMRModule

Motherboard PC Board

Indctr.Module

0.120 MAX

0.0830.165

SAMTEC Module Connector #BBL-125-T-E mates with SAMTEC Micro-socket #SL-125-TT-19 or SL-125-TT-39 (LIF)

0.153

#BBL-125-T-E (one pin of 25-pin strip)

Socket on Motherboard (one of 25-socket strip)SAMTEC. Inc. #SL-125-TT-19 or SL-125-TT-39 (LIF), see Note 3

0.2500.060

0.060Hollow leg 0.029 DIA

0.070

Flanges 0.07 DIA

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E3LIMTXC-20163

ORDERING INFORMATION

Part Number: TXC-20163-DCMM E3 Line Interface ModuleNRZ Clock/Data Output50-Pin Dual In-Line Package

RELATED PRODUCTS

TXC-02050, MRT Multi-Rate Line Interface VLSI Device. The MRT provides the functions for terminating ITU-specified 8448 kbit/s (E2) and 34368 kbit/s (E3) line rate signals, or 6312 kbit/s (JT2) line signals specified in the Japanese NTT Technical Reference for High Speed Digital Leased Circuits. An optional HDB3 codec is provided for the two ITU line rates.

TXC-20049D, DS3LIM Module (DS3 Line Interface Module). A complete analog to digital converter which receives and transmits B3ZS-encoded DS3 line signals and provides serial NRZ clock and data interfaces on the terminal side.

TXC-21049, DS3LIM Evaluation Board. A complete, ready-to-use test bed for the test and evaluation of the DSLIM-SN and DS3LIM Line Interface Modules. The module plugs into a socket on the evaluation board, input and output signals are terminated via BNC connectors, and all functions of the module are selectable via jumper insertion/extraction on the evaluation board.

TXC-20153D and TXC-20153G, DS3/STS-1 Line Interface Module (DS3LIM-SN). Complete and compact analog-to-digital interface that converts B3ZS-encoded DS3 or STS-1 line signals to and from NRZ data and clock signals. Packaged as 2.6 inch x 1.0 inch 50-pin DIP.

TXC-03701, E2/E3F VLSI Device (E2/E3 Framer). Maps broadband payloads into the E3 frame format.

TXC-06125, XBERT VLSI Device (Bit Error Rate Generator Receiver). Programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability.

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E3LIMTXC-20163

STANDARDS DOCUMENTATION SOURCES

Telecommunication technical standards and reference documentation may be obtained from the following organizations:

ANSI (U.S.A.):

American National Standards Institute (ANSI)11 West 42nd StreetNew York, New York 10036

Tel: 212-642-4900Fax: 212-302-1286

The ATM Forum (U.S.A.):

ATM Forum World Headquarters ATM Forum European Office303 Vintage Park Drive 14 Place Marie - Jeanne BassotFoster City, CA 94404-1138 Levallois Perret Cedex

92593 Paris France

Tel: 415-578-6860 Tel: 33 1 46 39 56 26Fax: 415-525-0182 Fax: 33 1 46 39 56 99

Bellcore (U.S.A.):

BellcoreAttention - Customer Service8 Corporate PlacePiscataway, NJ 08854

Tel: 800-521-CORE (In U.S.A.)Tel: 908-699-5800Fax: 908-336-2559

EIA - Electronic Industries Association (U.S.A.):

Global Engineering DocumentsSuite 4077730 Carondelet AvenueClayton, MO 63105

Tel: 800-854-7179 (In U.S.A.)Fax: 314-726-6418

ETSI (Europe):

European Telecommunications Standards InstituteETSI, 06921 Sophia - AntipolisCedex France

Tel: 33 92 94 42 00Fax: 33 93 65 47 16

ITU-T (International):

Publication Services of International Telecommunication Union (ITU)Telecommunication Standardization Sector (T)Place des NationsCH 1211Geneve 20, Switzerland

Tel: 41-22-730-5285Fax: 41-22-730-5991

- 26 - TXC-20163-MBEd. 1, June 1998

E3LIMTXC-20163

MIL-STD Military Standard (U.S.A.):

Standardization Documents Order Desk700 Robbins AvenueBuilding 4DPhiladelphia, PA 19111-5094

Tel: 212-697-1187Fax: 215-697-2978

TTC (Japan):

TTC Standard Publishing Group of theTelecommunications Technology Committee2nd Floor, Hamamatsucho - Suzuki Building,1 2-11, Hamamatsu-cho, Minato-ku, Tokyo

Tel: 81-3-3432-1551Fax: 81-3-3432-1553

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E3LIMTXC-20163

- NOTES -

TranSwitch reserves the right to make changes to the product(s) orcircuit(s) described herein without notice. No liability is assumed as aresult of their use or application. TranSwitch assumes no liability forTranSwitch applications assistance, customer product design, soft-ware performance, or infringement of patents or services describedherein. Nor does TranSwitch warrant or represent that any license,either express or implied, is granted under any patent right, copyright,mask work right, or other intellectual property right of TranSwitch cov-ering or relating to any combination, machine, or process in whichsuch semiconductor products or services might be or are used.

- 28 -

Engines for Global Connectivity

TranSwitch Corporation • 3 Enterprise Drive • •• •Shelton, CT 06484 USA www.transwitch.comTel: 203-929-8810 Fax: 203-926-9453

- 29 - TXC-20163-MBEd. 1, June 1998

E3LIMTXC-20163

DOCUMENTATION UPDATE REGISTRATION FORM

If you would like be added to our database of customers who have registered to receive updated documentationfor this device as it becomes available, please provide your name and address below, and fax or mail this pageto Mary Lombardo at TranSwitch. Mary will ensure that relevant Product Information Sheets, Data Sheets,Application Notes, Technical Bulletins and other relevant publications are sent to you. This information will bemade available in paper document form, on a Windows/DOS/Macintosh/UNIX CD-ROM disk, and on theInternet World Wide Web at the TranSwitch site, http://www.transwitch.com.

Please print or type the information requested below, or attach a business card.

Name: ________________________________________________________________________

Title: _________________________________________________________________________

Company: _____________________________________________________________________

Dept./Mailstop: ________________________________________________________________

Street: _______________________________________________________________________

City/State/Zip: _________________________________________________________________

If located outside U.S.A., please add - Postal Code: ___________ Country: ______________

Telephone:______________________________________________ Ext.: _________________

Fax: __________________________________ E-Mail: _______________________________

Purchasing Dept. Location: _______________________________________________________

Check a box if your computer has a CD-ROM drive: DOS Windows Mac UNIX ↓

Check box if you have Internet Web access: Sun Solaris HP Other

Please describe briefly your intended application for this device, and indicate whether you wouldcare to have a TranSwitch applications engineer contact you to provide assistance:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

If you are also interested in receiving updated documentation for other TranSwitch device types,please list them below rather than submitting separate registration forms:

__________ __________ __________ __________ __________ __________

Please fax this page to Mary Lombardo at (203) 926-9453 or fold, tape and mail it (see other side)

(Fold back on this line first.)

(Fold back on this line second, then tape closed, stamp and mail.)

FirstClass

PostageRequired

TranSwitch Cor porationAttention: Mar y Lombardo3 Enter prise DriveShelton, CT 06484U.S.A.

Please complete the registration form on this back cover sheet, and fax or mail it, if youwish to receive updated documentation on this TranSwitch product as it becomes avail-able.

TranSwitch Corporation • 3 Enterprise Drive • •• •Shelton, CT 06484 USA www.transwitch.comTel: 203-929-8810 Fax: 203-926-9453

Engines for Global Connectivity