DUSD(Labs)

EE249 Project:EE249 Project:Partitioning Algorithms & Partitioning Algorithms & Modeling Methodologies Modeling Methodologies for HW/SW Partitioning for HW/SW Partitioning in Metropolisin Metropolis

Mentor:Mentor:

John Moondanos,John Moondanos,

GSRC Visiting Fellow, UC BerkeleyGSRC Visiting Fellow, UC Berkeley

&&

Strategic CAD Labs Intel Corp.Strategic CAD Labs Intel Corp.

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Problem StatementProblem Statement

HW/SW partitioning deals with assigning parts of a system HW/SW partitioning deals with assigning parts of a system

description to heterogeneous implementation unitsdescription to heterogeneous implementation units Key task in system level design due to the downstream cost & performance Key task in system level design due to the downstream cost & performance

consequences of the initial partitioning choicesconsequences of the initial partitioning choices

Multi-faceted Multi-faceted Processor & flash on the same die or not?Processor & flash on the same die or not?

Functionality Partitioning into chipsFunctionality Partitioning into chips

Hardware vs. Software functionality ImplementationHardware vs. Software functionality Implementation

Which functions to which type of silicon?Which functions to which type of silicon?

Difficult to model & analyze with conventional RTL ToolsDifficult to model & analyze with conventional RTL Tools

Of course, the focus is on how it affects power consumptionOf course, the focus is on how it affects power consumption

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Goal of the ProjectGoal of the Project

Briefly Review the literature to capture the state of the artBriefly Review the literature to capture the state of the art

Develop technologies and methodologies for solving the Develop technologies and methodologies for solving the

partitioning problem within the Metropolis environmentpartitioning problem within the Metropolis environmentMethodologies will focus more on the system modeling Methodologies will focus more on the system modeling

methodology that is better suited for the capabilities of Metropolismethodology that is better suited for the capabilities of Metropolis

Technologies will focus more on the algorithms that must be used Technologies will focus more on the algorithms that must be used to accomplish the partitioning using the capabilities of the to accomplish the partitioning using the capabilities of the Metropolis environment.Metropolis environment.

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Suggestion for Design Driver for this ProjectSuggestion for Design Driver for this Project

For the hardware: The PXA800F cell phone processor from For the hardware: The PXA800F cell phone processor from

IntelIntelSome publicly available introductory material on the PXA800F is Some publicly available introductory material on the PXA800F is

available in the “backup material section”available in the “backup material section”

Modeling of the Xscale can happen with the GnuPro simulatorModeling of the Xscale can happen with the GnuPro simulator

For the Software: We have available Statistical Models for For the Software: We have available Statistical Models for

typical applications that run on the PXA800Ftypical applications that run on the PXA800F

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Backup MaterialBackup Material

Overview of the PXA800F cellular phone ProcessorOverview of the PXA800F cellular phone Processor

ReferencesReferences

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The Intel® PXA800F Cellular ProcessorThe Intel® PXA800F Cellular Processor

Full GSM/GPRS Class solutionFull GSM/GPRS Class solution

High-performance/Low-power Intel® XScale High-performance/Low-power Intel® XScale ™™

technology core, providing class-leading technology core, providing class-leading

headroom for rich data applicationsheadroom for rich data applications

Intel® Micro Signal ArchitectureIntel® Micro Signal Architecture

Intel® On-Chip Flash MemoryIntel® On-Chip Flash Memory GSM/GPRS Communications Stack, RTOS and GSM/GPRS Communications Stack, RTOS and

applications code for a single-chip mobile solutionapplications code for a single-chip mobile solution

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The Intel® XScale The Intel® XScale ™™ in the PXA800F in the PXA800F

High-performance, power-efficient processor supports data-intensive applicationsHigh-performance, power-efficient processor supports data-intensive applications

Processor core operates at an adjustable clock frequency from 104 to 312 MHz Processor core operates at an adjustable clock frequency from 104 to 312 MHz

Instruction cache and Data cache memories Instruction cache and Data cache memories

4 MB integrated Intel On-Chip Flash memory 4 MB integrated Intel On-Chip Flash memory

512 KB integrated SRAM 512 KB integrated SRAM

Memory controller supports synchronous Flash mode, page mode Flash, SRAM, Memory controller supports synchronous Flash mode, page mode Flash, SRAM,

DRAM, and variable latency DRAM, and variable latency

DMA controller DMA controller

Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC

Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP, Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP,

Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick, Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick,

Dallas* 1-Wire* Interface, keypad, PWM D/A, JTAGDallas* 1-Wire* Interface, keypad, PWM D/A, JTAG

Interfaces for Bluetooth, IrDA, GPS and digital camera peripheralsInterfaces for Bluetooth, IrDA, GPS and digital camera peripherals

LCD Controller for up to 120 x 240 display 16-bit color or gray scaleLCD Controller for up to 120 x 240 display 16-bit color or gray scale

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Intel Micro Signal Architecture in the PXA800FIntel Micro Signal Architecture in the PXA800F

Performs GSM/GPRS baseband signal processing Performs GSM/GPRS baseband signal processing

Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz

execution clock execution clock

Instruction cache and 64 KB dual-banked data SRAM Instruction cache and 64 KB dual-banked data SRAM

512 KB integrated Intel On-Chip Flash for field-upgradable signal 512 KB integrated Intel On-Chip Flash for field-upgradable signal

processing firmwareprocessing firmware

Includes microprocessor instructions such as bit manipulation Includes microprocessor instructions such as bit manipulation

Includes cipher and Viterbi accelerators Includes cipher and Viterbi accelerators

Multiple sleep modes and integrated power management minimize power Multiple sleep modes and integrated power management minimize power

consumption consumption

Interface support-digital I/Q, voice codec, auxiliary serial port for mixed-Interface support-digital I/Q, voice codec, auxiliary serial port for mixed-

signal analog baseband, I2S audio codec interface, RF synthesizer serial signal analog baseband, I2S audio codec interface, RF synthesizer serial

control interface, JTAGcontrol interface, JTAG

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The Memory SubsystemThe Memory Subsystem

The The Intel® XScale Intel® XScale ™™ Instruction and Data CacheInstruction and Data Cache

4MB of Flash & 512KB of SRAM always at 104MHz4MB of Flash & 512KB of SRAM always at 104MHz

Memory Controller managing accesses to external SRAMMemory Controller managing accesses to external SRAM

The MSAThe MSA Integrated 64KB SRAM for microcontroller like instructionsIntegrated 64KB SRAM for microcontroller like instructions

• Special instructions for maximizing GSM/GPRS performanceSpecial instructions for maximizing GSM/GPRS performance

512KB of flash for program store512KB of flash for program store

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PXA800F Block DiagramPXA800F Block DiagramUARTs for Bluetooth, IRDA

GSM Sim card I/F

External Power Management I/F

Synch Serial Port

Smart Battery I/F

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PXA800F Block DiagramPXA800F Block DiagramMemory Stick

Programmable Clock

Secure Card I/F

Pulse Width Modulator for buzzer

Timing Control UnitFor basestation timing

Encrypt/DecryptGSM data offloading MSA

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PXA800F Block DiagramPXA800F Block Diagram

Viterbi error decoding offloading MSA

High Speed Logger For debug

Full Bandwidth (Hi-Fi) digital audio I/F

DSP Synchronous Serial Ports interfacing with RF, speech

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PXA800F Block DiagramPXA800F Block Diagram

IF

ESED

ISBIUSwitch

PeripheralBus 1

PeripheralBus 2

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ReferencesReferences

On the hardware-software partitioning problem: System mOn the hardware-software partitioning problem: System modeling and partitioning techniquesodeling and partitioning techniques

Marisa López-Vallejo, Juan Carlos López Marisa López-Vallejo, Juan Carlos López July 2003 ACM July 2003 ACM

Transactions on Design Automation of Electronic Systems Transactions on Design Automation of Electronic Systems

(TODAES)(TODAES), Volume 8 Issue 3, Volume 8 Issue 3

A hardware/software A hardware/software partitionerpartitioner

using a dynamically determined granularity using a dynamically determined granularity Jörg Henkel, Jörg Henkel,

Rolf Ernst Rolf Ernst June 1997 Proceedings of the 34th annual June 1997 Proceedings of the 34th annual

conference on Design automation conference conference on Design automation conference

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ReferencesReferences

Issues in partitioning & design space Issues in partitioning & design space eplorationeploration for for

codesigncodesign

: Dynamic hardware/software partitioning: a first approach: Dynamic hardware/software partitioning: a first approach

Greg Stitt, Roman Lysecky, Frank Vahid Greg Stitt, Roman Lysecky, Frank Vahid June 2003 June 2003

Proceedings of the 40th conference on Design automation Proceedings of the 40th conference on Design automation

Hardware/software partitioning of software binaries Hardware/software partitioning of software binaries Greg Greg

Stitt, Frank Vahid Stitt, Frank Vahid November 2002 Proceedings of the 2002 November 2002 Proceedings of the 2002

IEEE/ACM international conference on Computer-aided IEEE/ACM international conference on Computer-aided

design design