200 978-4-86348-010-0 2009 Symposium on VLSI Circuits Digest of Technical Papers

19-3Dual-Power-Path RF-DC Multi-Output Power Management Unit for RFID Tags

Jun Yi, Wing-Hung Ki, Philip K. T. Mok and Chi-Ying TsuiDepartment of Electronic and Computer Engineering

The Hong Kong University of Science and TechnologyClear Water Bay, Hong Kong SAR, China, Email: eeyi, eeki, eemok, eetsui@ece.ust.hk

AbstractA dual-power-path (DPP) RF-DC topology is employed todesign the power management unit for an EPC C1 G2 RFIDtag using a 0.18µµµµm CMOS process with 7 output voltages forsignal processing blocks and OTP memory. The DPP techniquesplits the rectifier and reconfigures the RF-DC circuitsdepending on the state of input power, which saves storagecapacitor size without sacrificing efficiency, or alternatively,improves efficiency without additional capacitance.

I. IntroductionImproving RF-DC power conversion efficiency and

reducing cost are major issues in the design of RFID tags. Theupper part of Fig. 1 shows two existing RF-DC topologies [1-5]consisting of a rectifier, a storage capacitor, and with or withouta low dropout regulator (LDR). Previous works focused on therectifier with little attention on LDR efficiency and the storagecapacitor.

When receiving data-0 from the reader, the tag receivespower only for the first part of the Tari (complementary pulsewidth, CPW) [6], and the energy needed in the second part (PW)has to be stored by charging up the capacitor(s) during CPW.Similar situation happens for backscattering. Let the tag be at themaximum working distance that the input power is just adequatefor proper function. For Type-I topology, the received RF energyis converted to DC by a rectifier RECT, or with an LDR incascade, to supply the load and to charge up a storage capacitorCSI. The minimum CSI is IL×PW/∆VDD. To keep the area of CSIacceptable for on-chip implementation, [2] and [3] used large∆VDD, which however is undesirable for loading circuits; [5]considers making IL small, limiting the system function; and [1]used special FeRAM process offering very high capacitancedensity. This problem becomes increasingly pronounced as morefunctionalities like security protection and sensing are needed.Type-II topology mitigates the problem by moving the storagecapacitor CSII before LDR. With the LDR regulating VDD, ∆VCSIIcould be relatively large to allow a small CSII, trading off theefficiency of the LDR efficiency. Assume VCSII ramps up anddown linearly, the efficiency of the LDR is

ηLDR-II = α×∆VDD/(VDD + Vdo + 0.5∆VCSII) (1)where α=IL/(IL+ILDR), with the bias current ILDR << IL, and Vdo isthe dropout voltage of the LDR. Since ∆VCSII =(IL+ILDR)×PW/CSII, attaining high efficiency needs a large CSII.

II. Proposed Dual-Power-Path TopologyOur proposed dual-power-path topology is also shown in

Fig. 1, with related waveforms in Fig. 2. The rectifier of theprevious topologies that need to drive both resistive load (IL) andcapacitive load (storage capacitor) is split into two sub-rectifiersRECT_P and RECT_S, with RECT_P driving mainly theresistive load and RECT_S driving only the capacitive load. Asignal φDEM from the demodulator circuit controls theconfiguration. During the CPW phase (φDEM = "1"), switchesMSPA, MSPB and MSSA are closed, and the primary power path(PPP) is activated by connecting the LDR to RECT_P and CP.

This research is in part supported by Grant Research Council RGC 614506.

The load is supplied by RECT_P directly. At the same time,RECT_S charges up the secondary power path (SPP) storagecapacitor CS to VDD+Vdo+∆VCS. Once the PW phase starts the RFpower becomes zero, but φDEM changes from "1" to "0" with adelay of tdem which the finite response time of the demodulator.During the duration tdem, reverse leakage currents of the rectifiersdrain CS and CP, and CP also supplies the load so the voltageripple ∆VCP is (IL+ILDR+Ileak)×tdem/CP, which will be replenishedin the next CPW. With the elapse of tdem, leakage stopsimmediately by opening MSPA and MSSA. MSPB is also opened,disconnecting LDR from CP. To avoid undesirable chargesharing between CP and CS, MSSB is closed after a very smalldead-time. SPP is then enabled and CS is discharged by the loadduring PW so ∆VCS=(IL+ILDR)×PW/CS. Typically, PW is equal toCPW, and the overall LDR efficiency is

ηLDR-DPP = α×VDD/(VDD + Vdo + 0.25∆VCS + 0.25∆VCP) (2)Ideally, tdem=0 so ∆VCP=0 and CP is not needed. LDR

efficiency is improved if ∆VCS=∆VCSII. Conversely, if we keep

Fig.1. Existing and proposed RF-DC topologies.

Fig.2. Voltage waveforms of DPP topology (left). Ripple voltage ratio versuscapacitance saving with equal LDR efficiency (upper right). The maximumcapacitance saving versus tdem (lower right).

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2012009 Symposium on VLSI Circuits Digest of Technical Papers

the same efficiency, area of capacitors can be saved by 50% byallowing ∆VCS to be twice of ∆VCSII. In practice, tdem is finite,resulting in a finite ∆VCP. As tdem is very small, keeping ∆VCPmuch smaller than ∆VCS does not need a large CP, but areasaving is not optimal if ∆VCP is designed to be too small. Theripple voltage ratio ∆VCP/∆VCS is found to have an optimal valuethat gives maximum capacitance saving, as shown in Fig. 2. Theplot for tdem is also shown. In general, a saving of 20% to 40% incapacitor area can be achieved compared to Type-II topology,and more compared to Type-I. Alternatively, LDR efficiency canbe enhanced by about 10% to 15% with equal capacitance.

III. Multiple-Output PMU and Measurement ResultsFig. 3 shows the designed PMU that consists of two 0.5V

supplies for sensor and clock recovery circuit, two 1V suppliesfor demodulator and analog blocks, one 1.7V supply for signalprocessing and memory control, and 3.5V and 7V supply formemory reading and programming, respectively. DPP technique

is used for LDR2 and LDR3 with loads that consume most of thetag power: 3µA and 15µA, respectively. CP2B and CS2 are forLDR2, and CP3 and CS3 are for LDR3. For other LDRs, Type-IItopology is used. CP2A is for LDR_ST. A diode-connected nativenMOS MST is placed across SPA2 to jumpstart the bandgapreference and then the LDR_ST that powers the demodulatorfirst for proper startup.

The total size of two sub-rectifiers remains approximatelyunchanged as the original rectifier, as the loads are divided.RECT_P has three outputs, and RECT_S has two separateoutputs at the 18th stage, as shown in Fig. 4. A proposed "super-diode" with very steep I-V curve is used for protection. Fortesting purpose, the PMU is characterized using a 50-Ω signalgenerator providing a 900MHz 100% ASK modulated signal. Fig.5 shows the measured capacitor and supply voltages of the test

chip in Fig. 6. All the voltages are close to the designed values asshown in Fig.3. Table I and Table II show the performancesummary and comparison with other works.

IV. References[1] H. Nakamoto et. al., "A passive UHF RFID tag LSI with 36.5%

efficiency CMOS-only rectifier and current-mode demodulatorin 0.35µm FeRAM technology," IEEE Int'l. Solid-State Circ.Conf., pp. 310-311, Feb. 2006.

[2] A. Missoni et. al., "A triple-band passive RFID tag," IEEE Int'l.Solid-State Circ. Conf., pp. 288-289, Feb. 2008.

[3] U. Karthaus and M. Fischer, "Fully integrated passive UHFRFID transponder IC with 16.7-W minimum RF input power,"IEEE J. of Solid-State Circ., pp.1602–1608, Oct. 2003.

[4] W. G. Yeoh et. al., "A CMOS 2.45-GHz radio frequencyidentification tag IC with read/write memory," IEEE RadioFrequency Integrated Circ. Symp., pp.365-368, Jun. 2005.

[5] G. Balachandran and R. Barnett, "A 110nA voltage regulatorsystem with dynamic bandwidth boosting for RFID systems,"IEEE J. Solid-State Circ., pp. 2019-2028, Sep. 2006.

[6] EPC Class-1 Generation-2 UHF Air Interface Protocol StandardVersion 1.0.9.

TABLE I. PERFORMANCE SUMMARYParameter Measurement Notes

–6.63 / –3.396dBm

Read mode. Averaged in Tari / During CPW Input Power

–0.312dBm Write mode Rectifier

Output Power 119.6µW During CPW. Stored energy is 747.6pJ

Rectifier Efficiency 26.1% Read mode

PMU Output Power 35.6 / 84.8µW * Read / Write mode

PMU Efficiency 16.4% / 9.2% * Read / Write mode

27.02 – 37.86jΩ Read mode, 900MHz Input Impedance

34.48 – 26.66jΩ Write mode, 900MHz

Modulation 100% ASK PW = 0.525Tari = 13.125µs is used

Area 0.56684mm2 Storage MOSCAPs: 0.15684mm2

* The PMU is optimized for read mode. In write mode, the excessive current is drained by turning on of protection circuits whose power is unknown and hence not included.

TABLE II. COMPARISON WITH EXISTING WORKPMU load

power /current

Efficiency Storage

Cap. size

Length of PW

VDD drop ∆∆∆∆VDD

Modu-lation

CMOSTech.

[1] 80µW 36.6% N/A N/A N/A 15% ASK

0.35-µm FeRAM

[2] N/A N/A 0.11mm2 N/A 0.4V ASK 0.12-µm [3] 1.5µA 18% 250pF 100µs 0.6V PWM 0.5-µm

[4] 21.7µA / 26.6µW *

6.3% * 1nF ~ 2.3µs ~ 50mV * 75 % OOK 0.25-µm

[5] ~ 4µA # N/A 250pF 12.5µs ~ 0.2V # ASK 0.15-µm This work 35.6µW 26.1% (rect.)

16.4%(PMU) 1.055nF † 12.5 /13.125µs regulated 100%

ASK 0.18-µm

* [4] reports 100µW output with 2dBm input. Load current, power, and VDD drop are estimated from Fig.8 of [4]. # Estimated from Fig.18 of [5], which shows about 0.2V drop of VDD over 12.5µs. † CP1=150pF, CP2A&CP2B=300pF, CP3=220pF, CS2=55pF and CS3=330pF.

Fig.6. Chip micrograph

Fig.3. The multiple-output PMU using DPP topology.

Fig.4. RECT_S protected by super diode and simulated I-V curve.

Fig.5. Measured capacitor voltages and supply voltages.

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