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Team M3: Jacob Thomas Nick Marwaha Darren Shultz Craig T. LeVan Project Manager: Zachary Menegakis. DSP 'Swiss Army Knife'. Overall Project Objective: General purpose Digital Signal Processing chip. Stage 2 | January 24, 2005 | Architecture Proposal. Architecture Proposal. - PowerPoint PPT Presentation
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DSP 'Swiss Army Knife'
Team M3:Team M3:Jacob ThomasNick MarwahaDarren Shultz
Craig T. LeVan
Project Manager: Zachary MenegakisProject Manager: Zachary Menegakis
Overall Project Objective:General purpose Digital Signal Processing chip
Stage 2 | January 24, 2005 | Architecture Proposal
● General Purpose chip that performs a wide variety of functions– Differencer– Integrator– Leaky Integrator– First-Order Delay Network– Audio Comb– Etc
● Significance– Applications in all fields of DSP (digital signal processing)– Replaces commonly used algorithms based on the input coefficients– Help increase efficiency of DSP circuit design via re-use
Architecture Proposal
Stage 2 | January 24, 2005 | Architecture Proposal
Final Algorithm[1]
● H(z ) = (1 − c1z−N ) xb0 + b1z−1 + b2z−2
1/a0 − a1z−1 − a2z−2
Stage 2 | January 24, 2005 | Architecture Proposal
Initial Block Diagram
Floating Point Modification
Stage 2 | January 24, 2005 | Architecture Proposal
Floating Point Addition[2]
Stage 2 | January 24, 2005 | Architecture Proposal
Refined Components
Stage 2 | January 24, 2005 | Architecture Proposal
FP Multiplier
Floating Point Adder Detail
Benchmark Graphs
Matlab Codefunction output = swiss(z,a,b,c,N)%a DSP "swiss army knife"
n = [0 1 zeros(1,98)];max = length(z);t = [-0.5: 2*0.5/max: 0.5-2*0.5/max];
Hz = (1-c*z.^-N) .* ((b(1)+b(2)*z.^-1+b(3)*z.^-2) ./ ... ( (1/a(1))-a(2)*z.^-1 - a(3)*z.^-2));
plot(t,(abs(fftshift(Hz)).*10)-12.5,'b');
output = real(fftshift(Hz).*10)-12.5;
Stage 2 | January 24, 2005 | Architecture Proposal
Benchmark Graphs
Matlab Results
a0 = a1 = 1 ; a2 = 0
b0 = 1/N ; b1 = b2 = 0
c1 = 1 ; N = 8
Stage 2 | January 24, 2005 | Architecture Proposal
Matlab Results
a0 = 1 ; a1 = 0 ; a2 = 0
b0 = 1 ; b1 = -1 ; b2 = 0
c1 = 0
Stage 2 | January 24, 2005 | Architecture Proposal
Matlab Results
a0 = a1 = 1 ; a2 = 0
b0 = 1 ; b1 = 0 ; b2 = 0
c1 = 0
Stage 2 | January 24, 2005 | Architecture Proposal
Matlab Results
a0 = 1 ; a1 = 1 - α ; a2 = 0
b0 = α ; b1 = 0 ; b2 = 0
c1 = 0 ;
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Code
module swiss
(output reg [11:0] hz,
input [11:0] z, // in floating point form i.e. S*b^E [11]sign/[10:6]E/[5:0]S
input [4:0] N, // assumption that N is a positive integer
input [1:0] c1, b0, b1, b2, a0, a1, a2); // bit1 for sign, bit0 for value
// assuming all inputs except z are -1, 0, 1
// currently non-renormalized floating point numbers
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Code
reg [11:0] zN; // create an intermediate floating point variablereg [11:0] one = 12'b000000000001;reg [11:0] num = 12'b000000000000;reg [11:0] numtemp = 12'b000000000000;reg [11:0] den = 12'b000000000000;reg [11:0] dentemp1 =12'b000000000000;reg [11:0] dentemp2 =12'b000000000000;reg [11:0] biquad = 12'b000000000000;reg [4:0] diff;reg [3:0] i;
always@(z, N, c1, b0, b1, b2, a0, a1, a2)beginzN = z;// set intermediate variable zN to value of input z
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Code// performing operation z^Nif (N==5'b00000) zN = 12'b000000000001;else begin for(i=4'b0001; i<N; i=i+1) begin zN[5:0] = zN[5:0] * z[5:0]; zN[10:6] = zN[10:6] + z[10:6] - 5'b01111; if(zN[11] == 1 && z[11] == 0) zN[11] = 1; else if(zN[11] == 0 && z[11] == 1) zN[11] = 1; else zN[11] = 0; end end // else: !if(N==5'b00000)
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Code
// performing operation c1/z^N (or c1*z^-N)if (c1[0] == 0) zN = 12'b000000000000;else begin zN[5:0] = 6'b000001 / zN[5:0]; zN[10:6] = -zN[10:6] + 5'b01111; if(c1[1] == 1 && zN[11] == 0) zN[11] = 1; else if(c1[1] == 0 && zN[11] == 1) zN[11] = 1; else zN[11] = 0; end // else: !if(c1[0] == 0)
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Code// performing operation 1 - c1*z^-N// zN = 1 - c1*z^-N (comb filter) zN[11]=~zN[11];if(one[10:6]>zN[10:6])begin diff[4:0]=one[10:6]-zN[10:6]; zN[5:0] = zN[5:0]>>diff;endelse if(zN[10:6]>one[10:6])begin diff[4:0]=zN[10:6]-one[10:6]; one[5:0] = one[5:0]>>diff;endzN[5:0]=zN[5:0]+one[5:0];
one[11:0] = 12'b000000000001;
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Code
// performing b1/z (or b1*z^-1)if (b1[0] == 0) num[11:0] = 12'b000000000000;else begin num[5:0] = 6'b000001 / z[5:0]; num[10:6] = -z[10:6] + 5'b01111; if(b1[1] == 1 && num[11] == 0) num[11] = 1; else if(b1[1] == 0 && num[11] == 1) num[11] = 1; else num[11] = 0; end // else: !if(b1[0] == 0)
(...etc...)
Stage 2 | January 24, 2005 | Architecture Proposal
Verilog Test Benchmodule test_swiss
(output n,z,b0,b1,b2,a0,a1,a2 input hz);
initial
begin $moniter($time,,
"n=%b z=%b b0=%b b1=%b b2=%b a0=%b a1=%b a2=%b hz%b" n,z,b0,b1,b2,a0,a1,a2,hz);
#10/// (set input values here) #10/// Inputs not well defined, so no useful comparison to matlab results yet #10 #10 end // initial beginendmodule // test_swiss
Stage 2 | January 24, 2005 | Architecture Proposal
Proposal Estimates
Part Transistor Count Size Count Total Transistors Total Size
8-bit Full Adder 500 100x90=9,000 3 1,500 27,000
8-bit Multiplier 2000 200x180=36,000 7 14,000 252,000
8-bit Divider 3000 245x220=54,000 3 9,000 162,000
TOTALS N/A N/A N/A 24,500 441,000
Stage 2 | January 24, 2005 | Architecture Proposal
Waiting to re-calculate based on input definitions and the bit-width of the floating point numbers
(12-point FP gives similar estimates as above)
Marketing● DSP
– Communications● Wireless & standard
– Video● Noise reduction
– Audio● Basic building block of acoustic audio effects such as
acoustic echo simulation and plucked instrument synthesis● May require floating point accuracy to be useful
Stage 2 | January 24, 2005 | Architecture Proposal
Status● Research (restarted)● Transistor count (awaiting defined inputs)● Block Diagram (altered for floating point)● Verilog description (50%)● Layout (0%)
➢ To Be Done➢Define inputs and FP bit-width➢Finalize Transistor count➢Refine block diagram➢Verilog / Layout / Verification
Stage 2 | January 24, 2005 | Architecture Proposal
Design Decisions
● Move to floating point architecture
● Memory / Registers not included pending bit-width
Stage 2 | January 24, 2005 | Architecture Proposal
Problems & Questions
● Benchmark inputs not well defined
● Pushing the transistor count cap
● Hardware implementation of x-n and -1 not obvious (solved by floating point)
● Circuit may be a 'novelty' at only 8 bits(solved by floating point)
Stage 2 | January 24, 2005 | Architecture Proposal
References
● [1] http://www.ecpe.vt.edu/fac_support/DSPCL/docs/SPMag04.pdf
● [2] http://www.cse.psu.edu/~cg575/lectures/cse575-fpops.pdf