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A NEW TRANSVERSE AND LONGITUDINAL BUNCH BY BUNCH FEEDBACK PROCESSOR

M.G. Abbott, G. Rehm, I.S. Uzun1

Diamond Light Source, Oxfordshire, UK1STFC, UK

A NEW TRANSVERSE AND LONGITUDINAL BUNCH BY BUNCH FEEDBACK PROCESSOR

M.G. Abbott, G. Rehm, I.S. Uzun1

Diamond Light Source, Oxfordshire, UK1STFC, UK

Abstract and Context

Abstract We describe the development offirmware to support Longitudinal Bunch byBunch Feedback at Diamond Light source. Aswell as feedback, the system supports complexexperiments and the capture of detailed electronbeam diagnostics. In this paper we describethe firmware development and some details ofthe processing chain. We focus on some ofthe challenges of FPGA development from theperspective of a software engineer.

We are transitioning from Libera Bunch-by-Bunchplatform (based on 15 year old Virtex-II ProFPGA) to MicroTCA, which provides access tomore up to date hardware.

New Hardware Platform

Here we see the chosen hardware platform, with a 500 MSPSADC/DAC FMC card at top right, and a Virtex-7 690 FPGAunder the heatsink at bottom left.FMC-500M High Pin Count FMC providing dual channel

500 MS/s 14-bit ADC and dual channel 1230 MS/s 16-bitDAC. This will support bunch-by-bunch operation at ourmachine RF frequency of 500 MHz.

AMC525 Double width AMC card with two HPC FMC slots,2 GB of fast on board DRAM and 128 MB of slower DRAMconnected to a Virtex-7 690 FPGA, supporting an 8 lanegen3 PCIe connection over the MicroTCA backplane. Thisis where all the FPGA firmware will run, and the fastbackplane connection will allow us to do a lot of dataprocessing in the associated CPU.

Data Processing Paths through Bunch-by-Bunch Processor

ADC Bunch FIR DAC

ADCOVF

FIR

MMS

MEM0

÷N BBFIR ×N

MEM0

G

G

G

+ ×

MMS

MEM0

FIR DLYDAC

sequencer

bunchselect

detector

∼NCO1

∼ NCO0

MEM1

This figure shows the data processing for a single LMBF/TMBF channel:OVF ADC input overflow detection (programmable threshold)FIR I/O compensation filter (8 tap FIR)

MMS bunch position and motion measurement, measures min/max/sum and sum of squares÷N bunch by bunch decimation (average over programmable count)

BB FIR bunch by bunch filter (8 tap FIR per bunch)×N bunch by bunch interpolationG gain control (scale by power of 2)

DLY output alignment delay∼ controllable oscillator (NCO)

Overflow detection and saturation is implemented at each point where overflow can occur.

Overview of Implementation

interconnect

axi burstmaster

axi liteslave

axi litemaster

registertop

systemregisters

clocking

dsp main

fmc500m

PLLADC DAC

ADCin DACoutfRF fREV

idelay

125 MHz

TRG PM BLK SEQ0 SEQ1

fmc digital io

REF CLK

REG CLK

DSP CLK

ADC CLK

PCIeDRAM0

2 GBDRAM1128 MBDRAM1128 MB

100 MHz

fmc500m

idelay interrupts

ADC (×2)

DAC (×2) TRG/PM/BLK

SEQ0/1

PCIe DSPint

DMADSP DRAM

DRAM DMA PCIe

MGT PCIe

�

DSP

DMA interruptcontrol

�

DRAM

DSP

registerinterface

adc

sequencer

ADCbunch

fir

FIR

bunchselect

BNCH

nco0 NCO0

nco1 NCO1

dac

DAC

detector

ADCin DACout

adc event

nco1gainnco1gain

trigger

blankingwindowwindow

start/writestart/write

SEQ

DRAM1

turn clock T

registers R

R

T R T R T R

T R

T R T R

Overview of top level FPGA design.The “interconnect” at the top connects to all of the hardware resources provided bythe AMC525 carrier card, including 8-lane PCIe and 2 GB of fast DRAM. The restof the this figure shows connections to the FMC cards, clocking and control, and thedata processing core “dsp main”.

Overview of data processing implementation for a single channel.The symbol ADC represents points were data is interchanged with the other channeldepending on whether TMBF or LMBF mode has been selected.