DSP CONTROL OF A T H R E E PHASE UPS INVERTER

by

Kenneth Wicks

B.ASc., University of British Columbia, Canada, 1997

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

in

THE FACULTY OF GRADUATE STUDIES (Department of Electrical and Computer Engineering)

We accept this thesis as conforming

to the required standard

THE UNIVERSITY OF BRITISH COLUMBIA

February, 2001

©KennethWicks, 2001

In presenting t h i s thesis i n p a r t i a l f u l f i l m e n t of the requirements for an advanced degree at the U n i v e r s i t y of B r i t i s h Columbia, I agree that the Library s h a l l make i t f r e e l y a v a i l a b l e for reference and study. I further agree that permission for extensive copying of t h i s thesis for s c h o l a r l y purposes- may be granted by the head of my department or by his or her representatives. I t i s understood that copying or p u b l i c a t i o n of t h i s thesis for f i n a n c i a l gain s h a l l not be allowed without my written permission.

Department of ^L^C^tohU f\pXi CQnfWTfc&. £fr&Mfrfc£\Nr'-r

The U n i v e r s i t y of B r i t i s h Columbia Vancouver, Canada

Date • / 2 0 Q )

A b s t r a c t

The demand for three-phase uninterruptible power supplies has increased with the

decrease in reliability of power supplied by power utilities. A single three-phase

uninterruptible power supply (UPS) can typically supply many loads at a time. A UPS

must be able to supply relatively undistorted output line voltages with highly non-linear

loads. Many papers have been devoted to introducing new control schemes that can

supply these loads effectively.

A new control scheme is introduced, in this work, which is implemented with a

digital signal processor (DSP). The controller acts in a stationary reference frame as

opposed to the commonly used rotating reference frame. Although using a stationary

reference frame can create phase errors, the control algorithm is computationally more

efficient than using a rotating reference frame. The proposed technique uses two line

voltages and the corresponding differential output filter inductor currents for those lines

as the control variables. As a result, this technique utilizes fewer sensors compared to

techniques using a rotating reference frame.

In this work, the plant model is developed and the stability of the controller is

analyzed. The controller design is facilitated with the use of a Mathcad workspace,

Steady-state simulations and experimental results are presented for a balanced resistive

load. Even with relatively slow inner current loops, the performance of the controller is

acceptable. Slow current controllers are used because of large noise in the current

measurements of the experimental inverter.

This work provides the basis to further investigate the feasibility of using the

proposed controller to supply non-linear loads.

ii

T a b l e o f C o n t e n t s

ABSTRACT ii

LIST OF TABLES v

LIST OF FIGURES vi

LIST OF ACRONYMS viii

ACKNOWLEDGEMENTS ix

C H A P T E R 1 : INTRODUCTION 1

1.1 Three Phase UPS Circuit Description 1

1.2 Current Control Techniques 4

1.3 Proposed New Control Technique 8

1 4 Outline of the Thesis 11

C H A P T E R 2: ANALYSIS O F T H E N E W C O N T R O L T E C H N I Q U E 12

2.1 Small Signal Time Averaged Plant Model 12

2.1.1 Unbalanced Loads 17

2.1.2 Floating Filter Capacitor Neutral 18

2.2 Current Control Loop Analysis 18

2.3 Voltage Control Loop Analysis 26

C H A P T E R 3: SIMULATION USING PSIM 31

3.1 Circuit Description 31

3.2 Simulation Results and Discussion 35

C H A P T E R 4: E X P E R I M E N T A L UPS DESIGN 42

4.1 Description of the Power Circuit 42

4.1.1 AC-DC Rectifier Section 42

iii

4.1.2 Three Phase Inverter 44

4.1.3 Gate Driver Circuitry 45

4.1.4 Sensor Circuitry 46

4.2 Introduction to the DSP and its Features 49

4.2.1 DSP Core 50

4.2.2 Analog-to-Digital Unit 51

4.2.3 The PWM Controller 51

4.2.4 Programmable Interrupt Controller 54

4.3 DSP Code 54

4.3.1 Discretization of the Continuous-time Controllers 55

4.3.2 Program Code Description 57

C H A P T E R 5: E X P E R I M E N T A L RESULTS 63

5.1 Output Line Voltages 63

5.2 Effect of Noise on the Generated Line Voltages 67

C H A P T E R 6: CONCLUSIONS 70

6.1 Contributions 70 6.2 Future Work 71

BIBLIOGRAPHY 72

APPENDIX A: GATE DRIVER INTERFACE PCB LAYOUT 75

APPENDIX B: DSP CODE LISTING 76

B.l Modpi.h 76

B.2 Modpi.dsp 78

B.3 Main.dsp 80

iv

List of Tables

Table 2.1 Results from current controller design 24

Table 2.2 Voltage controller results for Kp = 0.3116, KI2 = 1000,

K V = 1500 2 9

Table 4.1 Spreadsheet for inductor design 44

Table 5.1 Measured output voltages for two current controller gains 64

v

L i s t o f F i g u r e s

Figure 1.1 Power circuit for the UPS 2

Figure 1.2 Voltage controller in D-Q reference frame 5

Figure 1.3 Addition of load current as a feedback signal 6

Figure 1.4 Space vector modulation 7

Figure 1.5 Basic system structure 8

Figure 1.6 Basic system structure with third harmonic injection 10

Figure 1.7 Basic system structure with the addition of load current

feedforward 10

Figure 2.1 UPS circuit to be controlled 12

Figure 2.2 Swl is on and Sw2 is off 13

Figure 2.3 Swl is off and Sw2 is on 14

Figure 2.4 Small signal time averaged plant model 17

Figure 2.5 Current control loops showing digital control elements 19

Figure 2.6 Current closed loop block diagram 20

Figure 2.7 Magnitude plot for R = 15fi, K = 0.055, K, = 1000 25

Figure 2.8 Phase plot for R = \5Q, K = 0.055, Kt = 1000 25

Figure 2.9 Voltage control loop block diagram 26

Figure 2.10 Magnitude plot for Kp = 0.3116, Kn = 1000, Kv = ^ 30

Figure 2.11 Phase plot for Kp = 0.3116, Kn = 1000, Kv = ^ 30

Figure 3.1 Power circuit with control connections 32

Figure 3.2 Deadtime insertion block 33

Figure 3.3 Controller block 34

Figure 3.4 Simulated line voltage VAB with the controller and for open loop 36

Figure 3.5 Simulated line voltage VCB with the controller and for open loop 36

Figure 3.6 Simulated duty-cycles for Kp = 0.065 37

v i

Figure 3.7 Simulated line voltages for Kp = 0.065 and Kp = 0.055 38

Figure 3.8 Simulated line voltages Vab and Vcb produced with noisy sensors 39

Figure 3.9 Simulated duty-cycles produced with noisy sensors 40

Figure 3.10 Small section of the duty-cycle for phase A 40

Figure 4.1 A C - D C rectifier section 43

Figure 4.2 Isolation transformer and variac 43

Figure 4.3 Gate drive circuitry 47

Figure 4.4 Level-shifting circuit for the current sensor 48

Figure 4.5 Voltage sensor circuit 49

Figure 4.6 Deadtime insertion into duty-cycle for phase A. Signals are active

low , ' 53

Figure 4.7 Signal flow diagram for a discretized PI controller 56

Figure 4.8 Signal flow diagram for a discretized modified PI controller 57

Figure 4.9 DSP initialization and infinite loop routine MAIN 58

Figure 4.10 A D C end-pf-conversion interrupt service routine 59

Figure 4.11 PI and modified PI controller routines where: sf = scaling factor 62

Figure 5.1 Measured steady-state output line voltages for K = 0.065, 19 Q

load 65

Figure 5.2 Measured steady-state output voltages for no controller, 19 Q

load 65

Figure 5.3 Measured output voltage from isolation amplifier 66

Figure 5.4 Measured differential inductor current after level shifting circuit 66

Figure 5.5 Measured duty-cycle for phase A for K = 0.065,19 Q load 68

Figure 5.6 Measured current reference iABref for K = 0.065,19 Q load 68

Figure 5.7 Comparison of current controller proportional gains for a 19 Q

load 69

v i i

L i s t o f A c r o n y m s

A/D. Analog-to-Digital

ADC: Analog-to-Digital Converter

A L U : Arithmetic and Logic Unit

D/A: Digital-to-Analog

DSP: Digital Signal Processor

ESR: Equivalent Series Resistance

IGBT: Insulated Gate Bipolar Transistor

M A C : Multiply And accumulate

PI: Proportional-Integral

PWM: Pulse Width Modulation

rms: root mean square

UPS: Uninterruptible Power Supply

ZOH: Zero Order Hold

v i i i

A c k n o w l e d g e m e n t s

I am deeply indebted to my supervisor, Dr. W.G. Dunford, for his advice on

solving the various hardware problems that I encountered. I would also like to thank my

previous supervisor, Dr. Hua Jin, for his advice and financial support.

I feel honoured to work beside many great colleagues in the Power Group at

UBC. I especially would like to thank Stephane Bibian, Yingran Duan, Anil Tuladhar,

Richard Rivas, and Mazana Lukic for the useful discussions that we have shared.

Lastly, but not least, I would like to thank my parents for putting up with me for

all these years.

ix

Chapter 1

Introduction

With the increasing threat of power failures today, there is a greater need for

uninterruptible power supplies to protect sensitive loads. Typically, a single three-phase

uninterruptible power supply (UPS) can supply many single-phase and three-phase loads.

The power supply must be able to maintain relatively undistorted output line voltages

with non-linear loads. This has been the focus of many papers in approximately the last

ten years. In this thesis, a new technique is proposed and analyzed for a balanced

resistive load. This provides the basis to further investigate the performance of this

technique with unbalanced and non-linear loads.

This chapter begins with the general description of a three-phase UPS.

Specific component values are also given at this point to facilitate the discussion in this

work. Some of the more prevalent current techniques will then be described on a general

basis. The new proposed control technique will follow the discussion on the current

techniques. Finally, the outline of the thesis will be presented.

1.1 Three Phase UPS Circuit Description

The power circuit for a three phase UPS, as shown in Figure 1.1, can be

functionally split up into three parts: a dc power source, a bridge circuit composed of six

or more "switches", and an output filter stage for each output phase. If isolation is

required then a three-phase transformer is connected to the output but this is considered

part of the load for this work. The dc power source can be many things. One example is

a high voltage battery. This work assumes that the dc source is ideal. The bridge circuit

consists of three "legs" of two power semiconductor devices that operate like switches.

The choice of the semiconductor device depends on the power required for the load. The

output filters are composed of an inductor and a capacitor and will be referred to as an

L C filter.

The power devices are turned on and off by controlling the gate voltages of the

devices. The gating patterns for the switches are determined by using a technique called

pulse-width modulation (PWM). The desired voltage waveform for each phase is

compared to a high frequency carrier waveform typically with a fixed frequency. A

triangular carrier waveform is used for inverter applications. Switching transitions occur

when the desired voltage waveform equals the carrier waveform. There are, therefore,

two switching transitions per switching period for each inverter leg. The gating pattern

for a leg is applied to the switch connected to the positive dc bus rail and the

complementary pattern is applied to the switch connected to the negative dc bus. If a

deadtime period is required between the on patterns of the two switches, then the

switching transitions are modified to include the deadtime.

Vdc / 2

V d c / 2

/YYYV

Figure 1.1: Power circuit for the UPS

2

Notice that the dc supply is split into two separate supplies. This could be a

center tapped filter capacitor. The dc supply does not necessarily have to be split. If the

ground is moved to the negative dc bus rail then the generated phase voltages will always

be greater that the ground potential. The center tapped supply causes the phase voltages

to be centered about the ground potential. In either case the generated line voltages are

centered about the ground potential and are identical for both configurations.

The L C filter capacitors, as shown in Figure 1.1, are connected to the center

tapped dc supply. Typically, the capacitors are not connected to the dc bus. As will be

shown in Chapter 2, the connection of the capacitors does not change the small signal

time-averaged model of the inverter. This work assumes that the capacitors are

connected to the dc bus filter capacitor.

The resonant frequency of the output L C filter is typically chosen to be at least

one decade below the switching frequency. In this case, the resonant frequency of the

filter is approximately 1 kHz which is substantially lower than the switching frequency of

18 kHz. The equivalent series resistance (ESR) of the output filter capacitor is included

in the model of the inverter. The ESR of the inductor is typically neglected so it is not

included in the model of the inverter.

The dc bus voltage and the full load power rating were chosen for convenience.

The values for the dc bus voltage Vdc ,the filter inductor L, the output filter

capacitor C , and the output filter's ESR Rc used for the analysis of this work are given

by:

Vdc = 230 V

L = 2.53 mH

C = \\pF

Rc = 0.3 fi

3

The full load power rating is 1 kVA. The nominal output line voltage is 104 V.

1.2 Current Control Techniques

Many different techniques are used to control three-phase three wire UPS

systems. This section summarizes some of the current techniques available. A paper

presented at an IEE colloquium titled "Control of UPS Inverters" [1] has a good summary

of the state of the art as of 1994.

Three-phase UPS systems are either controlled in a stationary reference frame,

such as the proposed controller in this work, or in a rotating (D-Q) reference frame as

shown in Figure 1.2 . Most of the control techniques that are developed today use the

rotating reference frame. There are two cited major advantages of using the rotating

reference frame: the controller operates on dc quantities while the stationary reference

frame techniques operate On ac quantities, and the bandwidth requirements are lower for

controllers based on the rotating reference frame. Using dc quantities implies that there

is no phase error between the input command voltage and the output voltage. A

proportional and integrator (PI) type controller will ensure that the error in steady state is

zero. Unfortunately, in the stationary reference frame, the controller introduces a phase

error between the input and output voltages. There are techniques available that can

compensate for the phase error if necessary but they work only for fixed frequency UPS

applications [2]. This work assumes that the phase error is acceptable. There are two

drawbacks of using the D-Q reference frame: the voltages (and often currents) need to be

converted into the D-Q reference frame using the transformation given in Equation 1, and

the number of required voltage sensors is greater than the proposed technique since all of

the phase voltages need to be measured. The control variables do not need to be

transformed into the stationary reference frame thus, computationally, control in the

stationary reference frame is more efficient.

4

cos(0) cos(0-^) cos(0 + ^ ) l sin(0) sin(0--^) sin(0 + ̂ ) ( 1 )

where: 0 = cot

co = speed of the rotating frame [rad/s] (2)

The voltages in the D-Q reference frame are given by:

K Vq}=T(0)[VA VB Vcf (3 )

In summary, control in a stationary reference frame is computationally more

efficient than control in a rotating reference frame since no transformation of the control

signals is required but stationary reference frame control produces phase errors between

the inputs and the outputs that do not occur using a rotating reference frame with a PI

type controller.

T(6)

Figure 1.2: Voltage Controller in D-Q reference frame

For applications where the control for the inner inductor current loop is done in

the stationary reference frame, the reference inductor currents need to be converted back

into the stationary reference frame. One example of a design utilizing the rotating

reference frame for voltage control and the stationary reference frame for current control

is given in [3] .

5

The dynamic performance of the controller is increased by measuring and using

the load currents. Simple techniques use the load current as a feedforward signal to

modify the inductor current reference as shown in Figure 1.3. More elaborate techniques

use the load current to predict the load current in the future. The load current could easily

be added to the proposed controller in this work. The feedforward signal would not be

the line currents but instead the difference in line currents. The addition of a load current

feedforward signal will be presented in the next section.

Figure 1.3: Addition of load current as a feedforward signal

There are two widely used techniques for generating the PWM gating patterns:

sinusoidal PWM, and space vector modulation. Many of the control techniques that

operate solely in the rotating reference frame use space vector modulation. Space vector

modulation utilizes the dc bus voltage better than sinusoidal P W M if a harmonic injection

technique is not used for sinusoidal PWM. Sinusoidal PWM generates the gating

patterns by comparing the desired voltage waveform to a high frequency carrier

waveform as described earlier. A balanced three-phase set of voltages is represented in

the stationary reference frame by a space vector Vnf of constant magnitude and rotating

with angular speed © as shown in Figure 1.4. The reference frame is split into six sectors

by six vectors corresponding to six operating states of the inverter to form a hexagon.

Two additional null-states are defined to bring the total number of operating states to

eight. As an example, state Vx - (1,0,0) corresponds to switches swl, sw4, and sw6 on

6

and the others off in Figure 1.1. In one switching period, the inverter passes through four

operating states including two active states and two null states in a set sequence that

replicates Vref. The transition between states is accomplished such that only one inverter

leg is switched at a time. The magnitude and argument of Vref determines the times that

the inverter is in each state. The two adjacent vectors that form the sector that Vref resides

in determines the two active operating states. A more complete description of state space

modulation can be found in [4].

V* =(0,1,0) = (1.1,0)

P«=<P.U)

Pi = 0.0.0)

^ = (0.0.1) ?i = CUU)

Figure 1.4: Space vector modulation

Controllers for three-phase UPS systems are typically implemented by either a

microcontroller or a digital signal processor (DSP). As a result, many of the developed

controllers utilize a digital control technique. The techniques range from relatively

simple techniques such as deadbeat control [5] to elaborate techniques such as adaptive

fuzzy control [6]. Control designers have also proposed sliding-mode controllers [7] and

robust controllers [8]. All of these controllers are used to minimize the distortion of the

output line voltages with highly non-linear loads.

7

1.3 Proposed New Control Technique

The new technique is based on the requirement of undistorted line voltages. It is

not necessary to have undistorted phase voltages. In fact, if the third harmonic injection

technique is used to increase the available output line voltage for a given dc bus voltage,

then the phase voltages are quite distorted. The output load is configured as a three-wire

system. This means that the outputs of the inverter are intrinsically coupled together.

This is different from the four-wire case where each phase is decoupled due to the neutral

wire. Since the output phase voltages are coupled together, the choice for the voltage

control variables is the line voltages instead of the phase voltages. As a result, the inner

current loops are differences of inductor currents instead of the actual currents. The

controller structure is similar to that used by ac- dc and single-phase inverters. An outer

voltage control loop provides a current reference for the inner current loop. The output of

the inner current loop is the desired duty-cycle. This control structure has been

extensively used in industry and is well analyzed [9]. For this application the general

structure does not change. The differences lie in the control variables and the model of

the plant. It is only necessary to control two line voltages with a common reference

phase. For this work the line voltages were chosen to be Vab and Vcb. In this case the

reference phase is phase B. The controller has two voltage loops feeding two current

loops. The structure of the complete system is given in Figure 1.5 below.

Figure 1.5: Basic system structure

8

Notice that the duty cycle for phase B is the negated sum of phase A and C if a

third harmonic is not injected. This technique only requires four sensors if Hall-effect

type sensors are used for the current measurement since the Hall-effect sensors can

measure differential currents. If shunt resistors are used for the current sensors then three

shunt resistors are required, one for each phase, since shunt resistors can only measure

absolute currents. It was found, in simulation, that if only two currents say i a and ib were

measured and i c was derived by setting the sum of the currents to zero, then the results

were not so good due to the non̂ -zero sum of filter capacitor currents that can occur when

the output voltages are not perfectly balanced. The currents do not sum to zero due to the

connection of the capacitor neutral to the dc bus. If the capacitors are not tied to the dc

bus, then the sum of the inductor currents is zero. In this case, only two of the phase

currents need to be measured and the third can be derived from the others.

One distinct advantage that this scheme has over many of the other techniques is

that it can be implemented in either analog or digital. The controller bandwidth can be

improved by using an analog controller if the performance is not satisfactory with a

digital controller.

If third harmonic injection is required then the modification to the control

structure is minimal. The third harmonic is added to the calculated duty-cycles from the

current loop controller. The voltage references then are changed to reflect the desired

output line voltage magnitudes as shown in Figure 1.6.

9

Figure 1.6: Basic system structure with third harmonic injection

The load currents can be used as a feedforward signal to improve the dynamic

performance of the controller as described in the previous section. The modification of

the controller structure, as shown in Figure 1.7, is minimal. Measuring the load current

requires the addition of two extra current sensors. This controller configuration is not

studied in this work.

Figure 1.7: Basic System structure with the addition of load current feedforward

10

1.4 Outline of the Thesis

The next chapter deals with the analysis of the controller in terms of plant

modeling and stability analysis for the current control loops and the voltage control loops.

Chapter 3 shows the development of a simulation using PSIM. The simulation

models the actual implemented system as closely as possible. Simulation results are

presented and discussed for some typical cases.

The experimental setup is discussed in Chapter 4. The physical details of the

power circuit are presented including the design of the filter inductors. The controller is

implemented using a digital signal processor (DSP). The DSP used in the setup is

described in this chapter indicating the features unique to the chosen processor. The

algorithm used for the controller is detailed with the help of flowcharts. Finally, the

interface circuitry between the DSP and the power circuit is described.

Chapter 5 shows some results obtained with the experimental apparatus. The

differences between the simulation and experimental results are discussed.

Concluding remarks are made in Chapter 6. The logical continuation of the work

associated with the proposed controller is also mentioned in Chapter 6.

11

)

Chapter 2

Analysis of the New Control Technique

This chapter presents the analysis of the proposed control technique. Firstly, the

small signal time averaged model of the system is derived. This technique has been used

extensively to describe the plant of power electronic circuits. Once the plant model is

obtained then the coupled inner current loop equations can be derived. The type of

controller to be used and suitable controller values are obtained with the use of Bode

plots. The coupled outer voltage loop equations are lastly derived. As with the current

loops, Bode plots are used to obtain a suitable controller.

2.1 Small Signal Time Averaged Plant Model

As described in 1.1, the UPS circuit has the following structure as given by Figure

2:1.

V d c / 2 &> Hfe Hfe L

JTYY\

S w l Sw3 Sw5 Rc

L VYYY\

R A/vVi

AAM Rc R

L JTYY\

AA/V

V d c / 2

Sw2 Sw4 Sw6

Rc

Figure 2.1: UPS circuit to be controlled

12

The output load is assumed to be balanced. Furthermore, the load is assumed to

be resistive for the analysis. The expressions derived for the rest of this chapter assume

these two conditions. For loads which are non-resistive but are balanced, the resistance

can be replaced by a general impedance. Unbalanced loads are much more difficult to

deal with but the general approach will be mentioned below.

Since each phase is identical, it is only necessary to consider one inverter leg at a

time. The circuit can not be completely decoupled, however, because the instantaneous

sum of the phase voltages is not assumed to be zero. As a result, the neutral voltage, vN,

of the load is not at the ground potential. This accounts for the coupled nature of the

three wire configuration. If a fourth wire was used to connect the ground of the inverter

with the load neutral then each phase can be completely decoupled.

Note that the resistance R c is the ESR of the filter capacitor. The other

components are considered to be ideal. The deadtime required by the switches is

assumed to be zero for the controller analysis. The effect due to the deadtime is a

disturbance in the system which must be minimized.

If the inverter leg containing switches Swl and Sw2 is considered then two states

can be derived. The first state corresponds to Swl is on and Sw2 is off and the other state

to Swl is off and Sw2 is on.

State 1:

V d c / 2

Vx R Vj

1 V W > c R c

Figure 2.2: Swl is on and Sw2 is off

13

From the circuit corresponding to statel, two differential equations can be written:

Vdc TdiL ... vy =L— (4)

2 x dt

^ C ^ + Z ^ ^ ^ + CO + ̂ -A-^^ (5) c dt L R R dt R dt

State 2:

i L L vx R V N -^-nmr\—^

—I— r^i

Vdc/2 (T Rc

Figure 2.3: Swl is off and Sw2 is on

Equation 5 remains the same for state 2. Equation 6 has the same form and is

given by:

Vdc T di, vy=L— (6)

2 x dt

Now equations 4 and 6 can be time averaged. Equation 5 is the same for both

states so it does not need to be time averaged. Equation 4 is multiplied by the duty ratio

14

Sx and Equation 6 is multiplied by 1 - Sx,

obtain the time averaged equation given by:

The two equations are then added together to

_ , Vdc . di, , . SxVdc- — -vx=L-±- (7)

Equations 5 and 7 now form the time averaged plant for one phase. A small

signal perturbation is then applied to Equations 5 and 7 i.e.

sx = sx

vx =vx

VN = VN

h =h

Equations 5 and 7 now become:

SxVdc-vx=L^- (8) dt

^ c 4 + r L = ^ z ^ + C ( i + ^ . ) ^ - ^ ^ ( 9 )

* dt L R R dt R dt

Equations 8 and 9 are almost in a form which is usable for Bode analysis. What

remains is to put the equations in the Laplace domain. The differential operators are

replaced by the Laplace variable s to obtain the frequency domain equations given by:

8xVdc-vx =SLTL (10)

15

\ (1 + sRcC) = ̂ ( 1 + sC(R + RC )) - ^-(1 + sRcC) (11) K K

The right most term in Equation 11 is the same for every phase since the load is

assumed to be balanced. This coupling term can be replaced by the other terms in

another phase to obtain a difference in inductor currents and phase voltages. The x and

inductor current designator L in Equations 10 and 11 is replaced by A for phase A and B

for phase B to obtain three equations:

SAVdc-vA=sLiA (12)

8BVdc-vB=sLiB (13)

(fA-7b)(\ + SRCC)=(VA V B \ \ + SC(R + RC)) (14) K

Finally vA and vB from Equations 12 and 13 can be substituted into Equation 14

to obtain a relationship between the difference in duty cycles and the difference in

inductor currents for phases A and B.

^ s C ( R , R c ) ) ~ s2LC(R + Rc) + s(L + RRcC) + R a

Since the load is balanced, the transfer function relating phases C and B is

identical to Equation 15. The plant model is now complete. Figure 2:4 shows a block

diagram illustrating the model.

16

Vdc(l+sC(R + Rc)) R(\ + sCRc) s*LC(R +Rc)+s(L+RRcC)+R \ \ + sC(R+Rc)

Vdc(l + sC(R + Rc)) s2LC(R +RC) +s(L +RRCC) +R

Vdc(i + sC(R + Rc)) A k R(\ + sCRc) s3LC(R +RC) +s(L+RRcC) + R \ + sC(R+Rc)

Figure 2.4: Small signal time averaged plant model

2.1.1 Unbalanced Loads

If the load is not balanced then equation 14 will no longer be valid. Dealing with

unbalanced loads is more difficult. A relationship for vN must be found. Since the sum

of the currents in the load equals zero, the following relationship relates the phase

voltages to the load neutral voltage:

V. v„ vr ~ , \ 1 1 N

f-T r-J ^7 N \ rr r» ry J (16)

ZA, ZB, and Zc are the impedances of phases A, B, and C of the load. vN from

Equation 16 can be substituted into Equation 11. Expressions for vA, vB, and v c can

also be substituted into Equation 11. These expressions are identical to Equations 12 and

13. The resultant equation relates iA to 8A, 8B, 8C, iB, and ic. There are, therefore,

fifteen different transfer functions required to relate iA, iB, and ic to 8A, 8B, and 8C in

comparison to the three for the balanced case. The relationship between the phase

17

voltages and inductor currents are similarly more complicated. For this reason the

balanced case was studied. The following analysis given in the next two sections for the .

inductor current control loops and the voltage control loops is similar for the unbalanced

case except that the plant model is more complicated.

2.1.2 Floating Filter Capacitor Neutral

The neutral of the filter capacitors, as shown in Figure 2.1, is tied to the dc bus.

As mentioned in Chapter 1, the capacitors are typically left floating. When the capacitor

neutral, v„, is floating, Equation 4 remains the same and Equation 5 becomes:

R c C ^ + i L = ^ ^ + C(l + ^ ) ^ - C ^ - C ^ ^ - (17) c dt L R R dt dt R dt

If a small signal perturbation is applied and the differential operators are replaced

by the Laplace variable s, then Equation 17 becomes:

7L(\ + SRcC) = ̂ (\ + sC(R + Rc))-sCvtt-^-(l + sRcC) (18) K K

Equation 18 is almost identical to Equation 11 except for the term sCvn. As with

the rightmost term, sCvn is a common term for all of the phases. Equation 14, therefore,

still holds true for this case. The plant model, as shown in Figure 2.4, is valid for a

floating filter capacitor neutral.

2.2 Current Control Loop Analysis

The inner current loops as shown in Figure 1.3 are analyzed in this section. As

can be seen in the figure, there are two current control loops each providing a duty-cycle

18

for phase A or C. The duty-cycle for phase B is the negated sum of the duty-cycles from

phases A and C. The plant model derived in the previous section combined with the two

current loops is shown below in Figure 2.5. Since the controller is implemented in the

discrete-time domain and the plant is in the continuous-time domain, analog-to-digital

(A/D) and digital-to-analog (D/A) converters need to be used to convert the signals from

one domain to the other. The samplers in Figure 2.5 represent the A/D converters and the

zero-order hold (ZOH) blocks represent the D/A converters. The blocks after the Z O H

blocks, in the figure, represent computational time delays. The computational time

delays exists because the calculated duty-cycles can only be updated at certain times

during the switching period. For the case of a symmetrical triangular carrier waveform,

the duty-cycles can be updated at the beginning of the cycle and at the middle of the

cycle. As a result, the smallest possible computational time delay is half the switching

period.

Figure 2.5: Current Control loops showing digital control elements

The controller is designed in the continuous-time domain. The dynamics

associated with the D/A converters, and the computation time delays need to be

accounted for because they cause phase delays [10]. The A/D converters do not have any

19

dynamics associated with them in the continuous-time domain. Since the discrete-time

controller G1 (z) is designed in the continuous-time domain, but is implemented in the

discrete-time domain, the controller needs to be converted from the continuous-time

domain into the discrete-time domain. The conversion is presented in Chapter 4.

The dynamics associated with the Z O H blocks and the computational delay

blocks can be lumped with the controllers by block manipulation. The reduced block

diagram, as shown in Figure 2.6, is entirely in the continuous-time domain. The transfer

function blockG, is given by Equation 15. The transfer blockG2 represents the

controller and the dynamics associated with digital control. The transfer function of G 2

is given later in this section.

o2 o2

J o2 J

) o2

Figure 2.6: Current closed loop block diagram

In Figure 2.6, iAB and iCB are the difference in the inductor currents of phases A

and B and the difference in inductor currents of phases C and B respectively. Similarly,

iABref and iCBref are the reference currents for the corresponding difference in inductor

currents.

20

The first step in the current loop controller design is to derive the loop transfer

functions of the current closed loop system. This can be accomplished by finding the

closed loop transfer functions and putting the resultant expressions in a form that the loop

transfer functions can be easily obtained. In general this two input, two output system

would have four loop transfer functions - the two direct transfer functions and two cross

transfer functions. Since the plant is symmetrical, the two direct transfer functions and

the two cross transfer functions are equal.

The closed loop transfer functions for the current loop are given by Equation 19

below:

i - 2^G2,+ 3GX G 2 . GXG2 n g .

~ 1 + 4 G G , + 3 G 2 G 2 A B n f 1 + 4 G G 2 + 3G,2G2

2 W 1 '

This now should be put in a form so that the two loop equations can be found. If

Equation 19 is put into the form then the loop equation is GH. By algebraic

manipulation Equation 19 can be written as:

2G,G 2 +3G, 2 G 2

2 G.G 2 1 + 2G,G 2 , * + 4G,G 2 ( 2 0 )

'AB - >>r r ± i r 2 r 2 A B r e f GG CBref K ' 2GxG2+3GlG2 1+ ° i u * (3G,G2) 1 + 2G,G 2 1 + 4G,G 2

The two loop equations can be now taken directly from Equation 20. The plant is

a linear time invariant system. As a result, each loop equation can be analyzed separately

for stability margins. By the superposition theorem if both of the loop equations are

stable then the entire system is stable. As mentioned above the stability of the closed-

loop system was analyzed by using bode plots. It is desired, by common practice, that

the phase margin should be at least 45 degrees and the gain margin should be at least 8

dB.

21

The loop unity gain cross-over frequency was chosen based on common practice.

It is usually chosen to as high as possible but low enough to minimize the effect of noise.

Some discussion on this can found in [11]. The unity gain cross-over frequency should

be less than 176th of the switching frequency for the current loops. Since the switching

frequency was chosen to be 18 kHz this implies that the unity gain cross-over frequency

should be less than 3 kHz. For analog controllers this is easily obtained but for digital

controllers using small signal control this is usually not the limiting factor. The limiting

factor is due to the zero-order hold and computational delays.

There is an unfortunate problem with using small signal control and that is due to

the model's dependence on the output load. It is very difficult, theoretically, to have a

system which has the above stability margins for the whole range of loads. The range of

the loads is typically from no-load to full load. In fact, for light or no loads, it is

generally impossible to have a good full load controller bandwidth and be stable at all.

The real system is generally found to be stable even though theory would suggest

otherwise. If one is overly concerned about the stability for light or no loads then gain

scheduling could be an option. This would require the calculation of the rms current in

the inductors. This is relatively simple to implement in a digital controller. It can be

done with an analog controller but the effort would be considerably higher compared to a

digital controller.

The analysis does not consider some of the practical limitations of the

implementation of the controller. This limitations include finite data word length and

quantization error. These issues will addressed in Chapters 3 and 4.

The analysis also assumes that the sensor gains are one. In actuality, the sensor

gains are far from unity. The sensor gains appear in the feedback paths of Figure 2.6. In

order to maintain the same closed-loop transfer functions given in Equation 19, the

reference currents are multiplied by the sensor gains and the controller gains are divided

by the sensor gains. By adding the sensor gains to the feedback paths, the closed-loop

22

transfer functions remain unchanged. The sensor gains are, therefore, included in the

feedback paths.

The controller for the current loops was designed with the use of Mathcad.

Mathcad was used instead of Matlab because time delays can not be dealt with easily in

Matlab. A PI controller was chosen since most controller designs for power electronic

plants use PI type structures. The controller was analyzed for a mid range load to

guarantee the widest range of the system being very stable with a good full load

bandwidth. The bode plots are generated using Mathcad.

The current controller was tuned mostly by trial and error. Generally, the

proportional gain was first increased until the desired unity gain cross-over frequency

was obtained. The integral gain was then increased until the minimum acceptable phase

margin is reached. Once the initial controller values are obtained, the controller is fine

tuned to give the magnitude and phase responses desirable shapes.

The transfer function of the block G2 is given by:

Y -— (\ - e M G2=K(\ + ±-)e 2 ^ - ^ (21)

The K in Equation 21 is the proportional gain of the PI controller. Kt is the

integral gain of the PI controller. The leftmost exponential term represents the

computational delay term. T in the equation is the switching period. The rightmost term

is the normalized zero order hold term. Note that the computational delay and the zero

order hold delay use half of the switching period. The implementation is, therefore,

sampling the data at twice the switching frequency and updating the duty-cycles twice

per switching period.

23

The bode plots below use the plant parameters specified in Chapter 1. Iloopd

represents the loop equation for the direct closed loop transfer function iAB I iABnf. Iloopx

represents the loop equation for the cross closed loop transfer function iAB liCBnf. The

magnitude bode plot is given by Figure 2.7 and its associated phase plot is given by

Figure 2.8. The margins and the unity gain cross-over frequencies for two current

controllers is tabulated in Table 2.1. Notice that only the proportional gain is changed in

the controller - the integral gain remains the same for both control designs.

Phase Margin Gain Margin Cross-over Frequency

Iloopd K = 0.055 Kj = 1000 80 degrees 10.8 dB 1750 Hz

K = 0.065 Kj =1000 76 degrees 9.2 dB 1970 Hz

Iloopx K = 0.055 Kj = 1000 116 degrees 9.8 dB 115 Hz

K = 0.065 Kj = 1000 105 degrees 8.6 dB 150 Hz

Table 2.1: Results from current controller design

Notice that the phase and gain margins for the direct loop transfer function are

very conservative. This is due to the less than ideal experimental set-up. Chapters 3 and

5 will discuss the reason for choosing such conservative margins. A better set-up would

allow the margins to be smaller and, as a result, the unity cross-over frequency and

bandwidth would be higher. The cross loop transfer function unity gain cross-over

frequency is quite small for the slower controller but note that, as shown in Figure 2.7,

the magnitude response approaches quite close to zero dB at around 850 Hz. For the

faster controller, the magnitude response crosses over the 0 dB line at 150 Hz but remains

within 2 dB of unity gain until the magnitude approaches 0.12 dB at 920 Hz. Due to

plant parameter variations, the unity gain cross-over frequency could be much higher

than the listed value in Table 2.1. The lower cross-over frequency indicates that the

24

difference in inductor currents iAB will response more strongly to the direct current

reference iABref compared to the cross current reference iCBref.

Magnitude (dB)

100

50

I l o o p d

I l o o p x

-so

-100 10 100

f (Hz) 1*10-

Figure 2.7: Magnitude plot for R = 15Q, K = 0.055, K, = 1000

1-10

Phase (dee)

300

100

I l o o p d

I l o o p x

-100

-aoo

N N

10 100 f (Hz)

rio 1-10

Figure 2.8: Phase plot for R = \5Q,K = 0.055, K, = 1000

25

2.3 Voltage Control Loop Analysis

The closed-loop current loops now form the plant for the voltage loop. The

dynamics associated with using discrete-time control have already been accounted for in

the current controller design since the A/D converters of the voltage loops do not add any

additional dynamics in the continuous-time domain. Figure 2.9 shows the structure used

to analyze the voltage control loops.

Figure 2.9: Voltage control loop block diagram

In Figure 2.9, Hx represents the leftmost transfer function relating iAB and iABref

given in Equation 19. H2 represents the rightmost transfer function relating iAB and

iCBref given in Equation 19. H3 relates the difference in inductor currents with the

corresponding line voltage as given in Equation 14. Finally, / / 4 is the voltage loop

controller.

26

As with the current loop, the voltage closed loop transfer functions can be found

and are shown in Equation 22:

_ HxH3H4+Hl

2H3H4 -H2H3H4 AB ~ '

l + 2HxH3H4 +H,2HIHI -H\H\H\

H ^ H * -VCBnf (22) 1 + 2H,HM. + H^HlHl -HlHlHl CBref

Equation 22 can now be put in a form so that the voltage loop equations can be

extracted. After algebraic manipulation, Equation 22 now becomes:

HXH 3H 4 + H XH\H2 — H2H y I + #l#3^4 v ,

A B rr TT jj , TJ2 TJ2TJ2 TJ2TT2TJ2 ABref

H2H3H4

\ + 2HxH3H4+Hx

2HlHl TJ TT TJ " CBref

1 + 2 3 4

2 . . (~H2H3H4) 1 + 2HXH3H4+H?H3

2H2

VcBref (23)

The unity gain cross-over frequency for the voltage loops should be significantly

lower than the unity gain cross-over frequency for the current loops. This will allow the

current loop to track the reference current provided by the voltage loop with good

accuracy. One consequence of the voltage loop being slower than the current loop is the

current loop can be approximated by either a gain block or a first order system. This

approximation was typically made when the responses were developed by hand. With

27

the use of software like Mathcad or Matlab the approximation no longer needs to be

made.

As with the current controllers, the voltage sensor gains are equal to one in Figure

2.9. The gains due to the voltage sensors are handled in the same way as the current

sensor gains except that, in this case, the voltage controller gains must also be multiplied

by the current sensor gains.

The voltage loop controllers are designed with the same iterative method as the

current loop controllers. In this case, however, the gain margin with a PI controller was

found to be insufficient. A modified PI controller was chosen to increase the gain

margin. The modified PI controller has better noise rejection because its magnitude

response rolls off at -20 dB/decade for high frequencies while the PI controller has a flat

magnitude response for high frequencies. The problem with modified PI controller is that

the extra pole required causes more phase delay. For this reason, a modified PI controller

was not used for the current loops. Modified PI controllers are typically used when the

gain margin obtained by a PI controller is not sufficient or high frequency noise is a

problem. The controller block has the following form:

HA = KpQ + £±)-±— (24) S 1 + SKy

Kp and KJ2 are the proportional gain and integral gain terms respectively as in

the PI controller case. \IKV is the corner frequency for the additional pole used to

attenuate high frequency noise.

The controller values for the current loop shown above were used for the voltage

loop Bode analysis. Vloopd represents the loop response for the direct closed loop

transfer function VAB IVABref. Vloopx represents the loop response for the cross closed

loop transfer function VAB IVCBref. Figure 2.10 shows the magnitude responses for the

28

loop equations and Figure 2.11 shows the corresponding phase plots. Table 2.2 shows

the results obtained with the two different current controllers and the same voltage

controller.

Phase Margin Gain Margin Cross-over Frequency

V l o o p d

K =0.055 53 degrees 10 dB 600 Hz

K = 0.065 52 degrees 10.3 dB 630 Hz

Vloopx

AT =0.055 infinite 25 dB N/A

K =0.065 infinite 26 dB N/A

Table 2.2: Voltage Controller Results for Kp =0.3116, Kn =1000, Kv = 7^5-

The unity gain cross over frequency has no meaning in the cross loop transfer

function because the magnitude plot never crosses the 0 dB axis. As a result, the phase

margin is infinite. Notice that the phase and gain margins for the direct loop transfer

function are much closer to the recommended values given above. As noted above, the

noise immunity is quite good for the voltage loop due to the extra pole of the modified PI

controller. This is clearly seen in the magnitude response shown in Figure 2.10. The

cross coupling for the voltage loop is very small as indicated by its magnitude response.

The effect of the voltage reference VCBref is very small compared to the effect of the

direct voltage reference VABref. Most of the coupling in this system comes from the fact

that each controller contributes equally to the derivation of the phase B duty-cycle.

29

Phase 200 I

100

Vloopd

Vloopx

-100r

-aooL

100

i (Hz) no 1-10'

Figure 2.11: Phase Plot for AT,, = 0.3116, Kn = 1000, Ky = _ i

1500

30

Chapter 3

Simulation Using PSIM

Chapter 3 details the simulations that were performed to verify the operation of the

proposed controller. The actual system was modeled as accurately as possible to help

explain the experimental results.

The first section of this chapter describes the implementation in PSIM of the

modeled circuit. The circuit blocks in PSIM that model the functional blocks of the DSP

are also described in this section. The physical structure of the DSP will be discussed in

further detail in Chapter 4. Waveforms produced from the simulations and the physical

significance of the results are presented in the second section of the chapter.

3.1 Circuit Description

The simulated circuit can be split into two functional blocks: the power circuit, as

shown in Figure 3.1, and the DSP block as shown in Figures 3.2 and 3.3. The structure of

the power block has already been described earlier so its description will not be repeated

here. The DSP block can be further split into two sections: the controller block and the

deadtime insertion block. The controller block computes the duty cycles for the three

phases and delays the generated signals by half of the switching period. The measured

variables and the calculated reference voltages are held by zero-order hold blocks. The

state of the switches in an inverter leg are controlled by the switches' gate voltages. The

deadtime insertion block inserts a 2 us deadtime between the falling edge of one gate

signal and the rising edge of the other gate signal. This ensures that the dc bus will not be

short-circuited. The. value of the deadtime corresponds to the minimum value specified by

the manufacturer of the switches that were used in the experimental setup.

31

ri fe

H

i f e

H

ug\ I/YYY\

Controller Deadtime Insertion

-i/YYYV.

6

• ^ A A / V - i

- A A / v -

I—wvJ

Figure 3.1: Power Circuit with Control Connections

The hardware deadtime insertion block in the DSP modifies the gating signals

symmetrically. The same method is used in the deadtime insertion block of the simulation

circuit. Details of the hardware deadtime block are included in Chapter 4.

The implementation of the PI and modified PI controllers in the simulation is

almost identical to their implementation in the DSP. The structures of the discretized

controllers are identical but the finite word length of the internal signals in the DSP is not

modeled in the simulation. Calculations in the simulation are performed with floating

point arithmetic and very high precision. The DSP performs 16-bit arithmetic with a 40-

bit accumulator in the multiply and accumulate (MAC) block of the DSP. The finite word

32

length in the DSP cause errors in the calculated duty-cycles which tend to destabilize the

controllers

Quantization effects are included in the simulation. The largest quantization error

is in the duty-cycles. The precision of the duty-cycles is only approximately 9 XA bits. The

simulation uses 9 bits of precision for the duty-cycles. The A/D in the DSP has 12 bits of

precision. Quantization errors tend to destabilize the controller. The quantization of the

duty-cycles is included in the deadtime insertion block as shown in Figure 3.2.

The voltage and current sensors are assumed to be ideal i.e. the sensors have

infinite bandwidth and no phase distortion. Measurement noise is added to the measured

currents and voltages by using a random voltage block from PSIM. Figure 3.3 does not

show the addition of measurement noise. The noisy measured signal is held by a ZOH

block and then quantized.

Figure 3.2: Deadtime Insertion Block

33

34

3.2 Simulation Results and Discussion

Results are presented for two cases. In the first case, the measured currents and

voltages are noiseless. Noise is added, in the second case, to the measured currents and

voltages to study the effect of noise on the generated duty-cycles. A time step of 0.1 p.s

was used for all of the simulations. The power circuit in both of the simulations presented

in this section start with zero initial conditions and at time t = 0. The results presented,

therefore, show the start-up transients produced with the controller.

Case 1: No Measurement Noise

This case is used to demonstrate the action produced by the controller to the

deadtime disturbance. Results obtained with the controller are presented together with

open loop results. The results obtained with two different current controller proportional

gains and the same voltage controllers are also presented to study the effect of the gain on

the output line voltages. The gains for the controllers are given in the previous chapter.

The per-phase load is 15 fi. The line voltages and VCB are shown in Figures 3.4 and

3.5. Figure 3.6 shows the generated duty-cycles for the current controller with

proportional gain Kp = 0.065. The duty-cycles range from -1 to +1. A duty-cycle of+1

corresponds to the top switch being on for the entire switching period while a duty-cycle

of-1 corresponds to the top switch being off for the entire switching period.

35

S2.Vl«(lb V l b Vlb_1

with controller jj j

reference

Figure 3.4: Simulated line voltage Vab with the controller and for open loop

Figure 3.5: Simulated line voltage Vcb with the controller and for open loop

36

S2.dj S2.db S2.dc

0.00 10X10 20.00 30.00 40.00 Time (m*)

Figure 3.6: Simulated duty-cycles for Kp = 0.065

Notice that in Figure 3.4 the line voltage Vab generated by the closed loop system

is considerably closer to the reference voltage than the line voltage generated by the open

loop system. The line voltage Vcb generated by the controller is too high. The waveform

for Vcb will be discussed in detail below. The disturbance created by the deadtime has

almost been eliminated with the use of the controller. The effect of the deadtime is seen in

the waveforms for line voltages produced with open loop. Distortion of the open loop

voltage waveforms is due to the deadtime disturbance. The duty-cycles, as seen in Figure

3.6, are also distorted to compensate for the deadtime disturbance. The distortion near

the peaks is primarily due to quantization errors not to the controller compensating for

deadtime.

37

1

(a) ^ ^ y c b i M ft 1 - -

/ f\ \Vab

\ (b) \ /

(a) Kp = 0.055 \ r i

(b) Kp = 0.065 -200.00

0.00 20.00 Timi (ms)

Figure 3.7: Simulated line voltages for Kp = 0.065 and Kp = 0.055

As can be seen in Figure 3.7, increasing the current controller proportional gain

forces the line voltages to become increasingly more balanced. The line voltages are more

balanced because Vcb has decreased in magnitude. The line voltage Vab is almost

identical for the two controllers. The magnitude of the line voltage Vcb has become

smaller because the phase C voltage is smaller for the higher gain controller. Notice that

in Figure 3.6, the duty-cycle for phase C is appreciably higher than the duty-cycles for

phases A and B. Since the duty-cycles for phases A and B are almost identical in

magnitude, the higher phase C duty-cycle causes Vcb to be larger in magnitude than Vab.

This is consistent with the results obtained with the experimental inverter as shown in

Chapter 5.

38

Case 2: With Measurement Noise

In this case, noise is added to the measured signals. A random number with a

peak-to-peak amplitude equal to 10% of the peak amplitude of the measured signal and no

offset is added to the measured signal. The faster current controller is used for this case.

The per phase load is 15 fi. The generated line voltages and duty-cycles are shown in

Figures 3.8 and 3.9 respectively. Figure 3.10 shows a small section of the duty-cycle for

phase A.

Vab Vob 200.00

Vcb

' " V \ Vab

// - \ \

10.00 20.00 30.00 time (ms)

Figure 3.8: Simulated line voltages Vab and Vcb produced with noisy sensors

39

-1.00 0.00 10.00 20.00

Timt (ms)

Figure 3.9: Simulated duty-cycles produced with noisy sensors

"'if 1

i j h i

i ! . .TL. . . -

fr Jl 1 :

\ -> 12.00 14.00 1800

Tim* (ms)

Figure 3.10: Small section of the duty-cycle for phase A

40

The duty-cycles generated in this case are slightly oscillatory. This is clearly seen

in the figure showing the small section of the duty cycle for phase A. As a result, the

generated line voltages have significant ripples. Notice that the ripples are concentrated

near the voltage peaks. The frequency of the oscillations is 2 - 4 kHz. The value of the

frequency is important as it is used to justify the oscillations found in the experimental

results. Since the noise in the real system is likely coloured with non-zero mean, these

simulation results are useful only to study the general effect of noise on the closed loop

system.

Measurement noise affects the performance of the controller more than the

quantization of the duty-cycles.

41

Chapter 4

Experimental UPS Design

The experimental UPS design is detailed in this chapter. The chapter is split into

three sections. The first section presents the design of the power circuit including the

AC-DC rectifier section, three-phase inverter, gate drive circuitry, and sensor circuitry.

In the second section, the architectural features of the DSP are presented. Finally, in the

last section, the developed DSP program is explained. In a few cases, such as the output

filter inductor, only the final design is presented. References are given for the design

procedure in these cases.

4.1 Description of the Power Circuit

The hardware for the power circuit and the interface between the power circuit

' and the DSP can be split into four functional blocks. Each functional block is detailed

separately.

4.1.1 A C - D C Rectifier Section

In previous chapters the dc bus has been represented by an ideal dc source. In

actuality, the dc bus is produced by rectifying an ac source and filtering the output with a

large capacitor as shown in Figure 4.1. As a result, the dc bus has a small ripple. The

magnitude of the ripple depends on the capacitance of the capacitor. Typically, the

capacitance is chosen to be 2 - 3 ^F per watt of output power. A capacitance that is too

small will result in an unacceptability large ripple. A capacitance that is too large could

result in the capacitor or the rectifier bridge destructively failing. As the capacitance

increases, the available time to charge the capacitor decreases and, as a result, the peak

charging current increases. If the peak current becomes too high then either the diode

bridge or the capacitor could fail. A three-phase bridge was used instead of a single-

phase bridge to increase the available dc bus voltage.

42

2200 uFd=

r0^ H2>

10K

z b = b > 10K

Figure 4.1: AC-DC rectifier section

A split dc bus capacitor is required for this application. The resistors across the

dc bus capacitor bank have two purposes: to discharge the capacitor bank when the power

circuit is turned off, and to balance the positive and negative voltage rails.

The three-phase voltage source is supplied by a power utility company. Isolation

is provided by a three-phase star-delta transformer. The dc bus magnitude is varied by a

three-phase variac. Figure 4.2 shows the configuration of the three-phase supply.

1 2 0 : 2 0 8 o «

V a r i a c

Figure 4.2: Isolation transformer and variac

43

4.1.2 Three Phase Inverter

The component values for the three-phase inverter were given in Chapter 1. Due

to the power requirements, insulated gate bipolar transistors (IGBT) are used for the

switches. An intelligent power module from Powerex is used for the IGBT bridge. The

power module is self-protecting provided that power is supplied to the logic circuits of

the module. The logic circuits will be briefly explained in the section on the gate driver

circuitry. The use of the power module simplifies the design of the inverter. The IGBT

switches in the module are rated for 600 V and 20 A. The part number for the module is

PM20CSJ060.

The filter inductor was designed with the aid of a simple spreadsheet as shown in

Table 4.1. There are many design procedures for inductors. A selection of design

procedures is given in [12].

Inductor Design Notes:

L 2.533 mH

u 125 Permeability

Ae 2.888 cm A 2 cross-sectional area Using 2x 77109-A7 cores

le 14.3 cm path length from Magnetics Inc.

Ipk 9.4 A peak current

Bmax 1.05 T peak flux density

N 89 turns number of turns U s e s A W G 18 Wire

Check 0.00317816

Bpk 0.926351583 T Calculated peak flux density

Table 4.1: Spreadsheet for inductor design

The inductor is made from a powdered iron core from Magnetics Inc. The cores

are stacked together to increase the effective cross-sectional area. The inductor was

designed conservatively to ensure that the magnetic core does not saturate.

44

The output filter capacitor is comprised of two 22 up electrolytic capacitors in

series. The cathodes of the capacitors are connected together. A single electrolytic

capacitor is not suitable because an electrolytic capacitor acts like a short-circuit when a

negative voltage is applied to its terminals. As a result, the capacitor can fail if the

current is sufficient. When the cathodes of two electrolytic capacitors are connected

together, a positive voltage is always seen across one of the capacitors thus the current is

limited. Unfortunately, the ESR of the series capacitors is double the ESR of the single

capacitor.

The load consists of parallel switched wire wound heater resistors connected in a

star configuration. Changing the number of parallel star connected resistors varies the

load.

4.1.3 Gate Driver Circuitry

An electrical isolation barrier is required between the DSP and the IGBT module.

Since the module only requires CMOS level voltages and small currents, only the

isolation barrier is necessary. The isolation is provided by high-speed optocouplers

HCPL 4054 from Hewlett Packard. No separate gate driver integrated chips are required.

The gate signal inputs for the IGBT module have high impedances. As a result, the gate

signals are susceptible to noise. A good layout is required to minimize the effect of

noise. The layout of the circuitry is a modified version of the suggested layout provided

by Powerex [13]. The modified layout can be found in Appendix A. Extra inverting

Schmitt triggers CD 40106BCN from Motorola are required to eliminate the noise spikes

on the gate signals. Testing showed that the IGBT module would not operate properly

without the Schmitt triggers.

The IGBT module has a separate gate driver for each of the top switches and a

single driver circuit for the bottom switches. Each circuit provides a fault output that can

be used by the controller to detect a problem with the bridge. In the implementation for

45

this work, the fault outputs were ignored. The module requires active low gate signals.

The gate driver circuitry, as shown in Figure 4.3, requires the DSP gate signals to be

active low since the Schmitt triggers invert their inputs.

The power module requires four isolated +15 Vdc power supplies to provide

power for each top switch logic circuitry and the single logic circuitry for the bottom

switches. Decoupling capacitors are also used placed near the supply pins of the IGBT

module.

4.1.4 Sensor Circuitry

The circuits for the sensors include the sensors themselves and the signal

conditioning circuits to bring the measured signals within the range of the DSP's A/D

inputs. The A/D inputs have a range of +2V to -2V.

The differential inductor currents are measured using a Hall-effect transducer

LT-25P from LEM Instruments Inc. The difference in inductor currents is obtained by

passing the phase B inductor wire through the sensors in the opposite direction than the

phase A and C inductor wires. The selected transducer has three current ranges that are

selected by the number of turns through the device. In this case, two turns are used to

maximize the precision of the measurement while guaranteeing the differential inductor

current lies within the measurement range. The gain of the sensor is 0.05.

The supply of the sensor is +5 Vdc. The output from the sensor is 2.5 +/- 2.0 V

where 2.5 V corresponds to zero current. As a result, the output must be shifted down by

2.5 V to lie within the range of the A/D inputs. Figure 4.4 shows an op-amp circuit that

shifts the input appropriately.

46

Vupc

Figure 4 . 3 : Gate drive circuitry

4 7

Vin lk -AA/V

+5V Voff

^181 LT1009CZ

18k, 0.1%

Figure 4.4: Level-shifting circuit for the current sensor

LT1009CZ is a precision +2.5V reference from Linear Technology.

The line voltages are measured using a precision isolation amplifier AD210 from

Analog Devices. Two voltage divisions are made to bring the signal within the range of

the A/D input as shown in Figure 4.5. The first division is done by a voltage divider.

The second division is due to the amplifier of the sensor. The overall gain of the voltage

sensor is 0.01147. The output of the sensor is inverted so the measured value needs to be

inverted in the DSP.

The isolation amplifier provides +/-15 Vdc reference voltages on the input side of

the device. The voltage from phase B is connected to the Icom pin in the input stage of

the device. If the reference voltages are connected to phase B via identical resistors, then

a line voltage measurement can be made.

48

12 I K

Vb<>

Out

A l l r e s i s tors are 1%

Figure 4.5: Voltage sensor circuit

The layout of the sensor circuits is critical since the relatively small currents in the

DSP side of the isolation barrier are easily affected by noise. As mentioned in Chapter 3,

the performance of the controller is strongly affected by the level of the noise in the

measured signals. There are no anti-aliasing filters on the inputs of the A/D except for

second-order low pass filters with a cut-off frequency of approximately 50 kHz. These

filters are located on the development board of the DSP. For this application, the

dynamics of the filters can be ignored. Anti-alaising filters are not required because the

output LC filters have already filtered the switching waveforms produced by the IGBT

bridge.

4.2 Introduction to the DSP and its Features

A DSP from Analog Devices Inc. was chosen to implement the digital controller.

The ADMC401 DSP is intended for use in motor controllers. As a result, the DSP has

hardware dedicated to pulse-width modulation (PWM) generation and deadtime insertion.

The user of the DSP can specify the switching frequency, required deadtime, and the

49

duty-cycle for each phase. The DSP automatically generates the six gate signals required

for the IGBT bridge.

A development kit was used in this work. The kit contains a development board,

which includes the peripheral hardware required by the DSP, and a connector board.

This section is split into several subsections that match the functional blocks of

the DSP. The assembly language of the DSP will be presented in the next section.

4.2.1 DSP Core

The ADMC401 is a 26 MIPS (million instructions per second) fixed-point DSP.

The arithmetic units of the DSP include a 16-bit arithmetic and logic unit (ALU), single

cycle 16-bit X 16-bit multiply and accumulate into a 40-bit accumulator (MAC), and a

32-bit logical and arithmetic shifter. The 40-bit accumulator is of particular interest

because many MAC calculations, such as in filtering, can overflow a 32-bit accumulator.

The DSP core features two independent data address generators. If data is stored

in the program memory space, then this allows access to both the program and data

memories for data in a single instruction.

The DSP core supports multifunction instructions. One example of a

multifunction instruction is a computation with memory read. The multifunction

capability of the DSP allows algorithms such as filtering to be processed very quickly.

The core has hardware that supports zero overhead looping. Once the number of

iterations is set with a single instruction, a block of instructions can be processed many

times with no additional overhead. Again this facilitates filtering algorithms since they

involve MAC instructions in a loop.

50

In general, the ADMC401 DSP core is very efficient at processing repetitive type

algorithms such as filtering. Even though the controller in this work does not require any

filtering, the features of the DSP core allow the PI and modified PI algorithms to be

completed very efficiently.

4.2.2 Analog-to-Digital Unit

The A/D unit of the DSP is very useful for digital controller applications. The

A/D unit can process 8 channels of data in under 2 us with 12-bits of precision. The unit

has two banks that allow two channels to be simultaneously sampled at a time. The input

channels can also be sequentially sampled. The data is processed by a 12-bit pipeline

flash analog-to-digital converter (ADC). The A/D unit produces an end-of-conversion

interrupt when the data is valid. The start-of-conversion can be coordinated with a

PWMSYNC pulse generated in the three-phase timing unit.

The inputs to the A/D unit range from OV to +4V. The DSP development board

has additional circuitry that shifts the -2V to +2V input from the connectorboard to the

OV to +4V range required by the DSP. The output from the A/D unit is a signed

fractional number i.e. ranges from -1 to 1. The gain introduced by the A/D unit is,

therefore, 0.5. The gains of the LEM sensor and isolated amplifier must be multiplied by

the gain of the A/D unit to obtain the total current and voltage sensor gains.

4.2.3 The P W M Controller

The PWM controller block of the DSP is comprised of four blocks: a 16-bit three-

phase PWM timing unit, output control unit, gate drive unit, and PWM shutdown

controller.

The three-phase PWM timing unit is the core of the PWM controller. The unit

produces three pairs of complimentary gate signals based on the values in four

51

configuration resisters: PWMTM, PWMDT, PWMPD, and PWMSYNCWT. A bit in a

fifth register, MODECTRL determines whether the duty-cycles are updated once (single-

update mode) or twice (double-update mode) per switching period. The PWMCHA,

PWMCHB, and PWMCHC registers control the duty-cycles to be produced.

The PWMTM register sets the PWM switching frequency. The value stored in

the register equals the number of clock cycles for half of the switching period. For every

clock cycle, the duty-cycles are compared to a timer with a period equal to the value in

the PWMTM register. If the duty-cycle equals the current timer value then a switching

transition occurs. The timer starts with the value in the PWMTM register and starts to

count down. When the timer has reached zero, then the timer starts counting up until the

value in the PWMTM register is reached. The first switching transition occurs while the

timer is counting down and the second while the timer is counting up. The resolution of

the duty-cycles is, therefore, limited by the switching frequency. The number of discrete

values that the duty-cycles can take in the single-update mode is equal to the value in the

PWMTM register while in the double-update mode the number of values is equal to

double the value in the register. The duty-cycles are quantized and this leads to errors as

mentioned in Chapter 3.

The PWMDT register holds half of the value of the deadtime to be inserted into

the gating patterns. The deadtime is added to both the high-side and the complimentary

low-side gate signals. The deadtime is, therefore, inserted symmetrically into the gating

patterns. As a result, the switching transitions are modified due to the addition of the

deadtime. Figure 4.6 shows an example of the addition of deadtime for the double-

update mode.

Pulse-widths are rejected if they are smaller than the value specified in the

PWMPD register by the PWM timing unit.

52

AH

AL

PWM SYNC

,<r- PWMCHA1—— PWMCHA2-

2 x PWMDT —*

Figure 4.6: Deadtime insertion into duty-cycle for phase A. Signals are active low

The PWMSYNC WT register specifies the width of the PWMSYNC pulse that is

generated by the three-phase timing unit. This pulse is generated at the switching

frequency in the single-update mode and at double the switching frequency for double-

update mode. The PWMSYNC pulse is used to synchronize the PWM controller. The

signal is also available externally so other devices can be synchronized with the pulse.

As mentioned earlier, the PWMSYNC pulse can be used to signal a start-of-conversion

for the A/D unit of the DSP.

The output control unit is controlled by the PWMSEG register. Setting the

appropriate bits of the PWMSEG register can individually enable each pair of gate

signals. The register also has bits that enable a crossover feature and enable the control

of an electronically commutated motor. These features were not used for this work.

The gate drive unit is associated with the PWMGATE register. Two optional

features are available with the use of the PWMGATE register: high frequency chopping

and switched reluctance mode. Since neither of these features were utilized in this work,

the PWMGATE register was not used. The gate drive unit also controls the polarity of

53

the gating patterns with the use of the PWMPOL pin. The voltage level on this external

pin determines whether the PWM gating patterns are active low or active high. In this

case, the PWM patterns are selected to be active low.

The last block of the PWM controller is the PWM shutdown unit. In this work,

the unit was disabled to simplify the external hardware to the DSP. The PWM shutdown

unit gives an external device the ability to shutdown the PWM controller.

4.2.4 Programmable Interrupt Controller

The ADMC401 allows the user to program interrupt service routines for handling

peripheral interrupts. The software code presented in the next section is interrupt driven.

The three interrupts of interest are the PWM trip, ADC end-of-conversion, and

PWMSYNC. Since the PWM shutdown unit was disabled, the PWM trip interrupt does

nothing. The ADC end-of-conversion and PWMSYNC interrupts are used by the code to

coordinate the calculation and updating of the duty-cycles. Fortunately, Analog Devices

has prewritten code for placing user defined interrupt vectors in the interrupt vector table.

Interrupts will be discussed in further detail in the next section.

4.3 DSP Code

In this section, the software code that implements the proposed controller is

presented. The first subsection shows the discretization of the continuous-time PI and

modified PI controllers from Chapter 2. In the second subsection, the functions for the

discretized controllers and the main interrupt service routine are described. The program

flow is also detailed, in the second subsection, with the aid of flowcharts. The complete

software code listing can be found in Appendix B.

54

4.3.1 Discretization of the Continuous-time Controllers

In Chapter 2, the PI and modified PI controllers were tuned in the continuous-time

domain. The actual controllers are implemented in the discrete-time domain. As a result,

the continuous-time controllers need to be discretized.

There are many techniques available that convert a continuous-time transfer

function into a discrete-time transfer function. The bilinear transformation was chosen

because Analog Devices has already developed software code for a PI controller using

this technique [14]. The bilinear transformation is performed by substituting the right-

hand side of Equation 25 into s in the transfer function to be discretized.

If a continuous-time PI controller is given by C(s) = U(s)/I(s),then using the

transformation yields:

2 z-l (25) s <=> T z + \

U(z) = (26)

Equation 26 corresponds to the following difference equation:

(27)

U(k) = cj(k) + c2I(k -1) + U(k -1) (28)

55

The difference equation given in Equation 27 can be directly implemented in the

DSP. A signal flow diagram can also be made from Equation 26 as shown in Figure 4.7.

The saturation block is used to avoid integral wind-up. Integral wind-up will be further

discussed in the next subsection.

U(k)

Figure 4.7: Signal flow diagram for a discretized PI controller

The above process can be repeated for the modified PI controller. If a

continuous-time modified PI controller is given by C2 (s) = U2 (s)/I2 (s), then the z-

domain transfer function for C 2 (s) is:

Kp (1 + ]-K12T)z2 + Kp (K]2T)z + Kp(- K12T -1) U2 (z) = = 2 12 (z)

(l + 2 ^ ) z 2 - 4 ^ z + ( 2 ^ - l ) ( 2 9 )

Equation 29 corresponds to the difference equation:

T 4 0-2%)

U2 (k) = U2(k-\) + f - U2 (k-2) + 1 + 2^- \ + 2±

T T

1

\ + 2± T

Y Y T Kp(KI2T 1) ±^f-I2 (k -1) + 2 — 12 (k - 2) 1 + 2^- 1 + 2 ^

T T

(30)

56

U2 (k) = kxU2 (*-!) + k2U2 (k-2) + pxI2 (k) + p2I2 (*-!) + p3I2 (k-2) (31)

The signal flow diagram for the modified PI controller is shown in Figure 4.8.

The saturation block is again used to avoid integral wind-up.

Figure 4.8: Signal flow diagram for a discretized modified PI controller

4.3.2 Program Code Description

Analog Devices provides numerous software examples, both in the user's manual

[15] and in various application notes [16]-[20]. A large amount of code written by

Analog Devices was used to reduce the code development time. The ADC end-of-

conversion interrupt service routine and modified PI controller routine were the only

significant portions of code that were developed.

The header file main.h includes the values for the PWM controller timing unit

registers. The header file modpi.h and dsp file modpi.dsp implements the modified PI

controller. The modpi routine can be called by any program if the header file is added to

its include list. This is equivalent to the use of the PI routine developed by Analog

Devices. Main.dsp is the main program file. The main program is interrupt driven. As a

result, after the DSP is initialised, the DSP enters an infinite loop while waiting for

interrupts to occur. The variables and constants used by the ADC end-of-conversion

interrupt routine and the routine itself are also included in the main.dsp file.

57

As can be seen by the flowchart in Figure 4.9, the DSP is first initialised and then

enters an infinite loop. The various functional blocks of the DSP including the PWM

controller unit, A/D unit, and interrupt controller are initialised in a known state. The

DSP then waits until an interrupt occurs. Once an interrupt has been detected then the

revalent interrupt vector is fetched and executed. Since the vector can only contain four

instructions, any large interrupt service routine, such as the ADC end-of-conversion

routine, must be located elsewhere in memory and a jump must be made to its location.

The ADC end-of-conversion interrupt is used instead of the PWMSYNC interrupt

because the ADC end-of-conversion interrupt guarantees that the sampled data is the

most current and valid. The PWMSYNC interrupt is generated by the occurrence of the

PWMSYNC pulse. The PWMSYNC pulse also is used to signal the start-of-conversion

in the A/D unit. Since the conversion time is almost 2 p.s, if the PWMSYNC interrupt is

used to process the new duty-cycles, then the most current sampled data will not be used.

The PWMSYNC and PWMTRTP interrupts contain no operation (NOP) instructions and

then return the control to the main program.

Enable interrupts

Calibrate A/D unit

Figure 4.9: DSP initialisation and infinite loop routine MAIN

58

The ADC end-of-conversion interrupt service routine, as shown in Figure 4.10,

performs the necessary calculations required to generate the new duty-cycles based on the

sampleddata just converted.

Read New Voltage and Current Data

Calculate Reference Voltages Vab and

Vcb

V e r r o r - V r e f - V m e a s u r e d

Execute Mod PI Controller Twice

lerror = Iref- I m e a s u r e d

Execute PI Controller Twice

V b = - ( V a + V c )

Update Duty-Cycles

Figure 4.10: ADC end-of-conversion interrupt service routine

The voltage references are calculated with the use of the sin function provided in

the trigono.h include file. The sine of the input variable x is approximated by the

following formula:

sin(x) = 3.140625*+ 0.02026367*2 -5.325196*3 +0.5446778*4 + 1.800293*5 (32)

where x can range from 0 to 0.5 which corresponds to 0 degrees to 90 degrees.

59

The sin function included in trigone h can take an input value from -1 to 1, which

corresponds to -180 degrees to 180 degrees.

The angle of phase A is used as a reference angle. The reference angle is

incremented and stored as a 32-bit value every time the service routine is executed.. The

DSP uses signed twosrcomplement arithmetic with fractional binary numbers. As a

result, the angle automatically "wraps-around" to -180 degrees when the angle exceeds

180 degrees. Glitches in the reference voltages are avoided with the use of a high

precision reference angle and the inherent arithmetic of the DSP. The sin of the reference

angle + 30 degrees is multiplied by the peak amplitude of the desired output voltage to

obtain the current instantaneous value of the VAB reference voltage. Similarly, the sin of

the reference angle + 90 degrees is multiplied by the peak voltage to obtain the VCB

reference voltage.

The error voltages and currents are saturated to half of their potential range. This

can degrade the transient response of the controller. Alternately, the errors can be scaled

down by two and the outputs of the controllers scaled up by two with saturation. Both

techniques were tried and no difference was notable in the output waveforms. The first,

simpler, method was therefore used.

The input to the modified PI controller routine is the error voltage. There are

three important issues that deal with the implementation of the routine: the scaling of the

controller coefficients, coefficient precision, and integral antiwind-up.

The controller coefficients must be represented by fractional numbers since the

DSP performs arithmetic assuming the input operands are fractional numbers. As a

result, the coefficients must be scaled down to lie within -1 and 1 while still maintaining

the maximum precision possible. The scaling factor should be a power of two. This

allows the final result to be shifted up by the barrel shifter of the DSP. In this case, the

largest coefficient is 1.92. A scaling factor of two was used.

60

The coefficients for the input and delayed input terms are quite small. In

particular, the coefficient for I2 (k -1) is very small. To maintain a high level of

precision in the coefficients, 32-bit numbers are used. Since the coefficients for the

delayed output terms are sufficiently large, only 16-bit numbers are used to represent

these coefficients.

Integral wind-up is a phenomenon that needs to be avoided. Integral wind-up

occurs when the output of a controller saturates for a long period of time. If no measures

have been taken then the integral of the input error becomes very large. As a result, any

change in the input error has no effect on the controller output and the closed-loop

controller opens creating an open-loop system. An error input with the opposite sign of

the original error has to be present for a long time before the system becomes controllable

again. Integral wind-up can be avoided by saturating the integral section of the

controller. The saturation is accomplished with the use of the MAC arithmetic unit of the

DSP since the new controller output is calculated solely with the MAC unit. After the

new scaled down output value is calculated the MAC is checked for overflow. If the

final calculation resulted in an overflow, then the MAC is saturated: Similarly, the

properly scaled controller output value is saturated if the scaling would result in a value

outside the range for fractional numbers. A flowchart, as shown in Figure 4.11,

demonstrates how saturation is implemented.

The delayed controller output values are stored as 32-bit values. This minimizes

the steady-state error of the controller due to finite word length effects.

The algorithm for the modified PI controller is very similar to the algorithm

developed for the PI controller by Analog Devices.

61

Calculate New Scaled Down Output Value (OV)

Yes

Saturate OV

Yes

Z H I Saturate OV

Figure 4.11: PI and modified PI controller routines

where: sf = scaling factor

The input to the PI controller is the error current. The algorithm developed by

Analog Devices was used to implement the PI controller. The flowchart in Figure 4.11

also applies to the PI controller routine except the scaling factor is four in this case. The

32-bit version of the algorithm is used to minimize the effects of finite word length.

The PI and modified PI controller routines are executed twice. The outputs f the

PI controller routines are the new duty-cycles for phases A and C. The duty-cycle for

phase B is the negated sum of phases A and C, which is saturated if necessary. The new

duty-cycles are now updated but do not come into effect until the next time the

PWMSYNC pulse is generated.

62

Chapter 5

Experimental Results

In this chapter, the results obtained with the experimental UPS inverter as

described in the previous chapter are presented. The experimental results are explained

with reference to the simulation results produced with PSIM. As expected, the real

system behaves quite closely to the simulated system but there are some differences that

can be attributed to inaccuracies in the simulated system. Unless otherwise specified, the

controller gains presented in Chapter 2 were used to produce the experimental results.

Since two proportional gains for the current controllers were given, a proportional gain is

listed for each result.

5.1 Output Line Voltages

The steady-state line voltages, as shown in Figures 5.1 and 5:2, are produced with

and without the controller. A per-phase load of approximately 19 fi and current controller

with a proportional gain K = 0.065 were used to generate the line voltage waveforms.

Notice the significant ripples in the waveforms produced with the controller. As

demonstrated with the use of a simulation, the ripples are due to noisy sensor

measurements. The measured voltage and current data is presented in the next section.

The system with the controller generates line voltages which are different by less than 4

Vrms. The line voltages are, therefore, well balanced.

The open-loop voltage waveform produced by the actual system for VCB is similar..

in shape but not magnitude to the waveform produced by the simulated system. VAB,

however, is different in shape and magnitude from the simulation result. Although the

simulation results for open-loop are different from the experimental results, the controlled

system produces similar results for the simulation and actual system.

63

The simulation with the controller produces line voltages whose magnitude does

not depend on the load. In reality, the load influences the output voltage,magnitude. The

average line voltage for a per-phase load of approximately 26 fi is 109 Vrms. When the

load is increased to approximately 13 fi, the average line voltage drops to 108 Vrms.

The load regulation for a 50 % change in load is 0.9 %.

The sensor gains for the voltage loops are different from their nominal gains. The

output voltage for VAB was measured to be 111 Vrms for a per-phase 19 fi load. The

output of the voltage sensor with this line voltage is 3.18 Vpeak-to-peak. The total gain

of the voltage sensor (isolation amplifier and A/D unit) is 0.00506 compared to the

nominal gain of 0.00573. The measured gain for the VCB sensor is very close to the gain

for the VAB sensor. As a result, the reference voltage peak amplitude was changed to

reflect the true gain of the sensors. All of the results presented in this chapter use the

adjusted voltage reference.

The measured line voltages for two different current controllers are tabulated in

Table 5.1. The results are obtained with a per-phase output load of approximately 19 fi.

Output Voltages

Current Controller Vab Vac Vcb Va Vb V c

K = 0.055 105 V 114 V 115 V 60 V 61 V 68 V

K = 0.065 107 V 111 V 109 V 62 V 61 V 63 V

Table 5.1: Measured output voltages for two current controller gains

As expected, the line voltages are better balanced with the faster current

controller. Notice that the line voltages for the faster current controller are all within

10% of the nominal line voltage of 104 Vrms. For both of the current controllers, the

phase C voltage is larger in magnitude than the phase A and B voltages. The phase C

voltage is also larger in magnitude in the simulations. The simulation behaves quite close

to the actual circuit for the controlled system case.

64

200

-200 I , . • -• • : 1

0 5 10 15 20 25 tim t (ms)

Figure 5.1: Measured steady-state output line voltages for K - 0.065, 19 fi load

200

.200 I 1 : • • •— 1

0 5 10 15 20 25 tim e (m s)

Figure 5.2: Measured steady-state output voltages for no controller, 19 fi load

65

1 0 15 tim e (m s)

2 0 2$

Figure 5.3: Measured output voltage from isolation amplifier

Figure 5.4: Measured differential inductor current after level shifting circuit

66

5.2 Effect of Noise on the Generated Line Voltages

As mentioned previously, the level of noise in the measured signals affects the

quality of the generated line voltages. Figure 5.3 shows the measured line voltage VAB at

the output of the precision isolation amplifier. The measured difference in inductor

currents after the level shifting circuitry is shown in Figure 5.4. Notice that in the

current measurement case the level of noise is quite substantial. The noise has a greater

effect on the duty-cycles compared to the current references. The duty-cycle for phase A

is shown in Figure 5.5 while the current reference is shown in Figure 5.6. The

duty-cycle and current reference were measured on a D/A output of the DSP. The current

reference has some oscillations but the magnitude of the oscillations is very small. The

oscillations in the duty-cycle for phase A are a lot more significant. The second PI

controller generates similar oscillations for the duty cycle of phase C. The oscillations

generated from the current controllers are larger than those from the voltage controller

because the bandwidth of the current controller is higher than that of the voltage

controller. The higher bandwidth implies that the current controller reacts more quickly

than the voltage controller. As a result, the current controller is more susceptible to

noise. The effect of varying the current controller bandwidth can be seen in Figure 5.7.

The ripples produced with the slower current controller are smaller than those from the

faster controller. This gives evidence that the oscillations produced by a controller

increases as its bandwidth increases.

67

0 5 10 15 20 25 tim e (m s)

Figure 5.5: Measured duty-cycle for phase A for K = 0.065, 19 fi load

180

0 1 2 3 4 S 6 7 8 tim e (mi)

Figure 5.7: Comparison of current controller proportional gains for a 19 Q load

69

Chapter 6

Conclusions

A new control strategy for a three-phase UPS is proposed in this work. The

inverter is modeled by a small-signal time averaged plant. Bode plots are used to analyze

the stability of the controller. Simulation and experimental results verify the operation of

the controller with a balanced resistive load.

The controller performs quite well even in the presence of substantial

measurement noise. A better circuit layout will reduce the noise in the measured signals

and, as a result, reduce the ripples generated in the output waveforms. The noise limited

the achievable bandwidth of the current controllers. The bandwidth of the current

controllers is far from its practical limit. Even with a slow current controller, the line

voltages are within 4 Vrms for a per-phase load of 19 Q. The line voltages are also

within 10 % of the nominal line voltage.

6.1 Contributions

Several contributions have been made in this work. The contributions include:

• Proposed a new control strategy that uses two line voltages and corresponding

differences in inductor currents for those lines as control variables for a three-

phase UPS. The controller can be implemented either as an analog or digital

controller. For this work, a digital controller is implemented since digital

controllers are typically used in this application.

• Analyzed the stability of the proposed controller for a balanced resistive load.

The analysis includes the phase lag introduced by using digital control.

70

• Verified the operation of the controller both in simulation and with an

experimental inverter.

6.2 Future Work

This work is the first step in determining the feasibility of using the proposed

controller for a three-wire UPS. There are three significant issues that need to be

addressed:

1) The stability under severely unbalanced loads must be investigated. Even though

most three-wire UPS systems are balanced, under transient conditions the load

may be become unbalanced. The controller must remain stable under these

conditions.

2) The transient response of the controller needs to be investigated. The transient

response was hot investigated in this work because the controller is far from

optimal due to measurement noise.

3) The response of the controller to non-linear loads must also be investigated. Most

of the work on three-phase UPS systems is directed towards obtaining undistorted

line voltages with non-linear loads. Most likely, control based on a small signal

averaged time-averaged model is too slow. The control strategy can still be used

but the plant will likely need to be modeled in another way. This can lead to

techniques such as inductor current prediction for large signal models.

71

B i b l i o g r a p h y

[1] C D . Manning, "Control of UPS Inverters" in LEE Colloquium on Uninterruptible

Power supplies, pp. 3/1 - 3/5, 1994

[2] A. Sugimoto, S Morimoto, M Yano, "A High Performance Control Method of a

Voltage Type P W M Converter" in LEEE PESC Conf. Rec, pp 360-368, 1988

[3] A. Tripathi, S. B. Dewan, "Modeling and Design of a Novel Voltage Control

System for Three Phase Fixed Frequency Static Power Supplies" in LEEE Conf. Rec. of

the Thirtieth IAS Annual Meeting, IAS'95, vol. 3, pp. 2641-2648, 1995

[4] Analog Devices Inc., "Implementing Space Vector Modulation with the

ADMC401" in Application Note AN401-17, 1999

[5] Jun-Seok Cho, Seung-Yo Lee, Hyung-Soo Mok, Gyu-Ha Choe, "Analysis and

Design of Modified Deadbeat Controller for 3-Phase Uninterruptible Power Supply" in

LEEE 1999 International Conference on Power Electronics and Drive Systems, PEDS'99,

pp. 1003-1009, 1999

[6] Feng-Yih Hsu, Li-Chen Fu, "Adaptive Fuzzy Control for Uninterruptible Power

Supply with Three-Phase P W M Inverter" in Proceedings of the 1996 Asian Fuzzy

Systems Symposium, Soft Computing in Intelligent Systems and Information Processing,

pp 199-193, 1996

[7] L . K. Wong, Frank H. F. Leung, Peter K. S. Tarn, "Control of P W M Inverter

using a Discrete-time Sliding Mode Controller" in LEEE 1999 International Conference

on Power Electronics and Drive Systems, PEDS'99, pp. 947-950, 1999

72

[8] Youichi Ito, Shoichi Kawauchi, "Microprocessor-Based Robust Digital Control

for UPS with Three-Phase PWM Inverter" in IEEE Transactions on Power Electronics,

vol.10, No. 2, pp. 196- 204, 1995

[9] H. Jin, Switched Mode Power Supply Design, Course Notes for ELEC 558,

University of British Columbia, 1998

[10] K. Ogata, Discrete-Time Control Systems, 2nd Edition, Prentice Hall, 1995

[11] Lloyd Dixon, " Average Current Mode Control of Switching Power Supplies" in

Applications Handbook, pp. 3-356 - 3-369, Unitrode Corporation, 1997

[12] N. Mohan, T. M. Undeland, W. P. Robbins, Power Electronics - Converters,

Applications and Design, Wiley, 1995

[13] Powerex Inc., "Using Intelligent Power Modules" in Application Note 6, pp. A-81

- A - l l l , 1998

[14] Analog Devices Inc., "Implementing PI Controllers with the ADMC401" in

Application Note AN401-13, 2000

[ 15] Analog Devices Inc., ADSP-2100 Family User'sManual, 3rd Edition, 1995

[16] Analog Devices Inc., "Generation of Three-Phase Sine-Wave PWM Patterns on

the ADMC401" in Application Note AN401-3, 1999

[17] Analog Devices Inc., " Double Update Mode of PWM Generation Unit of the

ADMC401" in Application Note AN401 -2, 1999

[18] Analog Devices Inc., "Basic Trigonometric Subroutines for the ADMC401" in

Application Note AN401 -10, 1999

73

[19] Analog Devices Inc., "ADC-system on the ADMC401" in Application Note

AN401-5, 1999

[20] Analog Devices Inc., "Three-Phase PWM Generation Unit of the ADMC401"

Application Note AN401 -1, 1999

74

Appendix A

Gate Driver Interface PCB Layout

Scale: 1.74:1

75

Appendix B

DSP Code Listing

B . l M o d p i . h

^***************************************************************************************

* Library: Implements a modified PI controller in double precision * * Fi l e : pimod.h * * Description: pimod include f i l e * Purpose : Declare library routines and macros for Modified PI controller * * Author : KW * Version : 1.0 * * Date : July 2000 ' .* * Modification History: November 2000 * * * * ECE * * UBC ' * ***************************************************************************************)

* * *. Constants that need to be defined in main.h: * * * * None ***************************************************************************************}

***************************************************************************************

* Other Libraries Required by this Module: * * * * None * ***************************************************************************************}

#ifndef PIMOD_INCLUDED #define PIMOD_INCLUDED [*************************************************************************************** * Routines Defined in this Module ' * ***************************************************************************************}

.EXTERNAL PIM0D32_Control_;

{*************************************************************************************** * Global Variables Defined in this Module * ***************************************************************************************}

{ None }

76

{***************************************************************************************

* Type: Macro * * Call: Init_PIMOD32(Delay_line, Initial_value, Initial_value);

* Sets the i n i t i a l value of the integrator (resets PI i f Initial_value i s zero) +

* Inputs : %0 : Delay line buffer * * %1, %2 : I n i t i a l values of integrator in 1.15 (dreg [not ar] or constant) * * • * * Outputs : None * * • * * Modified: ar, 13, M3, L3 * ***************************************************************************************)

.MACRO Init_PIMOD32(%0, %1, %2) ; 13 = *%0; L3 = %%0; M3 = 1;

ar = pass 0; DM(I3,M3) = ar; DM(I3,M3) =. ar; DM(I3,M3) = ar; DM(I3,M3) = ar; ar = %1; DM(I3,M3) = ar; ar = %2; DM(I3,M3) = ar;

.ENDMACRO;

* Type: Macro *

* * Call: PIMOD32(Delay_line, Coefficients); * * * * Calculates the current output of the modified PI from the input error * * The integrator consists of 32 bits * * * Inputs : %0: Delay line buffer * %1: Coefficient buffer * ar: Input error value in 1.15 format * * Ouputs : s r l : Output value in 1.15 format

* Modified: mxO, mxl, myO, mr, axO, ayO, ar, se, sr, 13, M3, L3, 17, M7, L7, 12, L2, M2

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * .MACRO PIMOD32(%0, %1);

13 = A%0; L3 = %%0; M3 = 1;

77

17 = A%1; L7 = %%1; M7 = 1;

12 = A%0; L2 = %%0; M2 = 2;

CALL PIMOD32_Control_; .ENDMACRO;

#endif

B .2 Modpi.dsp

. MODULE/RAM/S EG=US ER_PM1 PImod_controller; ^***************************************************************************** ********** * * * Library: Implements a modified PI controller in double precision * * * * F i l e : pimod.dsp *

* Description: pimod Code File * * Purpose : Library Routines for Modified PI controller * * Author : KW * * Version . : 1.0 * * Date : July 2000 * * Modification History: November 2000 * * Added 32 b i t coeff for Ik, Ik+1, and Ik+2 * * ECE * * UBC * ***************************************************************************************)

#include <main.h>;

j + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Calculate Configuration Register Contents from Parameters ***************}

{ None } ,*************************************************************************************** i * * Constants Defined in the Module ***********************************************************

{ None } ,*************************************************************************************** i * * Routines Defined in this Module * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * )

78

.ENTRY PIMOD32_Control_; j * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Global Variables Defined in this Module * *************************************** ************* ***********************************}

{ None }

j * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Local Variables Defined in this Module ' . • ' * ***************************************************************************************}

{ None }

r * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

* Type: Routine * * Call: c a l l PIMOD32_Control_; * * Implements a double precision Modified PI controller * * * * * * * * * * * * *

Inputs 13, 12.: pointers to Delay line buffer M3: M2:

Outputs

L3, L2 : length of Delay line buffer 17: pointer to Coefficient buffer M7: 1 L7: length of Coefficient buffer ar: Input.error value in 1.15 format

s r l : Output value in 1.15 format

* Modified: mxO, mxl, myO, myl, mr, axO, ayO„ ar, se, sr, 13, 17, 12 * • * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

PIM0D32_Coritrol_:

mxO = DM(I2,M2); {Dummy Read) s r l = ar;

* * *

• * * * * * * * * * * * * * * *

'* *

• mxO = DM(I3,M3), myO = PM(I7,M7) f mr = mxO * myO (SU) , mxO = DM(I3,M3), myO = PM(I7,M7) r

mr = mr + mxO * myO (SU) , myO = PM(I7,M7) r

mr = mr + s r l * myO (SU), mxO = DM(I3,M3), myO = PM(I7,M7) 9

mr = mr + mxO * myO (US),. mxO = DM(I3,M3), myl = PM(I7,M7) r

mr = mr + mxO * myl (US) , mxl- = DM(I3,M3);

mrO = mrl; mrl = mr2; DM(I2,M2) = mxO;

mr *= mr + mxl * myO (SS), mr = mr + mxO * myl (SS) ,

mxO = DM(I3,M3), myO = PM(I7,M7); mxl = DM(I3,M3), myl = PM(I7,M7);

79

DM(I2,M2) = mxO;

mr = mr + mxl * myO (SS),. mxO = DM(I3,M3), myO = PM(I7,M7); mr = mr + mxO * myl (SS); mr = mr + s r l * myO (SS) ; i f MV SAT mr;

DM(I2,M3) = mxO; DM(I2,M2) = s r l ;

SE = EXP mrl (HI) ; axO = SE; ayO = OxOOOl; ar= axO + ayO; i f GT JUMP PIMODSAT;

sr = ASHIFT mrl by 1 (HI); sr = sr OR LSHIFT mrO by 1 (LO) ; DM(I2,M2) = srO; DM(I2,M3) = s r l ; rts;

PIMODSAT: astat=0x40; i f MV SAT mr; DM(I2,M2) = mrO; DM(I2,M3) = mrl; srl=mrl; rts;

•ENDMOD;

B.3 Main.dsp

.MODULE/RAM/SEG=USER_PMl/ABS=0x60 Main_Test; j * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Application: Coupled dual loop PI controller for three phase inverter * * * * F i l e : Main.dsp * * * * Description: main program f i l e * * Purpose : * * * •Author : KCW * * Version : 1.0 * * Date : October 2000 * * Modification History: November 2000 * * * * EECE UBC * **********************************************

80

* Include General System Parameters and Libraries . * *************************************************************************************** j

#include <main.h>; #include <pwm401.h>; #include <adc401.h>; #include <trigono.h>; #include <dac401.h>; #include .<pi.h>; #include <pimod.h>;

^*** *********************************************************************************** * * Constants Defined in the Module * ***************************************************************************************}

.CONST Incr_LSW

.CONST Incr_MSW

.CONST PiOverSix •CONST PiOverTwo

= 0x3A07 ; = 0x006D ; = 0x1555; = 0x4000;

{ Angle increment } { 32 bit value } { Hex equivalent of pi/,6 } > ( Hex equivalent of pi/2 }

{*************************************************************************************** * Global Routines Defined in this Module ( .Entry ) * ***************************************************************************************}

{ None } [***************************************************************************************

* Global Variables Defined in this Module ( .Global ) . * **************************** * * *********************************************************}

{ None }

{*************************************************************************************** * Local Variables Defined in this Module * ***************************************************************************************\ .VAR/DM/RAM/SEG=USER_DM1 scale; . INIT scale : 0x60CA;

{ Desired voltage amplitude (0-1) }

. VAR/DM/RAM/SEG=USER_DM1 VrefA;

. VAR/DM/RAM/S EG=US ER_DM1 VrefB;

. VAR/DM/RAM/SEG=USER_DM1 VrefC;

.INIT VrefA : 0x0000;

.INIT VrefB : 0x0000;

. INIT VrefC : 0x0000;

{ Voltage demands

. VAR/DM/RAM/S EG=US ER_DM1 Theta_LSW;

.INIT Theta_LSW : 0x0000;

•VAR/DM/RAM/SEG=USER_DM1 Theta_MSW; .INIT Theta MSW : 0x0000;

.VAR/DM/RAM/SEG=USER DM1 Vab;

81

. VAR/DM/RAM/S EG=US ER_DM1 Vcb;

.VAR/DM/RAM/SEG=USER_DM1 lab; •VAR/DM/RAM/SEG=USER_DM1 Icb; •INIT Vab : 0x0000; •INIT Vcb : 0x0000; .INIT lab : 0x0000; . INIT Icb : 0x0000;

.VAR/DM/RAM/SEG=USER_DM1 VrefAB; •VAR/DM/RAM/SEG=USER_DM1 VrefCB; •VAR/DM/RAM/SEG=USER_DM1 IrefAB; •VAR/DM/RAM/SEG=USER_DM1 IrefCB; .INIT VrefAB : 0x0000; .INIT VrefCB : 0x0000; .INIT IrefAB : 0x0000; .INIT IrefCB : 0x0000;

,VAR/RAM/PM/CIRC/SEG=USER_PM1 PI_VCoef32[8]; •INIT PI_VCoef32: 0x715000, 0xDC5B00, 0x6B0B00, 0xC29D00, 0x7D6300, OxFDFOOO, OxOOOEOO, 0x021E00 ; {cL, dL, eL, a, b, cH, dH, eH } .VAR/RAM/DM/CIRC/SEG=USER_DM1 PI_VAB_Delay32[6] ; { Uk_L, Uk+1_L, Uk_M, Uk+1_M, Ik, Ik+1} •INIT PI_VAB_Delay32: 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000;

• VAR/RAM/DM/CIRC/SEG=USER_DM1 PI_VCB_Delay32[6] ; { Uk_L, Uk+1_L, Uk_M, Uk+1_M, Ik, Ik+1) •INIT PI_VCB_Delay32: 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000;

#define PI_ISF32 2 { n }

.VAR/RAM/PM/CIRC/SEG=USER_PM1 PI_ICoef32[2];

.INIT PI_ICoef32: 0xADF500, 0x545B00; { AO, Al }

.VAR/RAM/DM/CIRC/SEG=USER_DM1 PI_IAB_Delay32[3] ; { Ik, Uk_M, Uk_L}

.INIT PI_IAB_Delay32: 0x0000, 0x0000, 0x0000;

.VAR/RAM/DM/CIRC/SEG=USER_DM1 PI_ICB_Delay32[3] ; { Ik, Uk_M, . Uk_L)

.INIT PI_ICB_Delay32: 0x0000, 0x0000, 0x0000; I**************************************************************************************) { Start of program code ( i**************************************************************************************\ Startup:

PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); Set_Bit_DM(MODECTRL, 6); {Set into Double Update Mode} Set_InterruptVector(ADC_INT_ADDR, ADC_INT); { Vector for ADC_INT int }

IFC = 0x80; { Clear any pending IRQ2 inter.} ayO = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ayO; IMASK = ar; { IRQ2 ints f u l l y enabled here }

ADC_Init; { Calibrates the ADC block. This calibration requires { values from the ADC and so the PWMSYNC must be }

82

{ running when i t is called. Here a l l the offset are } { stored. { Thus, ADC_init is..placed after IRQ2 is enabled }

INIT_PIMOD32(PI_VAB_Delay32, 0x0000, 0x0000); { reset mod PI } INIT_PIMOD32(PI_VCB_Delay32, 0x0000, 0x0000); { reset mod PI ) INIT_PI32(PI_IAB_Delay32, 0x0000); { reset PI ) INIT_PI32(PI_ICB_Delay32, 0x0000); { reset PI )

DAC_Init;

MAIN: { Wait for interrupt to occur } NOP;

NOP; JUMP MAIN;

RTS;

[**************************************************************************************} { PWM Interrupt Service Routine } ^ *********************************************** ***************************************}

PWMSYNC_ISR: nop; r t i ; {**************************************************************************************} { ADC End-of-conversion Service Routine } (**************************************************************************************)

ADC_INT:

Set_DAG_registers_for_trigonometric;

DAC_Pause; { Required only when II, Ml or LI is used )

{ Read in measured line voltages and inductor currents )

ADC_Read(ADC0, Offset_0to3); { Use ADC converter on ADCM401 ) ar = -ar; dm(Vab) = ar;

ADC_Read(ADC4, Offset_4to7) ; ar = -ar; dm(Vcb) = ar;

ADC_Read(ADC1, Offset_0to3); dm(Iab) = ar;

ADC_Read(ADC5, Offset_4to7); dm(Icb) = ar;

{ Calculate current line voltage references )

axO = dm(thetaLSW); ,

83

ayO = Incr_LSW; ar = axO + ayO; dm(theta_LSW) = ar; axO = dm(theta_MSW); ayO = Incr_MSW; ar = axO + ayO + C; dm(theta_MSW) = ar;

axO = ar; ayO = PiOverSix; ar = axO + ayO; Sin(ar); myO = dm(scale); mr = ar*myO (SS); dm (VrefAB) = mrl;

axO = dm(theta_MSW); ayO = PiOverTwo; ar= axO + ayO; Sin(ar); myO =dm(scale); mr = ar*myO (SS); dm(VrefCB) = mrl;

axO = dm(VrefAB); ayO = dm(Vab); ena AR_SAT; ar = axO - ayO; dis AR_SAT;

dm(Verror) = ar; Pimod32(PI_VAB_Delay32, PI_VCoef32) ; dm(IrefAB) = s r l ;

axO = dm(VrefCB); ayO = dm(Vcb); ena AR_SAT; ar = axO - ayO; dis AR_SAT;

Pimod32(PI_VCB_Delay32, PI_VCoef32) ; dm(IrefCB) = s r l ;

{ Do inner current loop calculations

axO = DM(IrefAB); ayO = DM(lab); ena AR_SAT; ar = axO - ayO; dis AR_SAT;

Pi32(PI_IAB_Delay32, PI_ICoef32, PI_ISF32) dm(VrefA) = s r l ;

axO = DM(IrefCB); ayO = DM(Icb);

84

ena AR_SAT; ar = axO - ayO; dis ARJ3AT;

Pi32(PI_ICB_Delay32, PI_ICoef32, PI_ISF32); dm(VrefC) = s r l ;

axO = dm{Vref A); ar = -axO; axO = ar; ayO = dm(VrefC) ; ena AR_SAT; ar = axO - ayO; dis AR_SAT; dm(VrefB) = ar;

{ Update PWM duty cycle registers )

axO = DM(VrefA); axl = DM(VrefB); ayO = DM(VrefC); PWM_update_demanded_Voltage(axO,axl, ayO) ;

******************************} { PLOT on the DAC |**************** **************************}

myO = dm(Irefab); DAC_Update;

DAC_Put(4, myO);

RTI;

* * * * * * * * * A * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * } { PWM Trip Interrupt Service Routine

* * * * * * * * * * * *

PWMTRIP_ISR: nop; r t i ;

.ENDMOD;

85