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Solid-State Electronics 51 (2007) 1534–1539

DRAM retention tail improvement by trap passivation

A. Weber a,*, A. Birner b, W. Krautschneider c

a Qimonda Dresden GmbH and Co. OHG, Koenigsbruecker Street 180, D-01099 Dresden, Germanyb Infineon Technologies AG, Wernerwerkstr. 2, D-93049 Regensburg, Germany

c Hamburg University of Technology, Eissendorfer Strasse 38, D-21073 Hamburg, Germany

The review of this paper was arranged by Adrian M. Ionescu and Yusuf Leblebici

Abstract

A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM dataretention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electricfields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512 Mbit and 1 Gbit DRAMs in 110 nmtechnology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retentiontail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40%. Detailed activationenergy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps byF-implantation.� 2007 Elsevier Ltd. All rights reserved.

1. Introduction

The control of retention time distribution is one of themost important issues for a successful DRAM develop-ment. The distribution of retention time has been shownto exhibit two parts: tail and main distribution [1]. Mostof the cells belong to the main distribution and have reten-tion times significantly higher than product specification.Only a minor part (tail) suffers from increased leakageand limits production yield. It has been reported that trapassisted gate induced drain leakage (GIDL) is a major leak-age path for DRAM retention tail [2,3]. By means of statis-tical analysis of activation energies and their fielddependencies on individual memory cells we could providefurther insight into dominant mechanisms and their distri-bution [4]. It was found that the leakage current of themajority of worst tail cells is due to tunneling enhancedgeneration current (thermionic field emission) from traps

0038-1101/$ - see front matter � 2007 Elsevier Ltd. All rights reserved.

doi:10.1016/j.sse.2007.09.023

* Corresponding author.E-mail address: Andreas.Weber.drs@qimonda.com (A. Weber).

located in the G/D overlap area. The general approachto cope with the tail distribution is the reduction of electri-cal field strength at the storage node junction in order tominimize tunneling effects. With further decreased ground-rules this will only be possible by introducing three dimen-sional devices (e.g. RCAT, SRCAT, STAR, EUD – see [5]for a summary) as these allow wider depletion layer widthsfor the storage junction and therefore lower electrical fieldswithout inducing problems due to short channel effects. Onthe other hand, relatively low on-currents of 3D-devicescompared to planar devices become increasingly limitingfor high speed applications. Therefore, it is important tobetter understand and control the origin of the tail leakage,namely the traps themselves, instead of lowering theirimpact by electric field reduction. As a completely differentapproach the passivation of traps responsible for retentiontail cells is investigated in this work. This is very challeng-ing, because trap creation and passivation has to be studiedwith respect to the complete production process on anextremely low probability level (>4r deviation from med-ian for retention tail). Standard test structures are not suit-able for this purpose and new characterization methods are

A. Weber et al. / Solid-State Electronics 51 (2007) 1534–1539 1535

needed. The first section of this paper summarizes the usedcharacterization method of activation energy analysis onindividual cells. Section 2 reports on the retention tailimprovement obtained by F-implant experiments. Theresults are discussed and confirmed by activation energymeasurements on individual cells in the last section.

Fig. 2. Dependence of the activation energy on the trap level taking onlythermal SRH generation into account. The smallest possible activationenergy is given for a midgap trap and is equal to EG/2.

2. Activation energy

The activation energy Ea is the parameter in the expo-nent of the Arrhenius law, which accurately describes thetemperature dependence of leakage current and retentiontime in DRAM cells

ILeak /1

tRet

/ exp�Ea

kB � T

� �ð1Þ

with kB being Boltzmann’s constant and T the absolutetemperature. A higher Ea value corresponds to a highersensitivity of ILeak on temperature. Ea can be experimen-tally obtained by measurement of the retention time ofindividual memory cells at different temperatures (see [6]for details). Measured values can be compared with theo-retically calculated activation energies of different leakagemechanisms. For an ideal pn-junction under reverse biashigher than a few kBT/q, only minority carrier diffusioncontributes to the leakage current given by

I ideal ¼ �qADN

LN

n2i

N A

þ DP

LP

n2i

N D

� �ð2Þ

where q is the electron charge, A the junction area, DN,P arethe carrier diffusion coefficients and LN,P the diffusionlengths. As the temperature dependence is dominated byn2

i / expð�EG=kBT Þ with EG being the energy gap, the acti-vation energy for the leakage current of an ideal junction isapproximately 1.12 eV.

For non ideal junctions Shockley–Read–Hall (SRH)carrier generation from within the depletion layer exceedsthe ideal reverse current. Using the depletion approxima-tion the SRH generation current is calculated to

ISRH ¼ �qAWni

sp exp DEkBT

� �þ sn exp �DE

kBT

� � ð3Þ

Fig. 1. Band diagram of a reverse biased pn-junction. (a) SRH generation mebands is equal to EG/2 and determines the activation energy Ea. (b) SRH gen

where W is the depletion layer width, sn,p are the minoritycarrier lifetimes and DE is the difference between trap andintrinsic Fermi levels. The activation energy of SRH is

Ea;SRH ¼ �o lnðISRHÞoð1=kBT Þ �

EG

2þ jDEj ð4Þ

The first term arises from the T-dependence of ni whereasthe second term comes from the denominator of (3). Fora trap level a few kBT away from midgap always one ofthe exponential functions becomes negligible, the other giv-ing rise to an additional Ea of DE. Eq. (4) is furthermoresupported by looking at the band diagram of a reversebiased pn-junction (Fig. 1). The activation energy can beinterpreted as the larger distance from the trap level toeither one of the bands since both thermal steps are neededto generate a leakage current. The longer distance limits theprobability and therefore determines current and tempera-ture behavior. Calculating activation energy in terms oftrap energy yields Fig. 2. Ea is equal to EG/2 for a midgaptrap (compare Fig. 1a) and increases for off-center trap lev-els (compare Fig. 1b). It should be emphasized that activa-tion energies smaller than EG/2 therefore cannot beexplained by simple SRH current.

In high electric fields SRH carrier generation is enhancedby thermionic field emission (TFE) [7]. For electric fields F

chanism from a midgap trap. The energetical distance to either one of theeration for an off-center trap. Ea is determined by the longer transition.

Fig. 3. Band diagram of a reverse biased pn-junction. (a) TFE generation mechanism from a midgap trap. TFE consists of a thermal excitation from thetrap level to point P followed by tunneling through the remaining barrier [7,8]. The activation energy is determined by the thermal step and can be smallerthan EG/2. (b) For higher fields the energy barrier becomes narrower and tunneling occurs after a smaller thermal step. For a given trap level the activationenergy therefore gets smaller for higher fields.

1536 A. Weber et al. / Solid-State Electronics 51 (2007) 1534–1539

below�0.9 MV/cm this can be described by a field enhance-ment factor C [8] and the leakage current is given by

ITFE ¼ ðCðF Þ þ 1Þ � ISRH � CðF Þ � ISRH ð5Þ

where

CðF Þ ¼ 2ffiffiffiffiffiffi3pp F

F Cexp

FF C

� �2" #

ð6Þ

F C ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi24m�ðkBT Þ3

qq�h

ð7Þ

The activation energy of TFE enhanced generation currentcan be calculated by taking the derivative of (5) with re-spect to 1/kBT

Ea;TFE ¼ �o lnðITFEÞoð1=kBT Þ ¼ Ea;SRH �

o

oð1=kBT Þ lnðCðF ÞÞ

¼ Ea;SRH �3

2kBT � 3kBT

FF C

� �2

ð8Þ

Fig. 4. Dependence of the activation energy on trap level and electricalfield. High electric fields shift the activation energies for all trap levels tosmaller values. Contrary TFE reduced to thermal SRH for fields below�0.5 MV/cm.

As the electric field F exceeds a critical field FC the last termof (8) becomes significant and reduces the activation energyrapidly to typical values between 0.3 and 0.55 eV. At thesame field the leakage current starts to increase dramati-cally according to (5) and (6). Again, the band diagramin Fig. 3 visualizes this behavior as TFE consists of thermalexcitation to a point P followed by tunneling through theremaining energy barrier. As the electric field increasesfrom Fig. 3a to b the tunneling barrier gets narrower andless thermal excitation is needed before tunneling occurs.Therefore the activation energy for a given trap level de-creases for higher electric fields. Fig. 4 shows the activationenergy as a function of electric field and trap level. For elec-tric fields smaller than �0.5 MV/cm TFE reduced to simplethermal SRH generation.

3. Experimental results

The goal of our experiments was to improve the reten-tion tail distribution of a given device without alteringdevice performance. Therefore, our approach is not inreduction of electrical field but in reduction of trap densityin sensitive areas of the array device, namely the G/D over-lap area. It is well known that fluorine has trap passivationcapabilities. However, fluorine shows a very complexbehavior in silicon which is still under intensive investiga-tion. Depending on F-dose and the way of incorporation,beneficial as well as detrimental effects on CMOS deviceshave been reported ([9] and references therein). In orderto benefit from the trap passivation capability without neg-ative effects on gate oxide reliability, F-implantation onlyinto LDD region has been proposed in [10]. To use fluorinefor DRAM retention tail improvement extensive experi-ments on 512 Mbit and 1 Gbit BEST DRAM [11] in110 nm technology have been carried out in this work. Ina series of systematic experiments the best way to incorpo-rate F in the integration flow has been investigated. There-fore fluorine has been incorporated in three ways (Fig. 5):maskless F-implant (a) before and (b) post gate spacer for-mation, (c) F-implant post spacer into BL-side only. The

Fig. 5. Experiments on 512 Mb BEST DRAM [11] to find the most beneficial way of fluorine incorporation. Fluorine was implanted (a) maskless pre gatespacer formation, (b) maskless post spacer formation and (c) with resist covered buried strap (BS) junction.

A. Weber et al. / Solid-State Electronics 51 (2007) 1534–1539 1537

detailed process flow is shown in Fig. 6 and all usedimplant conditions are summarized in Table 1. Also shownin Table 1 is the retention failcount (FC) at repair level nor-malized to processing without F-implant. This is a quanti-tative measure for retention tail improvement. The positionof F-implantation within the DRAM process flow turnedout to be of major importance for the retention improve-ment capability. For implant pre spacer (similar to [10])no net benefit on retention tail could be observed. We attri-bute this to potentially introduced additional implant dam-age within high electric field regions. In case of post spacer

Fig. 6. Process flow for F-implant experiments.

Table 1

Implantscheme

F-implant Retention FC normalizedto FC withoutF-implant

Energy(keV)

Dose(l/cm2)

(a) Pre spacer 10 3E13 0.9710 1E14 1.13

(b) Post spacer 10 3E13 1.0710 7E13 0.8210 1E14 0.6910 1.3E14 0.610 1.7E14 0.7310 2E14 0.7910 3E14 1.19

(c) BL-side only 10 1E14 0.95

implantation F is incorporated still close enough to the G/D overlap area to effectively passivate GIDL traps duringsubsequent annealing but potential damage is confined out-side the high field area. The electric field distribution for acut along the mid of the active area is shown in Fig. 7,where the F-implanted region is sketched for both implantconditions. For implantation into BL-side only as shown inFig. 5c, the fluorine is too far away from the relevant trapsites at the storage side junction and no retention improve-ment was seen. The dependency of FC reduction onimplant dose for the most beneficial implant position postgate spacer formation is shown in Fig. 8. With increasingdose the FC decreases by up to 40% at a dose of1.3E14 cm�2. Then additional damage or concentrationdependent negative effects of fluorine take over and theFC increases again. It has been verified by TEM that theF-implants did not alter bird’s beak and gate oxide thick-ness. Charge-to-breakdown (QBD) measurements revealedno degradation of gate oxide reliability either and influenceon device parameters as Vt and Ion is negligible.

4. Activation energy analysis

To further elucidate the effect of F-implantation postgate spacer formation, activation energies of worst reten-tion tail cells for chips without and with 10 keV and1E14 cm�2 F-implant have been measured. The obtainedcumulative distributions are shown in Fig. 9. Each datapoint in the plot represents the activation energy for theleakage current of one individual cell. All cells have a reten-tion time close to repair level at 85 �C. Note that each curveis normalized to its own total FC, the one for F-implantedchips containing �30% less cells than the distribution with-out implant. In order to visualize the effect of the F-implanton tail cells, a simple Monte Carlo simulation is done. In afirst step the two distributions of Fig. 9 are parameterizedusing a finite probability density mixture consisting oftwo Gaussian distributions as Ansatz:

F ½Ea� ¼ a � F 1½Eajl1; r1� þ ð1� aÞ � F 2½Eajl2; r2� ð9Þ

Fig. 7. Electrical field distribution of the node junction. The fluorine distribution as implanted is sketched. More implant damage in high electrical fieldregions is expected for F-implant pre spacer (1) compared to implant post spacer (2). Therefore the benefit of F-implant is canceled by additional implantdamage for the pre spacer case.

Fig. 8. Dependence of normalized retention failcount (FC) at repair levelon post spacer F-implant dose. The implant energy was 10 keV and thereference group is without F-implant.

Fig. 9. Activation energy distribution of worst retention tail cells. Allmeasured cells have retention times close to repair level.

0.4 0.45 0.5 0.55 0.6 0.650

1000

2000

3000

4000

5000

Activation Energy [eV]

Sam

ple

Num

ber

Simulation no FimplantSimulation 10 keV, 1E14 1/cm2, F

100 000 samples

30% = 70 000 samples

Fig. 10. Simulated activation energy histogram according to the measuredcumulative distributions of Fig. 5. The number of samples was chosenaccording to the observed retention improvement: 100,000 sampleswithout F-implant, 70,000 (= � 30%) for F-implanted.

1538 A. Weber et al. / Solid-State Electronics 51 (2007) 1534–1539

with

F j½Eajlj; rj� ¼Z Ea

0

1

rj

ffiffiffiffiffiffi2pp � e

�E0a�ljð Þ2

2r2j dE0a ð10Þ

Herein lj and rj correspond to median and standard devi-ation of the j-th sub distribution, respectively. a is theweighting factor between the two Gaussian distributionparts. By fitting the curves a statistical model is obtained.It can be seen from Fig. 9 that the fitted distributions,shown as solid lines in the plot, agree very well with thedata. Then two sets of random numbers according to thesemodels are generated and their histograms are shown inFig. 10. The retention tail improvement of 30% of the F-implanted group is taken into account by generating 30%less random numbers. It can be seen, that the reductionin the total FC originates mainly from a reduction of theGaussian shaped component at lower activation energies,which has been shown to represent GIDL fails due to itsvoltage and temperature dependence [4]. The Gaussianshaped curve at higher values corresponds to pn-leakagefrom outside the gate influenced area. Note that the FC

A. Weber et al. / Solid-State Electronics 51 (2007) 1534–1539 1539

in this energy range has almost not been changed by theF-implant. In total, it can be concluded that the effect ofF-implantation is to passivate traps close to the implantedarea. This again is confirmed by the fact, that implantationinto BL-side only did not lead to a tail improvement at all.For the optimal dose of 1.3E14 cm�2 the F-implant resultsin a reduction of the total FC at repair level by 40%.

5. Conclusion

The experimental results clearly support the model oftrap assisted GIDL being the major leakage path responsi-ble for retention tail. Implantation of fluorine into S/Dpost spacer formation directly addresses this leakage pathand retention FC could be reduced by up to 40%. The effectof fluorine on tail retention can be explained by passivationof traps in the G/D overlap area. Thereby fluorine seems tohave a very short effective area around the implantedregion as implied by the BL-side only implant experimentshowing no benefit. The passivation of GIDL traps is fur-thermore confirmed by measurement of the activationenergy distributions among worst retention tail cells ofF-implanted and standard memory components. For theF-implanted chips mainly cells with activation energies cor-responding to GIDL are removed from the distribution.F-implantation as proposed in this work is highly attractivefor future trench as well as stacked DRAM generations,since the retention tail can be improved without negativeside-effects on the device. In this work we have directlyaddressed the root cause of retention tail cells, namely elec-trically active traps, instead of plain lowering their impactvia the reduction of the electric field strength with all itsunwanted effects like sacrificing device performance.

Acknowledgements

We would like to thank the unit process and the productengineering group of Qimonda Dresden GmbH & Co.OHG for their valuable support.

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