DRAM Memory module 4GByte DDR4 SO-DIMM - … · DRAM Memory module 4GByte DDR4 SO-DIMM SHN04G64A1BD1SA-XXRT Preliminary Data sheet BU: DRAM ... 3.4 TEMPERATURE SENSOR WITH SPD EEPROM

Revision Change Nr. Creation-/ Change Date created / changed by Verified by Released by

0.9 - 2015-09-03 G. Elsener / U. Brandt U. Brandt

++ Swissbit AG, Confidential ++

DRAM Memory module 4GByte DDR4 SO-DIMM SHN04G64A1BD1SA-XXRT

Preliminary Data sheet

BU: DRAM

Date: 2015-09-03

Revision: 0.9

Fi le :

dataSHN04G64A1BD1SA_4GB_Rev

0.9.docx

Swissbit AG Swissbit Confidential Revision: 0.9

Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com dataSHN04G64A1BD1SA_4GB_Rev0.9.docx

Switzerland [email protected] Page 2 of 20

Contents

1 PRODUCT DESCRIPTION ................................................................................................................................................ 3

1.1 PRODUCT OVERVIEW ................................................................................................................................................ 3 1.2 KEY FEATURES ....................................................................................................................................................... 3 1.3 ENVIRONMENTAL REQUIREMENTS ............................................................................................................................... 4 1.4 ORDER INFORMATION .............................................................................................................................................. 4

2 MODULE CONFIGURATION ........................................................................................................................................... 4

2.1 ADDRESS CONFIGURATION ........................................................................................................................................ 4 2.2 PARAMETERS ......................................................................................................................................................... 4 2.3 MODULE DIMENSIONS ............................................................................................................................................. 4 2.4 PIN OUT ............................................................................................................................................................... 5

2.4.1 Pin Description ..................................................................................................................................... 6 2.5 FUNCTIONAL BLOCK DIAGRAMM ................................................................................................................................ 7

3 ELECTRICAL SPECIFICATION .......................................................................................................................................... 9

3.1 ABSOLUTE MAXIMUM DC RATINGS ............................................................................................................................. 9 3.2 OPERATING CONDITIONS .......................................................................................................................................... 9 3.3 DDR4IDD SPECIFICATIONS AND CONDITIONS ............................................................................................................. 10 3.4 TEMPERATURE SENSOR WITH SPD EEPROM ............................................................................................................. 11

3.4.1 Temperature Sensor with SPD EEPROM Operating Conditions ..................................................... 11 3.4.2 Temperature Sensor and EEPROM Serial Interface Timing ........................................................... 12

4 TIMING SPECIFICATION.............................................................................................................................................. 12

4.1 TIMING VALUES USED FOR IDD MEASUREMENT .......................................................................................................... 12

5 SERIAL PRESENCE DETECT MATRIX (SPD) .................................................................................................................. 13

6 PART NUMBER DECODER .......................................................................................................................................... 15

7 DIMENSION DRAWING ............................................................................................................................................... 16

8 SWISSBIT LOCATIONS ................................................................................................................................................ 17

9 REVISION HISTORY .................................................................................................................................................... 20




1 Product description

1.1 Product Overview This Swissbit module is a 260-pin DDR4 Small Outline Dual-In-line Memory Module (SO-DIMM) for industrial

embedded applications. The module uses DDR4 components which are organized as a 32Mbit x8 I/Os x

16banks (4 internal Bank Groups) devices. This DDR4 device high speed double-data-rate transfer rates of

up to 2400Mb/sec/pin (DDR4- 2400).

The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS,

Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset.

DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to

capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional

noise immunity for these signals and provide precise crossing points to capture input signals.

This DDR4 SDRAM Modules uses an Onboard I2C temperature sensor with integrated serial presence-detect

(SPD) EEPROM. This nonvolatile storage device contains 512 bytes. The first 384 bytes are utilized by the SO-

UDIMM manufacturer (Swissbit) to identify the module type and information, the module’s organization

and several timing parameters. The last 128 bytes are available to the end user.

1.2 Key Features

260-pin DDR4 Small Outline Dual-Inline memory module

4GByte (512M x 64)

Single Rank

Fast data transfer rate up to 2400 MT/s

VDD = 1.2V +0.06V / VDDQ = 1.2V +0.06V

VPP = 2.5V (NOM)

VDDSPD = 2.5V (NOM)

No ECC support

Fly-by-bus with termination for C/A & CLK bus

Onboard I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM

Finish process: OSP with 30µ” hard gold on contact fingers and chamfer

Based on DDR4 – SDRAM component SAMSUNG K4A4G085WD (4Gbit)

512Mx8 organization / 78ball FBGA Package

16 Banks (4 Bank Groups)

Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type

8bit prefetch architecture

Internal(self) calibration : Internal self calibration through ZQ pin

Data bus inversion (DBI) for data bus

Bi-directional Differential Data-Strobe

On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity

Average Refresh Period 7.8µs at lower than TCASE 85°C, 3.9µs at 85°C < TCASE < 95°C

Internal VREF for data inputs

External VPP for DRAM Activating Power




1.3 Environmental Requirements

1.4 Order information

*Operating temperature

Commercial-Grade (blank) 0°C to 70°C

E-Grade (E) 0°C to 85°C

W-Grade (W) -40°C to 85°C

2 Module configuration

2.1 Address Configuration

Organization Device

configuration

Row

Address

Column

Address

Bank

Address

Bank Group

Address

Module

Rank address

512M x 64bit 512M x 8bit 15 10 BA0,BA1 BG0,BG1 CS0#

2.2 Parameters

Part number Density Transfer rate Clock Cycle/Data bit rate Latencies

SHN04G64A1BD1SA-FPRT 4GByte 17.0 GByte/s 0.938ns / 2133MT/s 15-15-15

SHN04G64A1BD1SA-GSRT 4GByte 19.2 GByte/s 0.833ns / 2400MT/s 17-17-17

2.3 Module Dimensions

Dimensions in millimeter

Length: 69.6 High: 30.0 Thickness: 3.70 (max.)

Dimension drawing

Operating Humidity 10% to 90% relative humidity, non condensing

Operating Pressure 105 to 69kPa (up to 10000 ft.)

Storage Temperature -55°C to 100°C

Storage Humidity 5% to 95% relative humidity, non condensing

Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C

Part number Comment

SHN04G64A1BD1SA-FPRT 4GB 1Rx8 PC4-2133P-SA1-10 (com.Temp.)*

SHN04G64A1BD1SA-GSRT 4GB 1Rx8 PC4-2400S-SA1-10 (com.Temp.)*




2.4 Pin out

FRONT SIDE PIN PIN LABEL PIN PIN LABEL PIN PIN LABEL PIN PIN LABEL

1 VSS 67 DQ29 133 A1 197 VSS

3 DQ5 69 VSS 135 VDD 199 DM5_n / DBI5_n

5 VSS 71 DQ25 137 CK0_t 201 VSS

7 DQ1 73 VSS 139 CK0_c 203 DQ46

9 VSS 75 DM3_n / DBI3_n 141 VDD 205 VSS

11 DQS0_c 77 VSS 143 PARITY 207 DQ42

13 DQS0_t 79 DQ30 KEY 209 VSS

15 VSS 81 VSS 145 BA1 211 DQ52

17 DQ7 83 DQ26 147 VDD 213 VSS

19 VSS 85 VSS 149 CS0_n 215 DQ49

21 DQ3 87 NC (CB5) 151 A14 / WE_n 217 VSS

23 VSS 89 VSS 153 VDD 219 DQS6_c

25 DQ13 91 NC (CB1) 155 ODT0 221 DQS6_t

27 VSS 93 VSS 157 NC (CS1_n) 223 VSS

29 DQ9 95 NC (DQS8_c) 159 VDD 225 DQ55

31 VSS 97 NC (DQS8_t) 161 NC (ODT1) 227 VSS

33 DM1_n / DBI1_n 99 VSS 163 VDD 229 DQ51

35 VSS 101 NC (CB2) 165 NC (CS3_n) 231 VSS

37 DQ15 103 VSS 167 VSS 233 DQ61

39 VSS 105 NC (CB3) 169 DQ37 235 VSS

41 DQ10 107 VSS 171 VSS 237 DQ56

43 VSS 109 CKE0 173 DQ33 239 VSS

45 DQ21 111 VDD 175 VSS 241 DM7_n / DBI7_n

47 VSS 113 BG1 177 DQS4_c 243 VSS

49 DQ17 115 BG0 179 DQS4_t 245 DQ62

51 VSS 117 VDD 181 VSS 247 VSS

53 DQS2_c 119 A12 183 DQ38 249 DQ58

55 DQS2_t 121 A9 185 VSS 251 VSS

57 VSS 123 VDD 187 DQ34 253 SCL

59 DQ23 125 A8 189 VSS 255 VDDSPD

61 VSS 127 A6 191 DQ44 257 VPP

63 DQ19 129 VDD 193 VSS 259 VPP

65 VSS 131 A3 195 DQ40

BACK SIDE

PIN PIN LABEL PIN PIN LABEL PIN PIN LABEL PIN PIN LABEL

2 VSS 68 VSS 134 EVENT_n 198 DQS5_c

4 DQ4 70 DQ24 136 VDD 200 DQS5_t

6 VSS VSS 138 CK1_t 202 VSS

8 DQ0 74 DQS3_c 140 CK1_c 204 DQ47

10 VSS 76 DQS3_t 142 VDD 206 VSS

12 DM0_n / DBI0_n 78 VSS 144 A0 208 DQ43

14 VSS 80 DQ31 KEY 210 VSS

16 DQ6 82 VSS 146 A10 / AP 212 DQ53

18 VSS 84 DQ27 148 VDD 214 VSS

20 DQ2 86 VSS 150 BA0 216 DQ48

22 VSS 88 CB4 152 A16 / RAS_n 218 VSS

24 DQ12 90 VSS 154 VDD 220 DM6_n / DBI6_n

26 VSS 92 NC (CB0) 156 A15 / CAS_n 222 VSS

28 DQ8 94 VSS 158 A13 224 DQ54

30 VSS 96 NC (DM8_n / DBI8_n) 160 VDD 226 VSS

32 DQS1_c 98 VSS 162 NC (C0, CS2_n) 228 DQ50

34 DQS1_t 100 NC (CB6) 164 VREFCA 230 VSS

36 VSS 102 VSS 166 SA2 232 DQ60

38 DQ14 104 NC (CB7) 168 VSS 234 VSS

40 VSS 106 VSS 170 DQ36 236 DQ57

42 DQ11 108 RESET_n 172 VSS 238 VSS

44 VSS 110 NC (CKE1) 174 DQ32 240 DQS7_c

46 DQ20 112 VDD 176 VSS 242 DQS7_t

48 VSS 114 ACT_n 178 DM4_n / DBI4_n 244 VSS

50 DQ16 116 ALERT_n 180 VSS 246 DQ63

52 VSS 118 VDD 182 DQ39 248 VSS

54 DM2_n / DBI2_n 120 A11 184 VSS 250 DQ59

56 VSS 122 A7 186 DQ35 252 VSS

58 DQ22 124 VDD 188 VSS 254 SDA

60 VSS 126 A5 190 DQ45 256 SA0

62 DQ18 128 A4 192 VSS 258 VTT

64 VSS 130 VDD 194 DQ41 260 SA1

66 DQ28 132 A2 196 VSS

Note: signal in brackets NC (Sig) may be routed to the socket connector, but is not used on the module




Pin Description

Symbol Function

CK0_t – CK1_t SDRAM clocks (positive line of differential pair)

CK0_c – CK1_c SDRAM clocks (negative line of differential pair)

CS0_n Rank select lines

CKE0 SDRAM clock enable

ODT0 On-Die Termination

ACT_n Activate command signal

RAS_n / A16 CAS_n / A15 WE_n / A14

Command inputs / Address bits 16:14 for activate command

A10 / AP SDRAM address input / autoprecharge Bit

A0 – A9, A11 – A13

SDRAM address inputs with single function

BA0 – BA1 SDRAM bank address inputs

BG0 – BG1 SDRAM bank group address

DQ0 – DQ63 DIMM data bus

DM0_n – DM7_n/ DBI0_n – DBI7_n

SDRAM data masks / data bus inversion: function defined by mode register

DQS0_t – DQS7_t Data strobe, positive line

DQS0_c – DQS7_c Data strobe, negative line (only used when differential data strobe mode is enabled)

VDD SDRAM I/O & core power supply (1.2 +0.06V)

VPP SDRAM activating power supply

VREFCA SDRAM command/address reference supply

VTT Termination supply for the address, command and control bus

VSS Power supply return (ground)

VDDSPD Power supply for serial presence detect (SPD)

SCL Serial clock for SPD

SDA Serial data out for SPD

SA0 – SA2 SPD address inputs

PARITY SDRAM parity input

ALERT_n SDRAM ALERT (CRC /CA parity error)

RESET_n Set SDRAM’s to a known state

EVENT_n TS signals a thermal event has occurred

NC No Connection




2.5 Functional Block Diagram

4GByte, 512Mx64 Module (Populated as 1rank module with x8 DDR4 SDRAM’s)







3 Electrical Specification

3.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE VDD Voltage on VDD pin relative to VSS -0.3 ~ 1.5 V 1,3

VDDQ Voltage on VDDQ pin relative to VSS -0.3 ~ 1.5 V 1,3

VPP Voltage on VPP pin relative to VSS -0.3 ~ 3.0 V 4

VIN, VOUT Voltage on any pin except VREFCA to VSS -0.3 ~ 1.5 V 1,3

TSTG Storage Temperature -55 to +100 °C 1,2

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

3. VDD and VDDQ must be within 300 mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than

500 mV; VREFCA may be equal to or less than 300 mV 4. VPP must be equal or greater than VDD/VDDQ at all times.

3.2 Operating Conditions

NOTE:

1. VDDQ tracks with VDD; VDDQ and VDD are tied together.

2. VPP must be greater than or equal to VDD at all times.

3. VREFCA must not be greater than 0.6 x VDD. When VDD is less than 500mV, VREF may be less than or equal to 300mV.

4. VTT termination voltages in excess of the specification limit adversely affect the voltage margins of command and address signals and reduce timing

margins.

5. Multiply by the number of DRAM die on the module.

6. Tied to ground. Not connected to edge connector.

Symbol Parameter Rating

Unit NOTE MIN. NOM. MAX.

VDD Supply Voltage 1.14 1.2 1.26 V 1

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1

VPP Peak-to-Peak Voltage 2.375 2.5 2.75 V 2

VREFCA(DC) Input reference voltage

command/

address bus

0.49 × VDD 0.5 × VDD 0.51 × VDD V 3

IVTT Termination reference

current from VTT –750 – 750 mA

VTT Termination reference

voltage (DC) –

command/address bus

0.49 × VDD -

20mV 0.5 × VDD

0.51 × VDD +

20mV V 4

II Input leakage current; any

input excluding ZQ;

0V < VIN < 1.1V

–2.0 – 2.0 µA 5

II/O DQ leakage; 0V < Vin < VDD –4.0 – 4.0 µA 5

II Input leakage current; ZQ –3.0 – 3.0 µA 5,6

IOZpd Output leakage current;

VOUT = VDD; DQ is disabled – – 5.0 µA

IOZpu

Output leakage current; VOUT =VSS; DQ and ODT

are disabled; ODT is disabled

with ODT input HIGH

– – 5.0 µA

IVREFCA

VREFCA leakage; VREFCA = VDD/2 (after DRAM is

initialized)

–2.0 – 2.0 µA 5




3.3 DDR4 IDD / IPP Specifications and Conditions

Parameter/Conditions Symbol DDR4 2133 DDR4 2400 Unit

IDD max IPP max IDD max IPP max Operating One Bank Active-Precharge Current (AL=0)

IDD0 267 32 276 32 mA

Operating One Bank Active-Precharge Current (AL=CL-1)

IDD0A 293 32 311 32 mA

Operating One Bank Active-Read-

Precharge Current (AL=0) IDD1 347 32 364 32 mA

Operating One Bank Active-Read-Precharge Current (AL=CL-1)

IDD1A 373 32 400 32 mA

Precharge Standby Current (AL=0) IDD2N 133 24 151 24 mA Precharge Standby Current (AL=CL-1) IDD2NA 187 24 204 24 mA Precharge Standby ODT Current IDD2NT 151 24 160 24 mA Precharge Standby Current with CAL

enabled IDD2NL 116 24 124 24 mA

Precharge Standby Current with Gear Down mode enabled

IDD2NG 160 24 160 24 mA

Precharge Standby Current with DLL

disabled IDD2ND 116 24 124 24 mA

Precharge Standby Current with CA parity

enabled IDD2NP 160 24 160 24 mA

Precharge Power-Down Current IDD2P 89 24 89 24 mA Precharge Quiet Standby Current IDD2Q 124 24 142 24 mA Active Standby Current IDD3N 240 24 258 24 mA Active Standby Current (AL=CL-1) IDD3NA 284 24 302 24 mA Active Power-Down Current IDD3P 124 24 133 24 mA Operating Burst Read Current IDD4R 764 24 836 24 mA Operating Burst Read Current (AL=CL-1) IDD4RA 791 24 871 24 mA Operating Burst Read Current with Read

DBI IDD4RB 782 24 853 24 mA

Operating Burst Write Current IDD4W 622 24 649 24 mA Operating Burst Write Current (AL=CL-1) IDD4WA 649 24 693 24 mA Operating Burst Write Current with Write

DBI IDD4WB 622 24 658 24 mA

Operating Burst Write Current with Write CRC

IDD4WC 560 24 596 24 mA

Operating Burst Write Current with CA

Parity IDD4WP 649 24 702 24 mA

Burst Refresh Current (1X REF) IDD5B 1227 144 1244 144 mA Burst Refresh Current (2X REF) IDD5F2 1031 120 1031 120 mA Burst Refresh Current (4X REF) IDD5F4 782 88 782 88 mA Self Refresh Current: Normal Temperature Range

IDD6N 98 40 98 32 mA

Self-Refresh Current: Extended

Temperature Range IDD6E 133 40 133 32 mA

Operating Bank Interleave Read Current IDD7 1182 60 1200 60 mA Maximum Power Down Current IDD8 62 16 62 16 mA Note: De-activated ranks are considered to be in IDD2N mode




3.4 Temperature Sensor with SPD EEPROM

3.4.1 Temperature Sensor with SPD EEPROM Operating Conditions

Parameter/Conditions Symbol Min Nom Max Unit Supply voltage VDDSPD - 2.5 - V

Input low voltage: logic 0; all inputs VIL -0.5 -

VDDSPD ×

0.3 V

Input high voltage: logic 1; all inputs VIH

VDDSPD × 0.7

- VDDSPD +

0.5 V

Output low voltage: 3mA sink current VDDSPD >

2V VOL - - 0.4 V

Input leakage current: (SCL, SDA) VIN = VDDSPD

or VSSSPD ILI - - +5 µA

Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z

ILO - - +5 µA




3.4.2 Temperature Sensor and EEPROM Serial Interface Timing

Parameter/Conditions Symbol Min Max Unit Clock frequency fSCL 10 1000 kHz

Clock pulse width HIGH time tHIGT 260 - ns

Clock pulse width LOW time tLOW 500 - ns

Detect clock LOW timeout tTIMEOUT 25 35 ms

SDA rise time tR - 120 ns

SDA fall time tF - 120 ns

Data-in setup time tSU:DAT 50 - ns

Data-in hold time tHD:DI 0 - ns

Data out hold time tHD:DAT 0 - ns

Start condition setup time tSU:STA 260 - ns

Start condition hold time tHD:STA 260 - ns

Stop condition setup time tSU:STO 260 - ns

Time the bus must be free before a new

transition

can start

tBUF 500 - ns

Write time tW - 5 ms

Warm power cycle time off tPOFF 1 - ms

Time from power on to first command tINIG 10 - ms

4 Timing Specification

4.1 Timing Values used for IDD Measurement

IDD MEASUREMENT CONDITIONS Symbol DDR4 2400 DDR4 2133 Unit

tCK (min) 0.833 0.938 ns

CAS Latency 17 15 tCK

tRCD (min) 14.16 14.06 ns

tRP (min) 14.16 14.06 ns

tRAS (min) 32 33 ns

tRAS (max) 9 x tREFI 9 x tREFI ns

tRC (min) 46.16 47.06 ns

tRFC1 (min) 260 260 ns



tREFI 7.8

µs 3.9




5 Serial Presence Detect Matrix (SPD)

BYTE BYTE DESCRIPTION VALUE

DDR4 2400 DDR4 2133

0 SPD BYTES USE/TOTAL BYTES AVAILABLE/CRC COVERAGE 0x23

1 SPD REVISION 0x10

2 DRAM DEVICE TYPE 0x0C

3 MODULE TYPE (FORM FACTOR) 0x03

4 SDRAM DEVICE DENSITY BANKS 0x84

5 SDRAM DEVICE ADDRESSING 0x19

6 SDRAM DEVICE TYPE (ARCHITECURE) 0x00

7 SDRAM DEVICE OPTIONAL FEATURES 0x08

8 SDRAM DEVICE THERMAL REFRESH OPTIONS 0x00

9 OTHER SDRAM OPTIONAL FEATURES 0x40

10 BYTE 10 RESERVED 0x00

11 NOMINAL MODULE VOLTAGE (VDD) 0x03

12 MODULE ORG. (PACKAGE RANKS DEVICE WIDTH) 0x01

13 MODULE MEMORY BUS WIDTH 0x03

14 MODULE THERMAL SENSOR SUPPORT 0x80



17 TIMEBASES (MTB FTB) 0x00

18 SDRAM device tCKMIN 0x07 0x08

19 SDRAM device Tckmax 0x0D 0x0C

20 CAS Latencies Supported, First Byte 0xF8

21 CAS Latencies Supported, Second Byte 0x0F 0x03

22 CAS Latencies Supported, Third Byte 0x00

23 CAS Latencies Supported, Fourth Byte 0x00

24 Minimum CAS Latency Time (tAAmin) 0x6E

25 Minimum RAS to CAS Delay Time (tRCDmin) 0x6E

26 Minimum Row Precharge Delay Time (tRPmin) 0x6E

27 Upper Nibbles for tRASmin and tRCmin 0x11

28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 0x00 0x08

29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte

0x6E 0x76

30 Minimum Refresh Recovery Delay Time (tRFC1min), LSB 0x20

31 Minimum Refresh Recovery Delay Time (tRFC1min), MSB 0x08





36 Minimum Four Activate Window Time (tFAWmin), Most Significant Nibble 0x00

37 Minimum Four Activate Window Time (tFAWmin), Least Significant Byte 0xA8

38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group

0x1E

39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group 0x28 0x2B

40 Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group 0x28 0x2B

41-59 Reserved -- must be coded as 0x00 0x00




BYTE BYTE DESCRIPTION VALUE

DDR4 2400 DDR4 2133

60 Connector to SDRAM Bit Mapping (DQ0-DQ3) 0x0C

61 Connector to SDRAM Bit Mapping (DQ4-DQ7) 0x2B

62 Connector to SDRAM Bit Mapping (DQ8-DQ11) 0x2D

63 Connector to SDRAM Bit Mapping (DQ12-DQ15) 0x04





68 Connector to SDRAM Bit Mapping (CB0-CB3) 0x00

69 Connector to SDRAM Bit Mapping (CB4-CB7) 0x00


71 Connector to SDRAM Bit Mapping (DQ36-DQ39) 0x0B







78-116 Reserved -- must be coded as 0x00 0x00

117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group

0x00 0x83

118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group

0x9C 0xB5

119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group

0xB5 0xCE

120 Fine Offset for Minimum Activate to Activate/Refresh Delay Time (tRCmin) 0x00

121 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) 0x00

122 Fine Offset for Minimum RAS to CAS Delay Time (tRCDmin) 0x00

123 Fine Offset for Minimum CAS Latency Time (tAAmin) 0x00

124 Fine Offset for SDRAM Maximum Cycle Time (tCKAVG max) 0xE7 0x00

125 Fine Offset for SDRAM Minimum Cycle Time (tCKAVG min) 0xD6 0xC2

126 CRC for Base Configuration Section, Least Significant Byte 0x5B 0x80

127 CRC for Base Configuration Section, Most Significant Byte 0xFB 0x26

128 Raw Card Extension, Module Nominal Height 0x0F

129 Module Maximum Thickness 0x11

130 Reference Raw Card Used 0x20

131 Address Mapping from Edge Connector to DRAM 0x00

132-253 Reserved -- Must be coded as 0x00 0x00

254 CRC for Module Specific Section, Least Significant Byte 0xEF

255 CRC for Module Specific Section, Most Significant Byte 0x55

256-319 RESERVED 0x00

320 Module Manufacturer-ID Code (LSB) 0x80

321 Module Manufacturer-ID Code (MSB) 0xDA

322 Module Manufacturer-Location X

323-324 Module Manufacturing date X

325-328 Module Serial Number X

329-348 Module Part Number SHN04G64A1BD1SA…

349 Module Revision Code 0x00

350 DRAM Manufacturer’s ID Code (LSB) 0x80

351 DRAM Manufacturer’s ID Code (MSB) 0xCE

352 DRAM Stepping 0x00

353-381 Module Manufacturer’s specific Data 0x00

382-383 RESERVED 0x00

384-511 End User Reserved 0x00




6 Part Number Decoder

S H N 04G 64 A1 B D 1 SA - XX X R T

1 2 3 4 5 6 7 8 9 10 11 12 13 14

1 S Swissbit OEM Module

2 H DDR4 technology

3 N 260pin SO-DIMM form factor

4 04G 4GByte capacity

5 64 64bit bus width (without ECC)

6 A1 PCB-type and revision

7 B DRAM organization (x8)

8 D DRAM DIE revision (D)

9 1 single physical module rank

10 SA DRAM vendor (SAMSUNG)

-

11 XX

Module speed-grade: FP = 2133MT/s CL15

GS = 2400MT/s CL17

12

X

Module operating temperature: Empty = commercial

E = E-Grade (0°C – 85°C)

W = W-Grade (-40°C – 85°C)

13 R RoHs compliant

14 T onboard I2C thermal sensor




7 Dimension drawing




8 Swissbit Locations

SWISSBIT AG

INDUSTRIESTRASSE 4

CH-9552 BRONSCHHOFEN

TEL +41 71 913 03 03

FAX +41 71 913 03 15

SWISSBIT GERMANY AG

WOLFENER STRASSE 36

D-12681 BERLIN

TEL +49 30 93 69 54 0

FAX +49 30 93 69 54 55

SWISSBIT NA

1117 E PLAZA DRIVE UNIT E SUITE 105/106

EAGLE, IDAHO 83616

TEL +1 208 938 4525

FAX +1 914 935 9865

SWISSBIT JAPAN CO., LTD.

3F, 2-1-24 KOENJI-KITA

SUGINAMI-KU, TOKYO 166-0002

JAPAN

TEL +81 3 5356 3511

FAX +81 3 5356 3512




RoHS and WEEE update from Swissbit Dear Valued Customer,

We at Swissbit place great value on the environment and thus pay close attention to the diverse aspects of

manufacturing environmentally and health friendly products. The European Parliament and the Council of

the European Union have published two Directives defining a European standard for environmental

protection. This states that Solid State Drives must comply with both Directives in order for them to be sold

on the European market:

RoHS – Restriction of Hazardous Substances

WEEE – Waste Electrical and Electronic Equipment

Swissbit would like to take this opportunity to inform our customers about the measures we have

implemented to adapt all our products to the European norms.

What is the WEEE Directive (2012/19/EU)?

The Directive covers the following points:

Prevention of WEEE

Recovery, recycling and other measures leading to a minimization of wastage of electronic

and electrical equipment

Improvement in the quality of environmental performance of all operators involved in the

EEE life cycle, as well as measures to incorporate those involved at the EEE waste disposal

points

What are the key elements?

The WEEE Directive covers the following responsibilities on the part of producers:

Producers must draft a disposal or recovery scheme to dispose of EEE correctly.

Producers must be registered as producers in the country in which they distribute the goods.

They must also supply and publish information about the EEE categories.

Producers are obliged to finance the collection, treatment and disposal of WEEE.

Inclusion of WEEE logos on devices

In reference to the Directive, the WEEE logo must be printed directly on all devices that have sufficient

space. «In exceptional cases where this is necessary because of the size of the product, the symbol of the

WEEE Directive shall be printed on the packaging, on the instructions of use and on the warranty»

(WEEE Directive 2012/19/EU)

When does the WEEE Directive take effect?

The Directive came into effect internationally on July 04, 2012.

What is RoHS (2011/65/EU)?

The goals of the Directive are to:

Place less of a burden on human health and to protect the environment by restricting the

use of hazardous substances in new electrical and electronic devices

To support the WEEE Directive (see above)

RoHS enforces the restriction of the following 6 hazardous substances in electronic and electrical devices:

Lead (Pb) – no more than 0.1% by weight in homogeneous materials

Mercury (Hg) – no more than 0.1% by weight in homogeneous materials

Cadmium (Cd) – no more than 0.01% by weight in homogeneous materials

Chromium (Cr6+) – no more than 0.1% by weight in homogeneous materials

PBB, PBDE – no more than 0.1% by weight in homogeneous materials




Swissbit is obliged to minimize the hazardous substances in the products.

According to part of the Directive, manufacturers are obliged to make a self-declaration for all devices with

RoHS. Swissbit carried out intensive tests to comply with the self-declaration. We have also already taken

steps to have the analyses of the individual components guaranteed by third-party companies.

Swissbit carried out the following steps during the year with the goal of offering our customers products

that are fully compliant with the RoHS Directive.

Preparing all far-reaching directives, logistical enhancements and alternatives regarding

the full understanding and introduction of the RoHS Directive’s standards

Checking the components and raw materials:

o Replacing non-RoHS-compliant components and raw materials in the supply chain

o Cooperating closely with suppliers regarding the certification of all components and

raw materials used by Swissbit

Modifying the manufacturing processes and procedures

o Successfully adapting and optimizing the new management-free integration process

in the supply chain

o Updating existing production procedures and introducing the new procedures to

support the integration process and the sorting of materials

Carrying out the quality process

o Performing detailed function and safety tests to ensure the continuous high quality

of the Swissbit product line

When does the RoHS Directive take effect?

As of June 08, 2011 only new electrical and electronic devices with approved quantities of RoHS will be put

on the market.

When will Swissbit be offering RoHS-approved products?

Swissbit’s RoHS-approved products are available now. Please contact your Swissbit contact person to find

out more about exchanging your existing products for RoHS-compliant devices.

For your attention

We understand that packaging and accessories are not EEE material and are therefore not subject to the

WEEE or RoHS Directives.

Contact details:

Swissbit AG

Industriestrasse 4

CH-9552 Bronschhofen

Tel: +41 71 913 03 03 – Fax: +41 71 913 03 15

E-mail: [email protected] – Website: www.swissbit.com

mailto:[email protected]




9 Revision History Date Revision Revision Details

2015-09-03 0.9 First Revision

Table 1: Document Revision History

Documents

DRAM Memory module 4GByte DDR4 SO-DIMM - … · DRAM Memory module 4GByte DDR4 SO-DIMM SHN04G64A1BD1SA-XXRT Preliminary Data sheet BU: DRAM ... 3.4 TEMPERATURE SENSOR WITH SPD EEPROM