DRACULA Standalone Verification DRACULA Standalone …read.pudn.com/downloads109/doc/452371/Cadence及MEDICI... · 2002-12-20 · Educational Services Group (ESG) February 16, 1995

Educational Services Group (ESG)February 16, 1995

DRACULA Standalone VerificationTraining ManualVersion 4.2

Educational Services Group (ESG)February 16, 1995

DRACULA Standalone VerificationTraining ManualVersion 4.2

1990-95 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

No part of this publication may be reproduced in whole or in part by any means (including photocopying or storage in an informationstorage/retrieval system) or transmitted in any form or by any means without prior written permission from Cadence Design Systems, Inc.(Cadence).

Information in this document is subject to change without notice and does not represent a commitment on the part of Cadence. The informationcontained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used onlyby Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth insuch agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy orusefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any thirdparty rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.

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Unpublished – rights reserved under the copyright laws of the United States.

In this manual the screen representation of “Framework” and any reference to it connotes Design Framework II software.

Other TrademarksFrameMaker is a registered trademark of Frame Technology Corporation.UNIX is a registered trademark, licensed exclusively by X/Open Company Ltd.X Window System is a trademark of the Massachusetts Institute of Technology.

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Table of Contents DRACULA Standalone Verification

2/16/95 Cadence Design Systems, Inc. iii

Table of Contents

DRACULA Standalone Verification

Module 1 Introduction to DRACULA

Course Schedule....................................................................................................................................... 1-6

Module 2 Cadence Basics

X Windows and Motif ............................................................................................................................. 2-4Using the Motif Window Manager .................................................................................................... 2-6Expand and Shrink Motif Windows .................................................................................................. 2-8

Starting Cadence Software..................................................................................................................... 2-10Opening a Design............................................................................................................................. 2-12Command Interpreter Window (CIW)............................................................................................. 2-14Form Controls .................................................................................................................................. 2-16Types of Forms ................................................................................................................................ 2-18Technology File ............................................................................................................................... 2-20

Lab 2-1. Starting Cadence Software ...................................................................................................... 2-21Lab 2-2. Opening Designs ..................................................................................................................... 2-21Lab 2-3. Setting Display Options........................................................................................................... 2-21

Module 3 Dracula Overview and Operation

Program Overview................................................................................................................................... 3-4Program Flow........................................................................................................................................... 3-6

Finding DRC Errors with DFII ........................................................................................................ 3-14Finding DRC Errors with InQuery .................................................................................................. 3-16Using the DRC Summary File ......................................................................................................... 3-18

Lab 3-1. Run DRC and Analyze Errors ................................................................................................. 3-19Electrical Rules Checking................................................................................................................ 3-22Types of ERC Checks...................................................................................................................... 3-24Using the ERC Error Summary ....................................................................................................... 3-26

Lab 3-3. Run ERC and Find Errors ....................................................................................................... 3-27Layout Versus Schematic ................................................................................................................ 3-30Preparing Netlists............................................................................................................................. 3-32

Lab 3-4. Run LVS and Find Errors........................................................................................................ 3-43

Module 4 Dracula Command File Structure

Global Program Information.................................................................................................................... 4-4

DRACULA Standalone Verification Table of Contents

iv Cadence Design Systems, Inc. 2/16/95

Database Layer Information .................................................................................................................... 4-6

Module 5 Layer Processing

Layer Processing Commands................................................................................................................... 5-4Logical Commands ............................................................................................................................ 5-6Selecting Shapes ................................................................................................................................ 5-8Sizing Shapes ................................................................................................................................... 5-14

Module 6 Design Rule Checking

DRC Applications.............................................................................................................................. 6-4DRC Commands ................................................................................................................................ 6-6DRC Command Selection Operators ................................................................................................. 6-8DRC Command Modifiers............................................................................................................... 6-10DRC Command Modifiers............................................................................................................... 6-12Width-factored Spacing Rules ......................................................................................................... 6-14Well Tie Checking ........................................................................................................................... 6-16Data Integrity Checking................................................................................................................... 6-18Gate Dimension Checking ............................................................................................................... 6-20

Speed Improvements for Hierarchical DRC.......................................................................................... 6-22Process Specification for DRC Lab ....................................................................................................... 6-24Lab 6-1. Create a DRC Command File from the Process Specification................................................ 6-25

Module 7 Designed Device Extraction

General Extraction Steps.......................................................................................................................... 7-4Labeling Your Design........................................................................................................................ 7-8Defining Text ................................................................................................................................... 7-10

Defining Connectivity............................................................................................................................ 7-12Extracting MOSFETs............................................................................................................................. 7-14Extracting PNPs..................................................................................................................................... 7-16Extracting NPNs .................................................................................................................................... 7-18Extracting Resistors ............................................................................................................................... 7-20Extracting Capacitors............................................................................................................................. 7-22Lab 7-1. Create, Run and Debug your own Extraction Command File................................................. 7-23


2/16/95 Cadence Design Systems, Inc. v

Module 8 ERC Commands and Applications

Checking Opens and Shorts ............................................................................................................... 8-4Finding Floating Wells ...................................................................................................................... 8-6Soft-connect Checking....................................................................................................................... 8-8Finding Improper Device Connections............................................................................................ 8-10

Lab 8-1. Create and Execute an ERC Command File ........................................................................... 8-11

Module 9 LVS Commands and Applications

LVS Structure Recognition...................................................................................................................... 9-4Device Reduction Using Structures ......................................................................................................... 9-6Primitive Structures ................................................................................................................................. 9-8Second-level Structures ......................................................................................................................... 9-10Second-level Structures ......................................................................................................................... 9-12Gate-level Structures.............................................................................................................................. 9-14Complex Second-level Structures.......................................................................................................... 9-16Complex Second-level Structures.......................................................................................................... 9-18Complex Second-level Structures.......................................................................................................... 9-20Complex Gate Structures ....................................................................................................................... 9-22Complex Gate Structures ....................................................................................................................... 9-24LVS Capability Overview...................................................................................................................... 9-26

LVS Comparison Behavior.............................................................................................................. 9-28LVS Comparison Behavior.............................................................................................................. 9-30LVS Comparison Behavior.............................................................................................................. 9-32LVS Parameter Comparison ............................................................................................................ 9-34

LVS Capability Overview...................................................................................................................... 9-36LVS Error Report................................................................................................................................... 9-38Header and LVSNET Information......................................................................................................... 9-40LVS Device Reduction .......................................................................................................................... 9-42Layout Reduction and Options Summary.............................................................................................. 9-44Schematic Reduction Summary............................................................................................................. 9-46Main Body LVS Report ......................................................................................................................... 9-48Initial Correspondence Node Pairs ........................................................................................................ 9-50Main Body LVS Report ......................................................................................................................... 9-52LVS Repeat Summary ........................................................................................................................... 9-60LVS Debugging Methods ...................................................................................................................... 9-62LVS Internal Flow ................................................................................................................................. 9-64Texting is Everything............................................................................................................................. 9-66Device Reduction................................................................................................................................... 9-70Correspondence Points........................................................................................................................... 9-72


vi Cadence Design Systems, Inc. 2/16/95

Discrepancy Points Analysis.................................................................................................................. 9-74Discrepancy Points Analysis.................................................................................................................. 9-76Methods Summary................................................................................................................................. 9-78Lab 9-1. Create an LVS Command File ................................................................................................ 9-79

Module 10 Parasitic Device Extraction

Parasitic Extraction Overview ............................................................................................................... 10-4General Parasitic Extraction ................................................................................................................ 10-10Command File for Parasitic Resistance Extraction (PRE) .................................................................. 10-14Second Phase of PRE Command File.................................................................................................. 10-16Second Phase (continued) .................................................................................................................... 10-18Netlist Formatting Options .................................................................................................................. 10-2010-1. Create and Execute a Command File for General Parasitic Extraction...................................... 10-2110-2. Execute and Modify a Command File for Parasitic Resistance Extraction................................ 10-21

Appendix A Dracula Flat Master Command File

Appendix B Command Quick Reference

Layer Processing Commands.............................................................................................................B-1

Appendix C Hierarchical Dracula

DRC Hierarchy Concept ..........................................................................................................................C-4Hierarchical DRC Error Output .........................................................................................................C-6

Multi-level DRC Operation .....................................................................................................................C-8LVS Hierarchical Concept...............................................................................................................C-10Automatic Texting of Cells for Hierarchical LVS...........................................................................C-14

Lab C-1. Running Hierarchical DRC.....................................................................................................C-15

Appendix D LVS Error Types

Error Type Overview .............................................................................................................................. D-4Error Type 1............................................................................................................................................ D-6Error Type 2............................................................................................................................................ D-8Error Type 3.......................................................................................................................................... D-10Error Type 4.......................................................................................................................................... D-12Error Type 5.......................................................................................................................................... D-14Error Type 6.......................................................................................................................................... D-16Error Type 7.......................................................................................................................................... D-18Error Type 8.......................................................................................................................................... D-20Error Type 9.......................................................................................................................................... D-22


2/16/95 Cadence Design Systems, Inc. vii

Error Type 10........................................................................................................................................ D-24Error Type 11........................................................................................................................................ D-26Error Type 12........................................................................................................................................ D-28Error Type 13........................................................................................................................................ D-30Error Type 14........................................................................................................................................ D-32Error Type 15........................................................................................................................................ D-34


viii Cadence Design Systems, Inc. 2/16/95

Introduction to DRACULA 1-1

Introduction to DRACULA

Objectives

■ Learn Operation and Error Resolution with Dracula

■ Learn Structure and Syntax of Dracula Command Files

■ Learn Applications of Dracula Command Files

2/9/95 Cadence Design Systems, Inc. 1-2

Terms and Definitions

Command File File containing rules and commands used by Dracula


For More Information

Manual Topic Manual Name

Layout editing Virtuoso Layout Editor

Dracula commands Dracula (Volumes 1, 2 & 3)

General/database information Design Framework II

Cadence administration Administration User Guide

Technology File Reference



Course Schedule

Day 1

Introduction

Cadence Basics

Dracula Tool Overview

DRC Operation, Labs

Lunch

ERC Operation, Labs

LVS Operation, Labs


Course Schedule


Course Schedule

Day 2

Dracula Command File Structure Overview

DRC Commands and Applications, Lab

Lunch

Designed Device Extraction Commands and Applications, Lab

Day 3

Designed Device Extraction Lab (continued)

Lunch

ERC Commands and Applications, Lab

LVS Commands and Applications, Lab

Day4

General Parasitic and Parasitic Resistance Extraction, Lab


Course Schedule

Cadence Basics 2-1

Cadence Basics

Objectives

■ Learn X Windows and Motif Basics

■ Learn to Start Cadence Software

■ Learn to Open Designs

■ Learn to Use Forms



Library A collection of cells.

Cell Design object that forms an individual building block of a chip orsystem.

View One representation of a cell.

X Windows A program allowing multiple programs to run on a single screen.

Motif Type of window manager for control of programs using theX Window System.

Cadence Basics 2-3

X Windows and Motif

Several programs can runat one time in X Windows.

Console window is theparent of all otherprograms.

The screen background iscalled the root area.

Pop-up menu (middle mousebutton) displays user-definedcommands.

After you type xinit or openwin,your screen displays the X WindowSystem environment.

cds2010-/Cadence/user1>

Root MenuNew WindowBig WindowclockLockShuffle UpShuffle DownRefreshRestart

cds2010-/Cadence/user1>


X Windows and Motif

Starting X Windows

Before you can start the Cadence software, you need to start the X Window System software.There are different versions of the X server so you may do one of the following

Type xinit in a UNIX window for the X11R4 and X11R5 server.

Type openwin -noauth in a UNIX window for the OpenWindows 3.0 server.

Whether you are using X11 or OpenWindows server does not make any difference to theappearance of the X Window System, as long as your are running the same window manager.Cadence supplies the Motif window manager with the software. The examples in this book areusing the Motif window manager. You can also use the Open Look window manager, but theappearance will differ from this book.

X Windows Environment

The default X Window System environment is customizable. This default environmentincludes a console window that displays system messages and a pop-up menu that lets youselect options start a new window, lock your screen, or refresh your screen. In a later module,you will learn how to customize the X Window System environment.

Cadence Basics 2-5

Using the Motif Window Manager

Click and pull onan edge tostretch it.

Click and pull on acorner to stretch it.

Click and pull on thetitle bar to move thewindow.

Use the left mouse buttonto move and resizewindows.

cds2010-/4.2.2>ls

cds2010-/4.2.2>



You can move and stretch windows by clicking on part of the window border.

■ Move windows by clicking and holding the left mouse button on the top title bar.

■ Stretch an edge by clicking and holding the left mouse button on an edge.

■ Stretch a corner by clicking and holding the left mouse button on a corner.

As you press the button and move the mouse, an outline of the window moves or stretches.

Release the mouse button to complete stretching or moving the window.

Cadence Basics 2-7


Click on this boxto enlarge thewindow and fillthe screen.

Single click on thisbar to pull down amenu (double clickto kill it).

Click on this box toshrink the windowto an icon.

Click on anyedge of awindow tobring it tothe front.


Expand and Shrink Motif Windows

You can expand a Motif window to fill the screen or shrink the window down to a small iconby clicking on the symbols in the right corner of the window banner.

Expand windows by clicking on the large square.

Return windows to their original size by clicking on the large square again.

Shrink windows to icons by clicking on the small square.

Reopen a window from an icon by double clicking on the icon.

Move an Motif Window to the Front

You can move any Motif window to the front of other windows by clicking on an edge of thewindow you want to bring to the front.

Killing a Motif Window

When you are finished using an Motif window, you can kill it. Don’t kill the window if you’restill running a program in it. This will cancel the program, and you may lose your data.

Motif window icon

Cadence Basics 2-9

Starting Cadence Software

Login:Password:

user1

host> xwin

1

host> icfb &xterm

Open Design Manager

mouse L: R:M:>

Set Search Path ...Library Browser...CDF

DesignFlow

Technology File

2

3


Starting Cadence Software

Step 1: To get to X Windows/Motif from UNIX

You log in to the system at the UNIX level. The system prompts you for a user name andpassword. From this environment, you can start the X Window System.

Steps 2: To get to Cadence Software from X Windows/Motif

Within X windows, you can use Motif Window Manager to control programs. Start theCadence software in an xterm. Here are two examples:

layoutPlus &icfb &

Step 3: The Cadence Software

The .cdsinit file initializes the Cadence software. It uses Cadence’s proprietary SKILL

language. The Command Interpreter Window (CIW) appears when the Cadence software hasstarted. You name your optional log file and desk setup with -log and -restore. Here’s anexample:

icfb -log mylog -restore mydesk &

The next example returns the version number of Cadence software but does not start it:icfb -W

Cadence Basics 2-11

Opening a Design

2

3

LibA

mux2

mycell

schematic

layout

Level: lib cell cellviewTools Design Window Create Edit

LibA mycell layout 1.02

1 Expand library and cell with the left mouse button.

Select the cellview with the middle mouse button.

Release on Edit or Read.


Opening a Design

You open designs and use design management commands with the Library Browser. Youexpand data to the cellview level and select Edit from its menu to open a design.

Select any data name in the browser with the middle mouse button to see its menu of designmanagement commands.

Select any data name with the left mouse button to expand it to the next level.

Cadence Basics 2-13

Command Interpreter Window (CIW)

Prompt line

Window

Mouse button cues

Output field:Running history of commands number

Input field:SKILL functions or expressions

icfb - Log: /usr/mnt/user1/CDS.log

Adding ‘.’ to your library path.Adding /4.3/etc/cdslib to your library path.

Adding /4.3/etc/cdslib/sheets to your library path.

Adding /4.3/samples/cdslib to your library path.

Welcome to Layout Training class...user1

Log file Menubanner


Command Interpreter Window (CIW)

Initial Window

When you start the Cadence software, the first window displayed is the Command InterpreterWindow (CIW). It is always window number 1.

Menu Bar

You can pull down command menus from the menu banner running across the top.

Output

The output area displays any portion of the log file (default name is CDS.log). The pathnameof the log file appears on the CIW title bar.

Input

The input area allows you to enter SKILL commands. By using window numbers, you candirect SKILL commands to operate on specific windows.

Prompt Line and Mouse Button Cues

The prompt line tells you what to do when using a command. The mouse button cues ( L:, M:,R:) display the action of each mouse button as you execute commands

Cadence Basics 2-15

Form Controls

TextEntryBox

Return acts like OKEscape acts like Cancel

Cyclic Fields act like Radio Buttons

CyclicFields

RadioButtons

CommandButtons

ToggleButtons

On-boardbuttons


Form Controls

Any menu command with an ellipsis (...) displays a form.

Types of Form Information

User-defined information (file and cell names) is typed as text. Combinations of predefinedchoices are displayed with toggle buttons. Mutually exclusive predefined choices aredisplayed as radio buttons and cyclic fields. Cyclic fields are used if a large number ofmutually exclusive choices are displayed. On-board buttons are used for auxiliary functions inthe display

Command buttons control the application of the form contents. OK applies the form settingsto the program and clears the form from the screen. Apply applies the form settings and keepsthe form on the screen. Cancel resets the form settings to the last state and clears the form fromthe screen. Defaults resets the form settings to the system-defined settings and keeps the formon the screen.

Cadence Basics 2-17

Types of Forms

Open Design

Standard Forms

Options Forms

Form Windows


Types of Forms

Standard Forms - control programs needing detailed information or control environmentalsettings

Options Forms - control the behavior of design creation and editing commands

Form Windows - tool boxes with controls for applications

Cadence Basics 2-19

Technology File

Cadence Library

DesignTechnology

DataFile

Stream, etc.

Dracula

Command File

properties

layers


Technology File

The technology file supports Cadence design data and applications. It contains layers andproperties used by Dracula and other products. Dracula can use the marker layer to send errorsinto a Cadence library for analysis.

Dracula also has an optional graphic user interface. This interface is not given to you whenyou buy Dracula. This interface uses view properties to set a choice of command file names.

Dracula uses Stream as an alternative data format. Dracula can read and write Stream format.

Cadence Basics 2-21

Cadence Basics LabsLab 2-1. Starting Cadence Software

Lab 2-2. Opening Designs

Lab 2-3. Setting Display Options


Dracula Overview and Operation 3-1

Dracula Overview and Operation

Objectives

■ Understand What Dracula Programs Do

■ Learn How to Use Dracula Programs

■ Learn to Find Errors with Dracula Programs



DRC Design Rule Check – checks physical layout data againstfabrication-specific rules.

ERC Electrical Rule Check – checks for electrical violations such asopen circuits or floating devices and nets.

LVS Layout Versus Schematic – compares a physical layout design tothe schematic from which it was designed.

Short Typically, an inadvertent connection made between one or morelayers, usually resulting in malfunction of the physical part.

Hierarchy Organization of design data where cells contain other cells.

Flat The absence of hierarchy in a design where all data shares onelevel.

LPE Layout Parasitic Extraction

PRE Parasitic Resistance Extraction

InQuery Chip-level results analysis tool. Can be used alone or with DFII.


Program Overview

1 12

DRC

LVS

ERC

MOS 1 2 3 4

Extraction and LPE/PRE


Program OverviewDRC

■ Design Rule Checks highlight deviations from physical design constraints set forth byprocess standards. Typical checks include material spacing, enclosure, and overlap.

Device Extraction

■ Device parameters and connectivity are extracted from the layout in order to performERC and LVS. LVS

ERC

■ Electrical Rule Checks highlight electrical problems, such as floating interconnect andshorted nets.

LVS

■ Layout Versus Schematic performs design matching of nets, devices, and deviceparameters. LVS compares any combination of physical or schematic designs.

LPE/PRE

■ LPE and PRE are used to find the parasitic effects of layout designs.


Program Flow

LayoutDatabase

DatabaseNetlist

DRC

DeviceExtract

Textand

GraphicError

Reports

LVS

ERC

LPE/PRE


Program FlowThere are several directions the physical verification flow may take. Layout data is usuallychecked for design rule violations first. More time consuming tasks like circuit continuitychecks are usually done last.

In the product flow shown, designs are handled differently for different verification products.Layout designs are input directly to DRC and are independent of other products. If ERC, LVSor LPE is required, then you need extraction to create device and connectivity informationfrom the original layout.

Netlist data is used only with LVS and with LPE when back-annotating original schematic netnames into the simulation netlist. You can compare two schematics or two layouts with LVSalso.


Operational Overview

PDRACULACommand File

Processor

Command File

DraculaProgramPhysical Data

Netlist Data

LOGLVSNetlist

Processor

Command File

Run Files

Errors

1

2

4

3

for LVS Textand

GraphicError

Reports

5


Operational Overview

First a command file must be developed that contains rules and commands that drive theDracula programs.

These command files must be compiled and checked by PDRACULA. At this stage commandfile errors will be found if they exist. This compiling stage creates the run files for Dracula.

If LVS is going to be used a netlist must be compiled using LOGLVS first.

The Dracula run is started and several reports are created depending on the type of program.These reports can be used for graphic or text-based error debugging.

Run files created by PDRACULA contain commands that generate data used by the Draculaprogram modules. These run files are called jxrun.com and jxsub.com.


Environment and Data Files

DraculaExecutableDirectory

Working

DraculaData

UNIX or DFII

Directory

Operates from

Layout DataSchematic DataCommand File

Run FilesResults FilesLog Files

PDRACULALOGLVSBinary Modules

Error Overlay

Directory

.DAT Files

Run Program

Run Scripts

DataGeneration


Environment and Data Files

At the UNIX level

■ PDRACULA and LOGLVS single command execution

■ Shell scripts you write

With Design Framework II

■ Standard DFII graphic encapsulation

■ Custom graphic encapsulation program from Application Support

■ InQuery results analysis tool for chip-level DRC and LVS

Input Data

■ Several types of layout data can be used by Dracula

— Cadence

— GDSII

— Applicon

■ Netlist data is processed by LOGLVS before use by Dracula

— CDL netlists made from Cadence schematic views

— SPICE, EDIF and Verilog netlists


DRC Overview

LayoutDatabase

TextOutput

Design Rule

CommandFile

GraphicOutput

Checks


DRC Overview

The design rules that control DRC operation are contained in the command file. The commandfile also contains instructions about what design to check and where it is located. Thecommand file must be processed with PDRACULA before running DRC.

DRC generates graphic and text error output. A SKILL file is created (with a user-definedname) by the system and loaded by the user to see errors overlayed on the design. A text fileis also created containing statistical information on the type, amount and location of errors.This file is called printf.sum.


Finding DRC Errors with DFII

Run DRC and

Load Graphic File

Overlay Error Cell

Graphic

into DFII

into Design

Create Error Files

Error Cellview

Search For and

Fix Errors

Summary File

Error File


Finding DRC Errors with DFII

There are several steps for displaying and finding DRC errors. Steps will vary using data otherthan DFII (GDSII, Applicon, etc.).

■ Errors are saved in two files. One contains the graphic errors and is created in SKILL.You specify the graphic error file name with the outdisk command.The other is thesummary file named printf.sum which contains a statistical listing of errors.

■ You must load the graphic error file in the CIW:

load “artchip”

The system creates a new cellview OUTartchip layout.

■ Place the error cell into the top-level design as an instance at the 0:0 origin.

■ Use the Search command to find graphic errors by their output name. All errors arestored on the marker layer. Use the printf.sum file for statistical information.


Finding DRC Errors with InQuery

Run DRC and

Overlay Errors

Graphic

on DFII Data

Create Error Files

Search For and

Fix Errors

Summary File

Error Files

with InQuery


Finding DRC Errors with InQuery

You use InQuery to efficiently find and fix errors in a large design.

■ Errors are saved in two ways. The first contains graphic errors. The second is a text file.The text file is a summary of error statistics named printf.sum.

■ You display the graphic errors with InQuery

— DFII users start InQuery from the menu

— non-DFII users create a placeholder cellview from the CIW


Using the DRC Summary File

All Error Cells Listings

Output Cell Summary

Problem Geometry Listing

Cell Name

Number of Acute Angle Input Polygons = 5

MET108 P1SEP05 P1WID05

• • •

Layer # Window # of Polygons

MET108 8 26.25 20.50 194.25 226.00 608

• • •

• • •

• • •Input Commands Listing


Using the DRC Summary File

The summary file is composed of some basic parts:

■ All Error Cells Listing

Use this to make sure all intended checks were performed.

■ Output Cell Summary

Use this to see the number of errors found separated by error type.

■ Problem Geometry and Acute Angle Listing

This section lists any reentrant, malformed or acute polygons.

■ Input Commands Listing

This section lists the entire command file used for the DRC run. Use this to crossreference output cell statistics with the actual checks you made in the command file.


DRC Lab

Lab 3-1. Run DRC and Analyze Errors



Electrical Rules Checking

LayoutDatabase

ERC

TextOutput

Extraction

CommandFile

GraphicOutput

Texted


Electrical Rules Checking

Electrical Rule Checking (ERC) checks the electrical integrity of the layout.

First, the layout must be texted with labels in the database or the EDTEXT file.

Then the command file must be processed by PDRACULA. Then you start the ERC job.

During extraction, devices and connectivity are recognized in the layout by commands in thecommand file. Then ERC checks the databases.

The output is either graphic or textual. Graphic output can be overlayed on DFII data oroverlayed by InQuery on GDSII data. This is very helpful for finding shorted nets. Fortext-based reports the printf.erc file provides the results of all texting, short and open errors.The printf.sum file gives a cell listing with coordinates and a problem geometry listing. Thisreport has the same format as the DRC summary.


Types of ERC Checks

■ Shorted Nets

■ Nets with the Same Labels that Don’t Connect

■ Soft-connect Checks


Types of ERC Checks

Shorts - multilab

Shorts are best found with the graphic capability of InQuery. InQuery displays only thepertinent shapes in the path of the shorting nets. This enables quick isolation of the violationregion.

Opens - samelab

ERC uses text to isolate which nets are disjoint and have the same labels.

Soft-connect Checks

These are also listed in the .ERC file.


Using the ERC Error File

Soft Check Listing

Text Summary

ERC Error Summary for Cell : SHORT01

input X 10.25 Y 9.75 NODE 2 ATTACH METAL1

Errors Found

Soft Connection Check on Layer NWELL

• • •

• • •

gnd X 168.00 Y 9.75 NODE 2 ATTACH METAL1

*/W* WARNING ** TEXT : input 2 SHORT DISCARDED*/W* WARNING ** TEXT : gnd 2 SHORT DISCARDED

Errors Listed Output Trapezoids


Using the ERC Error Summary

The summary file is composed of some basic parts:

■ Soft CheckListing

Use this to make sure all Soft checks were performed.

■ Text Summary

Use this to make sure all texts were extracted correctly and if not, what are the problemtexts.

■ ERC Error Summary for Specific Cells

This section lists all cells created by ERC errors whether they found errors or not.


ERC LabLab 3-3. Run ERC and Find Errors



Layout Versus Schematic

LayoutDatabase

DatabaseNetlist LOGLVS

LVS

TextOutput

Extraction

CommandFile

GraphicOutput


Layout Versus Schematic

Layout Versus Schematic (LVS) checks the consistency of connectivity and devices betweenthe layout and the schematic it was designed from. Also, any combination of designs may bechecked: layout vs. layout or schematic vs. schematic.

First, the schematic netlist must be processed by LOGLVS. Next, the command file must beprocessed by PDRACULA. Then you start the LVS job.

During extraction, devices and connectivity are recognized in the layout by commands in thecommand file. Then LVS compares the two databases.

The output is either graphic or textual. Graphic output can be overlayed on DFII data oroverlayed by InQuery on GDSII data. The printf.lvs file gives a comprehensive LVS reportwhich provides the most helpful analysis.


Preparing Netlists

DatabaseSchematic CDLout

LOGLVS

Cell-basedCDF

NetlistCDL-ASCII

NetlistProcessed

DFII

UNIX

VariousNetlist Types


Preparing Netlists

There are many netlist formats acceptable to Dracula. If your schematics are DFII-based usethe Circuit Description Language (CDL) netlist translator. It creates a spice-like netlist usingthe special netlist statements required by Dracula.

The netlist is created with the Library’s Component Description Format (CDF). AppropriateCDL-related properties must appear in each cell’s CDF for netlisting. These properties providethe netlist format information needed to create the netlist.

After the CDL netlist is created, or if a netlist in another format already exists, you runLOGLVS to process the netlist into a binary image. This binary file is used by Dracula LVS atrun time. You run LOGLVS in UNIX. The default output file name is LVSLOGIC.DAT.


Initial Correspondence Node Pairs

VDD:P

CLK

IN2

IN1

Layout

VDD:P

CLK

IN2

IN1

Schematic/Netlist



To resolve ambiguity and speed up LVS, initial correspondence point pairs should be set upbetween layout and schematic netlist. These points establish a starting place for thecomparison. Any net or device parameter can be used as a correspondence point.

If correspondence points are not set Dracula starts the comparison with automatch. This modelets comparison proceed without correspondence points (power and ground nodes using :Pand :G must be defined, however).

You can also create a file containing the names of node pairs for LVS. The command thatspecifies the node pair file is cpoint-file = filename.

For example:

The format of the file is:

Layout node name Schematic node name [A]

VCC vcc!

415 34 A

•••


LVS Device Reduction

SDW

MOS[P] PUP

INV

NANDoutput

MOS[N]



Provides various device-grouping methods for LVS analysis.

Device Group Application/Terminal Order

PUP Parallel Up (p-channels) - output, in1, in2, in3...

SDW Series Down (n-channels) - output, in1, in2, in3...

MOS[type] MOSFET (n or p-type) - gate, source, drain

CAP/RES/DIODE[type] Passive Devices (specify type) - terminal1, terminal2

INV Inverter - output, input

NOR Nor gate - output, in1, in2, in3...

NAND Nand gate - output, in1, in2, in3...


LVS Error Report

Device Reduction Summary

Correspondence Node Pairs

LVS Device Matching Summary

Schematics

Number of Matched Schematics Devices = 112

BJT RES

Layout Pad Type

8 CA

Number of Un-matched Schematics Devices = 1

CA 258 COCO 1

I

O

MOS

0 034

Discrepancy Points Listings


LVS Error Report

Device Reduction Summary

Good spot check to see how many devices LVS found and how it performed device reduction.

Correspondence Node Points Summary

Checks the essentials of continuity - did the number of pads in the layout match the schematic?

LVS Device Matching Summary

Total of the number of matched and unmatched errors.

Discrepancy Points Listing

Detailed analysis of LVS errors.


LVS Error Report

Discrepancy Points Listings

Layout SideSchematic Side

Node or Device BasedOccurence Names

Discrepancy Number

?Device NameUnmatched

?Net Name

or

Discrepancy Points Summary

Total Number and Type of Discrepancies


LVS Error Report


Provides a detailed examination of device-based and net-based analysis.

Example:

*************************** Discrepancy 1 *********************************

--- Node CA ---with Un-matched Devices-------

Occurrence Name Clk Dev203 Inv : Dev209 Inv X=143 Y=128 Clk, CA Clk, CA

Occurrence Name Cin ?dev233 Pdw : ***** Un-matched ***** Cin, CA, Carry

Dev234 Sup : Dev208 Sup X=103 Y=154 Cin, Carry, Ca Cin, Carry, Ca

***** Un-matched ***** : ?Dev18 Mos N X=106 Y=120Ca, Vss, Cin


Graphic LVS Error Analysis

Run LVS and

Overlay Errors

Graphic

on DFII Data

Create Error Files

Search For and

Fix Errors

.lvs File

Error Files

with InQuery


Graphic LVS Error Analysis

You use InQuery to find and fix errors in designs.

■ Errors are saved in two ways. The first contains graphic errors. The second is a text file.The text file is named printf.lvs.

■ You display the graphic errors with InQuery

— DFII users start InQuery from the menu

— non-DFII users create a placeholder cellview from the CIW with the command:iqCreateDummyCell


LVS LabLab 3-4. Run LVS and Find Errors


Dracula Command File Structure 4-1

Dracula Command File Structure

Objectives

■ Understand Dracula Command File Structure

■ Learn Basic Command File Syntax




Global Program Information

Description Block

Data Specifications

System Information

Data Handling

*description;indisk = ../draculalibrary = artLibprimary = bandgapschematic = LVSLOGICoutdisk = bandgapprintfile = bandgap

••

system = cadenceprogram-dir = /usr1/cadence/draculamode = exec now

••

resolution = .25 micronscale = .001 microntext-pri-only = yeskeepdata = yes;*end

Command File

description block

input layer block

operation block

Specifications


Global Program Information

The description block contains commands needed by the system to input, process and storedata.

■ format type

■ input and output file names

— top level cell name

— library name

— verification report and graphic error file names

■ scale and working resolution of the database

data off the resolution’s grid will be snapped to the specified grid

■ location of program executables

Some commands change their meaning when used for different data formats.

For Cadence data indisk is a path to a library:indisk = /usr1/mnt/user1/Dracula

For Stream data indisk is a stream database name:indisk = stream.db


Database Layer Information

Input Layer Block

Internal Layer Names

*input-layer;pwell = pwell drawingvddMet1 = metal1 vddactive = active

•••

text = texttext-sequence = poly1 metal1

•••

temporary-layer = tmp1 psd nsd•••

connect-layer = nsub pwell psd nsd poly1 metal1;*end

Command File

description block

input layer block

operation block

Text to Layer

Connection Sequence

Associations

Temporary Layers


Database Layer Information

The types of commands in the input-layer block are:

■ layer name definitions

— use layer name/purpose name for Cadence data

— use layer number/datatype number for Stream format

■ text to layer associations. Alternate format:metal1 = METAL1 text = TEXT attach metal1

■ interconnect sequence in mask order

provides default text-to-layer association list

■ temporary layers

inhibits generation of false compilation errors


Layer Processing andVerification Commands

*operation;not POLY1 mask poly1and NSD poly1 ngatenot NSD poly1 nsdand PWELL PSD ptap

•••

connect metal1 poly1 by contactconnect pwell psd by ptap

• • •ext[toe] metal1 lt .75 output met1sep 10enc[t] nsd poly1 lt .5 output p1ext 10

• • •element mos[n] ngate poly1 nsd pwellelement bjt[n] vnpn nsd pbase nemit

• • •multilab output short 10;*break LVSlvschk[c] printline = 150;*end

Operation Block

Interconnect

Design Rules

Layer Processing

Extraction Commands

Definitions

ERC and LVSCommands

Command File

description block

input layer block

operation block


Layer Processing and Verification CommandsYou use layer processing commands to create shapes needed for design rule checks andextraction. The process of extraction creates data suitable for ERC and LVS.

The types of commands in the operation block are:

■ layer processing

■ interconnect definitions

■ design rule checks

■ extraction commands

■ electrical rule checking commands

■ layout vs. schematic commands

Layer Processing 5-1

Layer Processing

Objectives

■ Learn an Overview of Layer Processing Commands

■ Learn Some Applications of Layer Processing

■ Learn Function Syntax



Layer Processing The creation or modification of layers for the purpose ofverification.

Derived Layer Layers created from other layers by layer-processing commands.

Original Layer A mask layer in the source database; you used these layers todraw the original design.


Layer Processing Commands

■ Used to Create Shapes for DRC or Extraction

■ Commands Use Derived or Original Layers

■ Command Groups:

— Logical - Create Shapes by Layer Interaction

— Selection - Select Shapes by Attribute or Relation to Other Shapes

— Sizing - Create Shapes by Changing Layer Dimensions



Layer processing is the creation of new layers for verification programs. There are severalgroups of commands.

New layers output from a layer processing command are called derived layers. Derived layerscan be shapes or edges. The input layers to a layer processing command can be either shapesor edges; they also can be derived or they can be an original layer (a layer used in the originaldesign).

All input shapes are merged by layer processing commands. Construction lines of all originalshapes are eliminated.


Logical Commands

or poly ndiff mask

and poly ndiff ngate

input layers poly, ndiff

not ndiff poly nsd xor ndiff poly gext


Logical Commands

Logical commands create new shapes. Logical commands take two input layers.

and Outputs a layer containing the overlapping areas of two differentshapes.

or Outputs a layer containing all shapes form the input layers. All shapeson the output layer will be merged.

not Outputs a layer containing areas of the first layer except overlappingareas of the second layer. Another way of thinking about this is “theoutput layer is equal to the first layer minus the second layer”. Theresulting output layer is dependent on the order of the input layers.

xor Outputs a layer containing the non-overlapping areas of two differentshapes.


Selecting Shapes

select ndiff inside pbase nemit

select diff outside pwell pdiff

select res enclose[1:1] cont badres


Selecting Shapes

Select commands have two input layers. Select commands output the entire shape of the firstinput layer if the selection condition is met.

All commands use range modifiers. The range modifier is represented by two numbersseparated by a colon.

inside Selects shapes of one layer that are completely inside shapes of anotherlayer. These shapes are also selected if they are coincident.

outside Selects shapes of one layer that are completely outside shapes ofanother layer. These shapes are also selected if they are butting.

enclose Selects shapes of the first layer that fully cover shapes of the secondlayer.


Selecting Shapes (continued)

select pdiff touch ndiff bcdiff

select diff overlap well tap

select diff cut[1:2] poly sd



touch Selects shapes of the first layer that butt shapes of the second layer.

cut Selects shapes of one layer that are partly covered by shapes of anotherlayer.

overlap Selects shapes of the first layer that satisfy conditions for touch, inside,cut, enclose and hole.



select well hole pstop pwell

select diff vertex[8:8] octDiff

select poly1 label[r] pres p1res

pres

select poly1 label clk p1res

node ‘clk’


Selecting Shapes

vertex Selects shapes that match the specified range of vertices.

hole Selects shapes of the first layer which have all edges completelytouching one shape of the second layer.

label Selects shapes of the first layer that enclose the origin of the specifiedtext string.

Alternatively, you select shapes of the first layer for the specified netname.


Sizing Shapes

value

rescon resterm

size rescon by .5 resterm

size metal1 by -1 tmp1

size tmp1 by 1 clnmet output met1 10

metal1

tmp1

clnmet


Sizing Shapes

size Oversizes or undersizes all shapes on the input layer by the valuespecified. Positive values oversize. Negative values undersize.

You use size for recognition of devices and their terminals, intermediateprocessing, the elimination of unwanted data or merging data.

You also use size to create pattern generation data for mask making.

some options

o Meaningful only with oversizing. Oversizes data without merging thenoutputs only the overlapped regions. No intermediate layer is created.

p Meaningful only with undersizing. Undersizes original layers beforemerging.

w You use w to increase efficiency during sizing very dense layers likeinterconnect. w works together with the size-min-width variable set in thedescription block.

output You use output to store data for error flags, Dracula generated mask dataor final pattern generation (PG) data. output stores data in polygon format.


Sizing Shapes

3

grow metal 3 2 outmet

2

grow metal -2 0 outmet

2

3

shrink metal 3 2 outmet

2

shrink metal -2 0 outmet

2


Sizing Shapes

grow Oversizes two perpendicular edges of a shape. Positive values oversize thetop and/or right edges. Negative values oversize the bottom and/or leftedges.

shrink Undersizes two perpendicular edges of a shape. Positive values undersizethe top and/or right edges. Negative values undersize the bottom and/orleft edges.

Design Rule Checking 6-1

Design Rule Checking

Objectives

■ Understand the Purpose of Design Rule Checking

■ Become Familiar with DRC Applications

■ Create and Execute DRC Commands



DRC Acronym for Design Rule Check.

Fabrication The act of building a semiconductor device using variousprocessing techniques.

Physical Data A computer-based topological layout of an electrical device.


DRC Applications

width metal1 lt 2 output met1wid 2

ext[r] poly1 lt .3 p1fix

ext[t] poly1 ndiff lt 2.5 output p1ndsep 3

ext[p] metal1 lt .75 &

length metal1 gt 20 output fmetsep 4


DRC Applications

The purpose of these DRC commands is to locate violations of process rules in a layout.

All commands except area check edge-to-edge of shapes.

You use the output of DRC commands as error flags or for deriving intermediate layer data.DRC errors are stored in Cadence or Stream format. You look at the errors with either VirtuosoLayout Editor or with InQuery.

You couple commands to pass the results from one operation to a subsequent operation. This‘filters’ data through various steps of a verification algorithm. This coupling is called‘conjunction’. With conjunction, complex checks can be developed without creatingintermediate layers.


DRC Commands

width met lt 2 out...

ext met poly le 1 out...

enc cont met lt 2 out...

area met range 4 8 out..

int bcut nsd lt 1 out...

ext[h] met lt 1 out...


DRC Commandswidth Checks inside edge to inside edge of shapes on one layer.

area Checks the area of shapes.

ext Checks outside edge to outside edge of different shapes. Shapes may be on thesame layer or different layers.

ext[h] Checks outside edge to outside edge of the same shape. Commonly callednotch checking.

enc Checks outside edge of shapes on the first layer to inside edge of shapes on thesecond layer.

int Checks inside edge to inside edge of shapes on different layers.


DRC Command Selection Operators

ext m1 p1 sellt 2 err1

ext m1 p1 selgt 2 err1

ext m1 p1 selle 2 err1

ext p1 m1 selra 0 5 err1

m1 m1

2< 2

p1

0 < selra < 5

m1

> 2

ext m1 p1 selge 2 err1

m1

>= 2


DRC Command Selection Operatorslt, le, range Less than, less than or equal to and range of two values (not inclusive).

gt, ge Greater than, greater than or equal to (used for length only).

sellt Same as lt except sellt selects shapes from the first layer of the violation.

selle Same as le except selle selects shapes from the first layer of the violation.

selra Same as range except selra selects shapes from the first layer of the violation.

selgt Selects all shapes from the first layer that selle does not select.

selge Selects all shapes from the first layer that sellt does not select.


DRC Command Modifiers

ext[p’]...

ext[c’]...

ext[n’]...

ext[c]...

ext[n]...

ext[p]...

parallel modifiers

nodal modifiers

projection modifiers


DRC Command Modifiersc - parallel Restricts commands to check parallel edges only. All commands check

parallel and non-parallel edges by default.

c’ - not parallel Restricts commands to check non-parallel edges only.

n’ - same net Restricts commands to check only shapes on the same net. The layerscontaining these shapes must appear in a connect command before thismodifier is used.

n - different net Restricts commands to check only shapes on different nets. The layerscontaining these shapes must appear in a connect command before thismodifier is used.

p - projection Restricts commands to check facing edges only. All commands checkprojecting and non-projecting edges by default.

p’- no projection Restricts commands to check non-facing edges only.


DRC Command Modifiers

region generation

general modifiers

square corner check

ext[r]... ext[r’]...

ext[t]... ext[o]... enc[e]...

ext[s]...


DRC Command Modifiersr - region Generates a shape in the area of the violation instead of error edges.

r’ - outer region Generates minimum width shapes outside the violation region insteadof error edges.

t - touch Includes errors where layers butt.

o - overlap Includes errors where layers overlap.

e - not enclosed Select shapes on the first layer where they fall outside the second layer.

s - square corner Includes square corner check.


Width-factored Spacing Rules

Problem: Spacing of metal1 is 2.

Step 1.

width[p] metal1 lt 1.2 & ;Step 1

If metal1 width is less than 1.2, spacing is 3.

ext[p] metal1 metal1[o] lt 3 output err 1 ;Step 2

Step 2.

2

< 1.2

3


Width-factored Spacing Rules

This problem is solved using command conjunction:

Step 1. All edges of metal1 width less than 1.2 are selected.

Step 2. The selected edges are temporarily named metal1 for the next part of the command.

These temporary edges are then checked for spacing to metal1[o].

metal1[o] edges are the original metal1 edges.

The selected edges are output to an error cell called err01.

If you need to use the selected edges from the first part of this command later for otheroperations, you use the conjunctive copy feature. Conjunctive copy can only be used whenconjuncting commands.

Conjunctive copy outputs the results from the first command to the layer named &name. Thefirst layer used as a temporary name in the second command now retains its original data. The[o] option applied to the second layer is now meaningless. We can alternatively write theabove solution like this:

width[p] metal1&m1wid lt 1.2 & ;Step 1

ext[p] &m1wid metal1 lt 3 output err 1 ;Step 2


Well Tie Checking

size ptap within pwell by 20 tmp1

20

20

ptap

pwell

not pwell tmp1 err1 output err 1

and pwell psd ptap1

2

3


Well Tie Checking

You use the size command with the within option for the solution.

1. You find the pseudo-contact.

2. You size within by the coverage amount.

3. Then you not the remainder from the well region. Output the remaining portion as anerror.


Data Integrity Checking

path

flag-offgrid = yes

flag-acuteangle = yes

flag-selfinters = yes

path-w-offgrid = yes

path-w-round = up

overlap metal1 badmet


Data Integrity Checking

You use a variety of commands for data integrity checking.

flag-offgrid and path-w-offgrid output errors when any shape is off the coordinates of yourdesign. You state the design coordinates with the resolution command in the description block.All data is snapped back onto grid using flag-offgrid. You determine how paths are snappedwith path-w-roundup. These commands must appear in the description block.

You use flag-acuteangle to find all shapes formed with acute angles. This command mustappear in the description block.

You use flag-selfinters to find all self intersecting shapes. This command must appear in thedescription block.

You use overlap to find all overlapping shapes on the same layer. overlap must appear in theoperation block. overlap must be the first command to use any layer in the command file.overlap creates trapezoid data only.


Gate Dimension Checking

and poly psd pgate

psd

poly

ext[tr] pgate psd lt .001 edges

plength edges range 0 10 output err 1

1

2

pgate

edges

3


Gate Dimension Checking

You use the plength command to measure the length of edges. The edges plength measuresmust be selected with any DRC command using the t and r modifiers. plength measures edgeswithout regard to vertices.

1. You find the layer to measure. In the example a p-channel recognition layer is selected.

2. You select the edges of the layer to measure.

3. Then you measure the edge length. The result is output to an error cell. This exampleoutputs all pgate which have widths greater than 10.


Speed Improvements for Hierarchical DRC

size vapox by 20 tmp1

and tmp1 metal1 tmp1

flatten tmp1 fmet1

20<15u

ext fvapox fmet1 lt 15 output err 1

flatten vapox fvapox

1

2

3


Speed Improvements for Hierarchical DRC

It can be time consuming when dense layers are be checked. For localized checking aroundsparse layers, such as pads, use the flatten command. These steps describe how the applicationworks:

1. Oversize the sparse layer to the extent necessary. and the dense layer with the oversizedsparse layer.

2. flatten the sparse and dense layers.

3. Check the distance between the layers you flatten.


Process Specification for DRC Lab

Partial Specification for P-substrate BICMOS Process

rule specification dimension(microns)

rule specification dimension(microns)

well checks metal1 checks

1a minimum pwell width 2.5 4a minimum metal1 width 0.75

1b pwell enclosure of active 0.5 4b minimum metal1 spacing 0.75

1c minimum nwell width 2.5 4c metal1 enclosure of contact 0.5

1d nwell enclosure of active 0.5

contact checks

diffusion checks 5a minimum contact width 1

2a* minimum active width 1.5 5b minimum contact spacing 1

2b minimum active spacing 1.5

2c NPLUS enclosure of active 0.25 pad checks

2d PPLUS enclosure of active 0.25 5a minimum Vapox width 18

2e active enclosure of contact 0.5 5b metal1 enclosure of Vapox 1

* Ignore acute angles and non-parallel edges

poly1 checks

3a minimum poly1 width 1

3b minimum poly1 spacing 1

3c poly1 extension past active 1.5

3d poly1 enclosure of contact 0.75


Process Specification for DRC Lab

Use this Process Specification as a guide to create a DRC command file for Dracula. You willtranslate the requirements of the specification into Dracula syntax.

Some of the rules will require layer processing before making checks.


Labs in this Section

Lab 6-1. Create a DRC Command File from the Process Specification


Designed Device Extraction 7-1

Designed Device Extraction

Objectives

■ Learn to Extract Layout Devices

■ Write an Extraction Command File



Connectivity Expression of electrical connection between devices of a circuit.

Recognition Layer A unique layer used to identify a device.

Terminal 1. A connection point to a device.

2. An input or output connection to a cell.


General Extraction Steps

Find the Recognition Layer

Derive Terminal Layers

Create Pseudo-contacts

1

2

3



This is a guideline for designed-device extraction. It is not exhaustive, but it will help you getstarted in the right direction. There are six steps. The first three deal with preparation using thelayer-processing tools discussed earlier in this manual. Steps 4, 5, and 6 perform the actualextraction of devices and connectivity and use commands we’ll discuss later in this module.

Recognition Layer

The recognition layer should be identified first. You use a layer that is derived from the uniqueinteraction of the various layers that make up the device can usually be found. You can use anoriginal layer which may make unique device identification easier.

Terminal Layers

Second, there may be mask layers that will not provide correct terminals. For example, sourceand drains in a SAG (self-aligned gate) process. The single active region drawn must be splitinto two shapes, which represent the source and drain.

The recognition layer must overlap or touch all the terminal layers.

Psuedo-Contact Layers

To facilitate soft-connect checking the use of sconnect is necessary to connect diffusions towells. A ‘contact’ that represents the overlapped area of diffusions and wells must befabricated and then used along with the connecting layers in an sconnect statement.



DS

G

B

mo

s[n

]

Extract Connectivity

Extract and

Declare Parameters

4

5

6 .3 pF/ square

.04 ohms/square

(for Resistors andCapacitors Only)

w= 4, l = 2

Measure Devices


General Extraction Steps (continued)

Connectivity

You derive connectivity using the connect command. You include all contacts in connectcommands and pseudo-contacts you created in sconnect commands. Make sure the layernames used in each connect and sconnect command are consistent.

Device Extraction

Device extraction requires a recognition layer and connected terminal layers. The elementcommand provides different fields for different kinds of devices. MOSFET parameters aremeasured, also. Corner effect is measured later during comparison.

Declare Parameters

After the devices have been extracted you declare values of sheet resistance and capacitivearea or perimeter with the parameter command. All properties measured must be directlyrelated to the recognition layer of the device. You measure widths and lengths during LVS.


Labeling Your Design

vdd:

vdd1:p

agnd:g

vdd:

clk:i d0:o vss

vcc, vdd, gnd, vss and ground are

recognized supply names

edtext = text.file

Optionally import text from a file with


Labeling Your Design

Dracula requires text for specific applications.

For ERC, all power and ground supplies must be labelled. The exception are the default labelsautomatically recognized by Dracula: vdd, vcc for power supplies; vss, gnd and ground forground supplies.

Even if you set automatch = yes, LVS runs faster when power and grounds are labelled.

For LPE, all inputs and outputs must be labelled for creation of a logic level netlist.

To connect nets which have no connection in the design you use the colon suffix (:).

You use the edtext file to import texts for specific Dracula runs. You put the edtext commandin the operation block before the connect command. Example format:

vdd: x=0 y=-260 attach=metal1

clk x=22 y=71


Defining Text

connect-layer = pwell psd metal1 poly1

textsequence = poly1 metal1

xCLK

xCLK


Defining Text

Text is defined in a physical design by the placement of labels. You use labels for ERC andLVS. The origin of labels must overlap layers in connect and sconnect commands.

connect-layer You must use connect-layer if you use connect. connect-layerspecifies the mask order from top tp bottom (right to left). Thefirst three characters of any layer named in connect-layer mustbe unique. connect-layer also prioritizes mask layers for labelattachment.

textsequence Prioritizes mask layers for label placement. textsequenceoverrides the layer names and layer order defined byconnect-layer.


Defining Connectivity

connect metal1 poly1 by contact

sconnect pwell psd by ptap

connect metal1 psd by contact


Defining ConnectivityConnectivity is defined in a physical design by the relationship of its overlapping layers. Theshapes on layers in the connect and sconnect commands are saved as electrical nets. Thisinformation is used for ERC and LVS.

Here are the two commands in their complete form:•••

connect metal1 poly1 by contact

connect metal1 nsd by contact


connect metal1 pemit by contact

connect metal1 termres by contact

connect metal1 pbase by pcont

sconnect nsd epi by ntap ;soft connections

sconnect nsd nwell by ntap ;soft connections

sconnect psd pwell by ptap ;soft connections

•••

connect makes connections between two overlapping shapes with an overlapping contactlayer. Each contact layer name must correspond to one upper-layer name.

sconnect makes connections between two overlapping shapes with an overlapping contactlayer. Each contact layer name must correspond to one upper-layer name.sconnect passes connectivity to the lower-layer for subsequent soft-connectchecking.


Extracting MOSFETs

element mos[n] ngate poly1 nsd pwell

D

S

GB

n-MOSFET

psd well tie

pwell

contact hole

metalSiO2


Extracting MOSFETsYou derive the recognition layer with and. This will be poly1 overlapping nsd/psd.

You derive the terminal layers by removing poly1 from nsd/psd with the not command.

Here are the layer processing steps:

•••

and active NPLUS ndiff

and active PPLUS pdiff

not ndiff poly1 nsd ;n-source/drain

not pdiff poly1 psd ;p-source/drain

and ndiff poly1 ngate ;n-channel

and pdiff poly1 pgate ;p-channel

•••

element mos[n] ngate poly1 nsd pwell ;n-channel

element mos[p] pgate poly1 psd nwell ;p-channel

•••


Extracting PNPs

element bjt[p] lpnp psd epi pemit iso

B

C

E

P- isolation (iso)

LPNP

nsd

S


Extracting PNPs

It’s best to use the collector for the recognition layer. The PNP collector of a single structurecan be split to be used as different devices. In this process, the area enclosed by the collectorwill be the recognition layer. This area will overlap or touch all terminals.

Significant layer processing may be required to properly extract the PNP with multiplecollector structures. If your process allows, try a static emitter size to differentiate from thecollector diffusion.

The emitter is the only processed terminal layer. You use and to derive it from the recognitionlayer. You must remove it from the original psd layer with not.


•••

and psd epi tmp1

ext[hr] tmp1 le 10 pnp ;pnp recognition layer

and pnp psd pemit ;pnp emitter terminal

not psd pemit psd ;adjusted psd layer

•••

element bjt[p] lpnp psd epi pemit

•••


Extracting NPNs

element bjt[n] vnpn epi pbase nsd iso

C

E

B

VNPN

P- isolation (iso)

buried layer

sinker

ndiff

S


Extracting NPNs

Use the emitter for the recognition layer. It is enclosed by the pbase diffusion layer. You usethe inside selection command or and to find the npn recognition layer. and is faster.

The emitter and its contact overlaps the pbase and will short the base to emitter. To preventthis you must derive separate contacts for the connections to pbase. You must then remove thepbase contact you derived from the contact layer.


•••

and nsd pbase npn ;npn recognition layer

•••

not pbase nsd tmp1 ;block out nsd contact

and contact tmp1 pcont ;pbase contact

not contact pcont contact ;adjusted contact

•••

element bjt[n] vnpn epi pbase nsd

•••


Extracting Resistors

element res[p] pres resterm [epi]

PLUS MINUS

P- isolationPRES

metal1

SiO2

epi

contact hole

p-resistor


Extracting Resistors

Begin by finding the resistor terminal areas. There are several ways to accomplish this:

a) The simplest way is to use and to select contact within the resistor body, or

b) you can oversize contact by the enclosure rule of PRES

After any of the above steps the resistor terminal areas must be removed from PRES with not.This will give you the resistor recognition layer.

Here are the layer processing steps (there are a number of ways to extract the resistor):

•••

and contact PRES tmp1 ;resistor contact

size tmp1 by 1.5 termres ;resistor terminal

not PRES termres resp ;pres rec. layer

•••

element res[p] resp termres

parameter res[p] 200 ;sheet res of 200 ohms/square

•••


Extracting Capacitors

element cap[n] ncap metal1 nsd [epi]

PLUS MINUS

thinox

epi

nsdP- isolation

n-capacitor


Extracting Capacitors

Use and to find the overlap of metal1, nsd and thinox for the recognition layer.

The terminal layers should be represented by metal1 for one plate of the capacitor and nsd forthe other plate.


•••

and thinox metal1 tmp1

and tmp1 nsd ncap ;ncap rec. layer

•••

element cap[n] ncap metal1 nsd

parameter cap[n] 9e-15 ;9f farads capacitance/square

•••


Lab

Lab 7-1. Create, Run and Debug your own Extraction Command File


ERC Commands and Applications 8-1

ERC Commands and Applications

Objectives

■ Learn ERC Command Applications

■ Create an ERC Command File



ERC Abbreviation for Electrical Rule Check.

Floating net or device A net or device with no connection to any other part of thecircuit.

Short A single net with multiple labels indicating an inadvertentconnection. A single net connecting too many devices.


Checking Opens and Shorts

clk clkOpen Circuit

samelab output open 1

vdd vssShort Circuit

multilab output short 1


Checking Opens and Shorts

samelab Finds open circuits between unconnected nets with the same labelsattached.

multilab Finds short circuits between connected nets with different labelsattached.


Finding Floating Wells

pwell


sconnect psd pwell by ptap

lconnect pwell disc vss output err 1•••

2

3

psd

pwell

Floating Well

metal1

vss

psd

and psd pwell ptap1


Finding Floating Wells

This technique does not rely on device extraction. Connectivity extraction is necessary.

1. Connection of layers in the layout. You use the connect command for standardconnections. You must use the sconnect command for well connections for subsequentsoft-connect checking.

2. You use lconnect to select any layer either connected or not connected to the specifiednet name. Conditions for lconnect are disc and conn.


Soft-connect Checking

and pwell psd ptap

psd

psd

pwell


sconnect psd pwell by ptap

softchk pwell output[u] err 1

1

2

3


Soft-connect Checking

Soft-connect checking prevents well regions from being used as conduction paths in a circuit.Wells usually have high resistance and therefore create large voltage drops betweenconnections through them.

Three steps are used to find soft-connect problems with Dracula:

1. Creation of a ‘pseudo-contact’. You use pseudo-contact to model the virtual connectionby overlap that the layout would have when it is built.


3. softchk outputs multiple diffusion shapes that are not connected but overlap the samewell.

Text errors are output to the <printfile>.ERC file.

You use abort-softchk if you want the program to stop when a soft-connect error has beendetected. This could save hours of processing time. abort-softchk is placed in the descriptionblock of the command file.


Finding Improper Device Connections

connect metal1 nsd by contact

sconnect nsd nwell by ptap

econnect mos[p] nwell disc vdd output err 1•••

2

3

p-mosvss

and nsd nwell ntap1


Finding Improper Device Connections

You extract devices necessary for econnect.


2. You use econnect to select any device which has terminals either connected or notconnected to the specified net name. Conditions for econnect are disc and conn.


Labs in this Section

Lab 8-1. Create and Execute an ERC Command File


LVS Commands and Applications 9-1

LVS Commands and Applications

Objectives

■ Learn LVS Structure Recognition

■ Understand Uses of LVS Commands

■ Understand LVS Report Format

■ Learn LVS Debugging Methods

■ Create LVS Applications



LVS Abbreviation for Layout Versus Schematic.

Structure Internal mechanism Dracula uses to categorize and process data.


LVS Structure Recognition

■ Understand Structure Types

■ Learn How to Identify Structure Types

■ Learn to Find Errors Using Structures


LVS Structure Recognition


Device Reduction Using Structures

SDW

PUP

NAND

Primitive

A

B

Y

YA

B

Y

A

B

B

AStructures

Second-levelStructures

Gate-levelStructures


Device Reduction Using StructuresPrimitive structures are mosfets, capacitors, etc. Second-level structures are the internalstructures Dracula uses to recognize both standard and complex gates. Gate-level structurespermit an even higher level of recognition which can speed up error resolution.

There are also complex gate structures.


Primitive Structures

MOS[P]

CAP[N]

RES[P] DIO[P]

BJT[N]


Primitive StructuresExamples of the lowest-level structures:

Mosfet MOS[type] gate, source, drain

Bipolar BJT[type] collector, base, emitter

Resistor RES[type]Capacitor CAP[type]Diode DIO[type] terminal1, terminal2


Second-level Structures

PUP Output, IN1, IN2, INn...

SUP Output, IN1, IN2, INn...


Second-level StructuresPull-up device structures (usually p-channels):

Parallel Up PUP output_node, input_node1, input_node2, .....

Series Up SUP output_node, input_node1, input_node2, .....


Second-level Structures

PDW Output, IN1, IN2, INn...

SDW Output, IN1, IN2, INn...


Second-level StructuresLoad device structures (usually n-channels):

Parallel Down PDW output_node, input_node1, input_node2, .....

Series Down SDW output_node, input_node1, input_node2, .....


Gate-level Structures

INV OUT, A

NAND OUT, A, B

NOR OUT, A, B

P

N

A OUTOUTA


Gate-level StructuresTypical INV, NAND and NOR transistor-level circuits can be reduced to their gateequivalents.

Nand gate NAND output_node, input_node1, input_node2, .....

Nor gate NOR output_node, input_node1, input_node2, .....

Inverter INV output_node, input_node


Complex Second-level Structures

PUPI OUT, A, B

SUP OUT, C, OUT

SDWI D, A, B

PDW OUT, C, D

symbolic name

internal net closestto the output


Complex Second-level StructuresThe process of reduction starts at the incomplete parallel or series structure. An incompleteparallel structure is at least two devices in parallel and either source/drain connected to asupply or an output. An incomplete series structure is at least two devices in series and eitheroutside source/drain connected to a supply or an output.

The remaining devices not recognized as incomplete structures are then classified as thestandard structures (PUP, SDW, etc.). They are then combined with the incomplete structuresfor the final complex gate. In order to connect the standard structures to the incompletestructures, the output node for parallel structures is used as a symbolic node. Incomplete seriesstructures are connected to standard structures using an internal node closest to the output ofthe final complex gate.



SDWI

PUPI

SUPSDWI

PDW

OUT

A

B

C

PUPI

SUP

PDW

A

B

COUT


Complex Second-level StructuresFirst, the incomplete structure is recognized then combined with the remaining structures. Theremaining structure(s) use the standard second-level structure names loosely (SUP, PDW,etc.).

And-Or gate PUPI symbolic_node, input_node1, input_node2

SUP output_node, input_node3, symbolic_node

SDWI internal_node, input_node1, input_node2

PDW output_node, input_node3, internal_node



PDWI

SUPI

PUPPDWI

SDW

OUT

A

B

DSUPI

PUP

SDW

DOUT

C

A

C

B


Complex Second-level StructuresFirst, the incomplete structure is recognized then combined with the remaining structures. Theremaining structure(s) use the standard second-level structure names loosely (SUP, PDW,etc.).

Or-And gate SUPI internal_node, input_node1, input_node2

PUP output_node, input_node3, internal_node

PDWI symbolic_node, input_node1, input_node2

SDW output_node, input_node3, symbolic_node


Complex Gate Structures

AND

AOI OUT

A

C

AND

B

AOI OUT, C, OUT

A

C

B OUT

AND OUT, A, B

AOI


Complex Gate StructuresTo understand the conversion use the n-channels. The AND branch (using A and B inputs) iscombined with the OR stack (input C). This results in a two input AND driving a two input OR.

And-Or gate AND symbolic_node, input_node1, input_node2

AOI output_node, input_node3, symbolic_node


Complex Gate Structures

OR

OAI OUT

A

C

OR

B

OAI OUT, C, OUT

A

C

B OUT

OR OUT, A, B

OAI


Complex Gate StructuresTo understand the conversion use the n-channels. The OR branch (using A and B inputs) iscombined with the AND stack (input C). This results in a two input OR driving a two inputAND.

Or-And gate OR symbolic_node, input_node1, input_node2

OAI output_node, input_node3, symbolic_node


LVS Capability Overview

■ Device Reduction and Parameter Consolidation

■ Device Parameter Comparison

■ Flexible Comparison Tolerances



Device Reduction and Parameter Consolidation

When comparing a schematic to a layout, there may be a number of structural differencesbetween them that should not be considered real errors, only different representations of thesame circuit. Examples are different configurations of devices whose parametric value andfunction is equivalent.

Device Parameter Comparison

In order to compare device parameters between layout and schematic, SKILL procedures thatcontain methods of property evaluation and comparison need to be called by an LVS function.These SKILL procedures determine tolerances for comparison and error messages to bedisplayed in the compared views.

Flexible Comparison Tolerances

Tolerances for comparison may be modified. Effective gate width and lengths may also bemodified to achieve more accurate comparison results.


LVS Comparison Behavior

BA

Z

Device Reduction and

MOS Input Swapping

p p p

w/l w/l wsum/lavg

r

r

.5 r

(no lvschk option needed)

(no lvschk option needed)

Parameter Consolidation



These behaviors do not require the specification of options for Dracula LVS. These behaviorsprovide flexibility during the comparison.

MOS Input Swapping Relaxes constraint of matching input terminals to gates when thelogical function of the gate is the same.

Device Reduction andParameter Consolidation

All parallel devices are reduced in both the schematic and layout.The formula for capacitor parameter consolidation is:

cfinal = c1 + c2

For resistors:rfinal = 1 / ( 1 / r1 + 1 / r2 )

For MOSFET width and length:wfinal = ( w1 + w2 )

lfinal= ( l1 + l2 ) / 2

You use smash-cap-type = yes in the description block to reduceparallel capacitors which have different subtypes.



BA

ZProhibit Input Swapping

p p p

w/l w/l 2w/l

r

r

.5 r

lvschk[x]...

Reduce Series Resistors

lvschk[r]...

r r 2r

lvschk[k]...

Prohibit Parallel Reduction



Prohibit Input Swapping You use this option to perform an exact transistor-to-transistorcomparison.

Reduce Series Resistors You use this option to reduce series resistors.The formula for parameter consolidation is:

rfinal = r1 + r2

Prohibit ParallelReduction

You use this option to prohibit all devices from being reduced.



Series MOS Reduction w/l w/l

lvschk[s]...

CMOS Gate Reduction

lvschk[c]...

w/l w/l

A ZA Z

Reduce Series Capacitors

lvschk[a]...

c c .5 c

mos

mos

inv

wsum/lavg

wsum/lavg



Reduce Series Capacitors You use this option to reduce capacitors in series. The formula forcapacitor series parameter consolidation is:

cfinal = 1 / ( 1 / c1 + 1 / c2 )

Series MOS Reduction You use this option to reduce all series MOS configurations thatare parallel. This includes MOS configurations that function asfully parallel logic but have no intermediate series connection.The formula for width and length parameter consolidation is the same forstandard device reduction.

CMOS Gate Reduction You use this option to reduce all MOS devices into the highestequivalent CMOS gate-level structure. Consolidating MOSdevices to the gate level speeds LVS error resolution.


LVS Parameter Comparison

Corner Effect Factored Against Width

lvschk weffect = .56

Parameter Tolerance

lvschk wpercent = 10 lpercent = 10

lvschk resval = 10 capval = 10

winital

wfinal = winital - ( weffect * length * bends )

length

bends


LVS Parameter Comparison

Parameter Tolerance You use these tolerance functions to measure parameters and setcomparison tolerances. All tolerance comparisons reference theschematic. You use wpercent and lpercent for MOS widths andlengths. You use resval and capval for resistor and capacitorvalue parameters.Other tolerance functions:

w/l-percent - for MOS w/l ratiocaparea - for capacitance areadioarea - for diode areadioperi - for diode perimeterresarea - for resistor areaeaper - for emitter areamoscap-area - for MOS capacitor area

You use unspec-para = yes in the description block to printunknown layout and schematic device parameters in the<printfile>.lvs report.

Corner Effect FactoredAgainst Width

You use weffect to include corner effect while the systemmeasures parameters.


Dracula LVS Report Format

■ Identify Each Section of the Report

■ Understand the Purpose of Each Section




LVS Report Format Overview

Header and LVSNET Information

Layout Reduction and

Schematic Reduction Summary

Run Options Summary

Main Body LVS Report

LVS Repeat Summary


LVS Error ReportHeader and LVSNET Information

Contains execution time, software version and top cell name. LVSNET Summary Reportreports netlist processing information.

Layout Reduction and Run Options Summary

Contains device counts before and after layout device reduction as well as comparison options.Good spot check to see how many devices LVS found and how it performed device reduction.


Contains device counts before and after schematic reduction. Compare this with the layoutreduction.


Contains LVS Run Options, Correspondence Node Pairs, LVS Device Matching, DiscrepancyPoints Listing, Discrepancy Points Summary and Device Matching by Type. Most of yourtime is spent here working with Discrepancy Points.

LVS Repeat Summary

Contains the Device Match Summary, the Discrepancy Points Summary and Device Matchingby Type.


Header and LVSNET Information

******************************************************************************* */N* DRACULA ( REV. 4.1.0494 / CADENCE /GENDATE: 18-APR-94/18 ) *** ( Copyright 1994, Cadence ) *** */N* EXEC TIME =19:08:11 DATE =10-NOV-94 *******************************************************************************

INDISK PRIMARY CELL :

ECADTOPLEVEL

*********** LVSNET SUMMARY REPORT ***********

WEFFECT VALUE= 0.0000000


Header and LVSNET InformationHeader

Dracula version information and execution time.

Top Level Cell

Name of the top-level cell you specified.

LVSNET Information

Reports the value used for corner effect. Used for the measurement of bent gates.



Pmos

Nand

Nmos

A

B

Y YA

B


LVS Device ReductionProvides various device-grouping methods for LVS analysis. Device reduction reduces thenumber of devices in both the layout and schematic. This improves the speed of comparisonand permits more flexibility in the creation of the design.


Layout Reduction and Options Summary

REDUCE (LAYOUT) SUMMARY REPORT *******

******* STATISTICS BEFORE REDUCE ****

MOS BJT RES DIODE CAP UND BOX CELL LDD 202209 0 0 0 0 0 0 0 0

OPTION TO SMASH PARALLEL DEVICES IS -- ON OPTION TO CONSTRUCT MOS PARALLEL/SERIES STRUCTURES IS -- ON OPTION TO SMASH PSEUDO PARALLEL DEVICES IS -- ON OPTION TO FORM CMOS GATES IS -- ON

******* STATISTICS AFTER REDUCE **** MOS BJT RES INV DIODE CAP SDWI PDWI SUPI 30864 0 0 26369 0 0 28672 48 0 PUPI SDW PDW SUP PUP AND OR AOI NAND

0 1223 899 512 450 0 0 0 65 NOR OAI UND BOX CELL LDD SMID PMID MOSCAP

1755 0 0 0 0 0 0 0 26


Layout Reduction and Options SummaryStatistics

The Statistics section is a Good spot check to see how many layout devices Dracula found andhow it managed device reduction. The report lists before and after reduction. The number ofdevices in both reports must be the same. If any devices in the UND group exist before or afterreduction, make sure you start solving for errors there first.

Reduction Options

Various options are used to reduce devices during comparison. This summary verifies whichoptions were set when the LVS was started. The more reduction options you use, the lower thenumber of final devices are compared.



******* REDUCE (SCHEMATIC) SUMMARY REPORT *******


MOS BJT RES DIODE CAP UND BOX CELL LDD 156017 0 0 0 0 0 0 0 0

******* STATISTICS AFTER REDUCE **** MOS BJT RES INV DIODE CAP SDWI PDWI SUPI

30864 0 0 26369 0 0 28672 48 0 PUPI SDW PDW SUP PUP AND OR AOI NAND

0 1223 899 512 450 0 0 0 65 NOR OAI UND BOX CELL LDD SMID PMID MOSCAP

1755 0 0 0 0 0 0 0 26


Schematic Reduction SummaryStatistics

Good spot check to see how many schematic devices Dracula found and how managed devicereduction. The report lists before and after reduction. The number of devices in both layoutand schematic reports after reduction must be the same. This is the device count Dracula willbe using to perform the comparison. If any devices in the UND group exist before or afterreduction, make sure you start solving for errors there first.


Main Body LVS ReportExecution Time and Run Options List

***************** LVS REPORT *****************

DATE : 10-NOV-94 TIME : 19:26:52

PRINTLINE = 9999 WPERCENT(MOS) = 5.000 % LPERCENT(MOS) = 1.000 % RESISTOR WIDTH CHECK: RESWPR= 1.000 % RESISTOR LENGTH CHECK: RESLPR= 5.000 %


Main Body LVS ReportExecution Time

Dracula version information and execution time.

Run Options

These are command line options for Dracula to control error output listing, tolerances fordevice size checking and others. The percent figure for tolerances represents a window whichis placed on either side of the schematic device size value. If the layout values are outside thiswindow an error is reported. The smaller a percentage, the tighter the tolerance.



VDD:P

CLK

IN2

IN1

Layout

VDD:P

CLK

IN2

IN1

Schematic/Netlist

EDTEXT File


Initial Correspondence Node PairsTo resolve ambiguity and speed up LVS, initial correspondence point pairs should be set upbetween layout and schematic netlist. These points establish a starting place for thecomparison. Any net or device parameter can be used as a correspondence point.

If correspondence points are not set, Dracula starts the comparison with automatch. This modelets comparison proceed without correspondence points (power and ground nodes using :Pand :G must be defined, however).

You can also create a file containing the names of node pairs for LVS. The command thatspecifies the node pair file is cpoint-file = filename.

You use the TEXT-PRI-ONLY command to keep lower-level text from appearing in thecomparison. This would raise text that is not useful and perhaps confuse your efforts to resolveerrors.


Main Body LVS ReportCorrespondence Node Pairs

1 *************************************************** ********* CORRESPONDENCE NODE PAIRS *********** ***************************************************

SCHEMATICS LAYOUT PAD TYPE

VCC 1 VCC 1 P VSS 2 VSS 3 G IR1R0ACREGOPS<9> 434 IR1R0ACREGOPS<9> 1521 I IR1R0AMREGOPS<60> 185 IR1R0AMREGOPS<60> 1560 I***TOTAL = 721***

/*W WARNING : LIST OF SCHEMATIC PADS HAVE NO LAYOUT CORRESPONDENCE IR1W0A2SETSEL<5> 100 I IR1W0A2SETSEL<4> 101 I***TOTAL = 66***

/*W WARNING : LIST OF LAYOUT PADS HAVE NO SCHEMATIC CORRESPONDENCE IQSELMVOUT 8776 WRENIN2 702***TOTAL = 38***

.. BIG SCH NODE : VCC 1 CONN = 2643 .. BIG SCH NODE : VSS 2 CONN = 154 ** WARNING ** UN-LABELED BIG SCH NODE = 2781 CONN = 1416*/W* WARNING -- 4 PADS ARE FLOATING, AND DROPPED FROM INITIAL CORRESPONDING PAIRS! PLEASE CHECK .lvs DISCREPANCY REPORT

NUMBER OF VALID CORRESPONDENCE NODE PAIRS = 717


Main Body LVS ReportCorrespondence Node Pairs

Checks the essentials of continuity - did the number of pads in the layout match the schematic

Do not attempt to continue error resolution when any pads either from layout or schematic aredropped or known pads or significant nodes are not matched. These must be fixed first.

Warnings issued about either layout or schematic pads without correspondence may or maynot be of immediate significance.

Unlabeled big nodes are not a problem, necessarily, but Dracula issues a warning.

Try to reduce the number of unnecessary correspondence nodes. Your job will run faster andbe easier to debug.


Main Body LVS ReportDevice Match Summary

1 *************************************************** ********** LVS DEVICE MATCH SUMMARY ********** ***************************************************

NUMBER OF UN-MATCHED SCHEMATICS DEVICES = 256 NUMBER OF UN-MATCHED LAYOUT DEVICES = 256 NUMBER OF MATCHED SCHEMATICS DEVICES = 90627 NUMBER OF MATCHED LAYOUT DEVICES = 90627



Device Match Summary

Ultimately, you want the unmatched devices in both schematic and layout to be 0. The numberof matched devices in both should be equal. If you have 0 unmatched devices this does notnecessarily mean you have no errors. Pads connected nowhere, unmatched device sizes, etc.are still problems you solve for in the discrepancy points listing.


Main Body LVS ReportDiscrepancy Points

1 *************************************************** ********** DISCREPANCY POINTS LISTING ********** ***************************************************

** WARNING ** SCHEM PAD : INAPHI2 636 CONNECTED TO NOTHING

*************************** DISCREPANCY 1 *********************************

--- NODE N8048 ---WITH UN-MATCHED DEVICES-------

OCCURRENCE NAME N8048 ?DEV172915 INV : ***** UN-MATCHED ***** N8048, IRLPHI1<1>

***** UN-MATCHED ***** : ?DEV219010 INV: X=2814.00 Y=3040.30

N8048, ?IRLPHI1<1>

TOTAL 260 DISCREPANCY POINTS REPORTED

1 *************************************************** ********** DISCREPANCY POINTS SUMMARY ********** ***************************************************

2 MATCHED NODE TO NO DEVICE 2 MATCHED NODE TO EXTRA SCHEMATIC DEVICES 256 MATCHED NODE TO UN-MATCHED LAYOUT AND SCHEMATIC DEVICES




Provides a detailed examination of 15 separate error types. The format of the discrepancypoints section has the schematics on the left and the layout on the right. Each discrepancy isnot one error - Dracula may look at the error in several ways. This can help you resolve errorsfaster. Each discrepancy point will be either node or device-based depending on the error type.Each discrepancy point may contain a number of occurrences of nodes connected to the areain question.

When devices or nodes are not matched they are prefixed by a question mark and instead ofthe matching device, a string stating un-matched is printed instead.

The schematic side shows nets expanded hierarchically through the schematic netlist. Thelayout side shows a labelled node or a node internally generated by Dracula.

The summary contains all the error types used to categorize errors and the number ofdiscrepancy points found in each category.

When you see pads connected to nothing, solve these errors first.


Main Body LVS ReportDetailed Device Matching Summary

*************************************************** ******** DEVICE MATCHING SUMMARY BY TYPE ******** ***************************************************

TYPE SUB-TYPE TOTAL DEVICE UN-MATCHED DEVICESCH. LAY. SCH. LAY.

MOS N 107338 107338 256 256 MOS P 48667 48667 256 2561 *************************************************** ********** UN-MATCHED SCHEMATIC DEVICES ********** ********** (LIST UP TO 100 ) ********** ***************************************************

OCCURRENCE NAME N8048 ?DEV172915 INV : ***** UN-MATCHED ***** N8048, IRLPHI1<1> ?DEV151090 MOS P ---- M151090 : ***** UN-MATCHED ***** IRLPHI1<1>, VCC, N80481 *************************************************** ********** UN-MATCHED LAYOUT DEVICES ********** ********** (LIST UP TO 100 ) ********** ***************************************************

: ?DEV218750 INV : X=697.20 Y=2986.60 N7264, ?8074



Detailed Device Match Summary

List all devices by device type. Reports all unmatched devices on both the schematic side andthe layout side. The number of unmatched devices should be 0. The total device counts aretaken after reduction and the values should be equal.


LVS Repeat Summary

1 *************************************************** ********** LVS SUMMARY (REPEATED) ********** ***************************************************

*************************************************** ********** LVS DEVICE MATCH SUMMARY ********** ***************************************************

NUMBER OF UN-MATCHED SCHEMATICS DEVICES = 256 NUMBER OF UN-MATCHED LAYOUT DEVICES = 256 NUMBER OF MATCHED SCHEMATICS DEVICES = 90627 NUMBER OF MATCHED LAYOUT DEVICES = 90627

*************************************************** ********** DISCREPANCY POINTS SUMMARY ********** ***************************************************

2 MATCHED NODE TO NO DEVICE 2 MATCHED NODE TO EXTRA SCHEMATIC DEVICES 256 MATCHED NODE TO UN-MATCHED LAYOUT AND SCHEMATIC DEVICES

*************************************************** ******** DEVICE MATCHING SUMMARY BY TYPE ******** ***************************************************

TYPE SUB-TYPE TOTAL DEVICE UN-MATCHED DEVICE SCH. LAY. SCH. LAY.

MOS N 107338 107338 256 256 MOS P 48667 48667 256 256


LVS Repeat SummaryThis is the section of the report you give to your boss to prove you found all the errors. Itcontains three sections previously seen in the report. Unmatched devices should be 0, nodiscrepancy points should be present and there should be no unmatched devices for all devicetypes. Keep this for documentation.


LVS Debugging Methods

■ Understand Basic Internal Flow of Comparison

■ Learn Methods of Finding Errors with Dracula LVS


LVS Debugging Methods


LVS Internal Flow

Open Databases

1Filter All

4

and Top Cell Unused Devices

Build Map of

6

Correspondence

Reduce Devices

5

as AllowedExpand All Data

2

Top Cell Down

Extract Devices

3

and Parameters

Trace Inward

7

from Pads

Perform

9

Comparison

Build Device

8

and Node Map

Points


LVS Internal Flow

Steps one, two and three - both schematic and layout databases are opened. All connectivityand devices are recognized and measured.

Steps four, five and six - unused devices are dropped from consideration. Remaining devicesare reduced to their lowest common equivalent in both schematic and layout. Correspondencepoints are checked and a mapping file is created.

Steps seven, eight and nine - Dracula attempts tracing from the established correspondencepoints to all devices in the design. As Dracula traces it builds a map of all devices and internalnodes encountered. After all possible tracing is complete, Dracula performs the comparison.


Texting is Everything (almost)

Preventative Questions:

■ Which text layer is used?

■ Are text origins placed correctly on shapes?

■ Is case sensitivity an issue?

■ Are you using top level text only?


Texting is Everything

The Dracula extraction process imports all layers from the layout database. It expects text tobe present on layers specified in the code instructions. If continuity is dependent on virtualwiring, an open circuit will be formed from missing text.

In the extraction process text is associated with shapes by overlapping the shape with theorigin of the text. If the origin is not on either the interior, the edge, or the vertex of the shape,no association will be made.

If case of the original Stream text is preserved (where a mix of lower and upper case exists)these texts must match schematic case.

During processing, Dracula pulls text from the entire database at all hierarchical levels. Thiscan cause a number of errors when the text or text layer in lower level cells is the same as padtext.


Texting is Everything (almost)

The Analytical Question:

Were text labels spelled correctly? (don’t just blame the layout)

■ First look at shorts, floats and opens (in lvs.log)

■ Check address bit numbers (and spelling in general)

■ Check supply suffixes

■ Check virtual wire suffixes


Texting is Everything (continued)

Here’s an example of the shorts, floats and opens report:---------------------- ALL ERROR CELLS LISTING ----------------------

ERRSHT12 ERROPN12 ERRFLT12

BEGIN AT TIME =12:04:15 DATE = 8-NOV-94

INDISK PRIMARY CELL : ECADTOPLEVEL

CELL ERROPN12 DELETED BECAUSE OF NO OUTPUT DATA

---------------------------- OUTPUT CELL SUMMARY -----------------------------

CELL-NAME LAYER # ---------- W I N D O W ----------

DATATYPE # OF POLYGONS

TEXTS

(LINE SEGMENTS)

ERRSHT12 14/ 0 4.00 495.90 616.20 499.40 5 0

ERRFLT12 14/ 0 0.00 -44.00 1496.30 554.00 3693 0

OUTDISK PRIMARY CELL : OUTECADTOPLEVEL

WINDOW : 0.00 -44.00 1496.30 554.00

*/W* WARNING ** TEXT : IR1E3MVSETSEL<5> 256 SHORT DISCARDED

*/W* WARNING ** TEXT : IR1E3MVSETSEL<4> 256 SHORT DISCARDED


Device Reduction

Are the numbers of devices after reductionthe same for layout and schematic?

■ Check the filter options

■ Check the reduction options

■ Check the reduction group UND for any devices

■ Check the log file for schematic processing errors (in lvs.log)


Device Reduction

Here’s an example of the schematic circuit processing report:

FILE iregbot.lvs INPUT

ENCOUNTERED 0 ERRORS ( 690 WARNINGS) DURING FILE INPUT

CIRCUIT FILE INPUT AND PROCESSED

ENTER COMMAND

: con TOP

TRANSISTOR LEVEL FILE :LVSLOGIC CREATED

NUMBER OF TRANSISTORS, ELEMENTS & CELLS : 5618

************** element,ixmxr,node= 5618 500000 3366

Here’s an example of the reduction options summary:


MOS BJT RES DIODE CAP UND BOX CELL LDD

8529 0 0 0 0 0 0 0 0

OPTION TO SMASH PARALLEL DEVICES IS -- ON

OPTION TO CONSTRUCT MOS PARALLEL/SERIES STRUCTURES IS -- ON

OPTION TO SMASH PSEUDO PARALLEL DEVICES IS -- ON

OPTION TO FORM CMOS GATES IS -- ON


Correspondence Points

Don’t continue without resolving the following:

■ Unmatched pad text

■ Unconnected pad text

■ Discarded pads text

■ Pads with no correspondence whose number of connections match anunlabeled big node of the other design (may not be an error)

Try using:

■ ABORT-P-G-SHORT for an initial run (stops at shorted supplies nodes)

■ Look in the log file for the X:Y coordinates for Dracula’s estimated locationof the shorted nodes


Correspondence Points

Here’s an example of unconnected pad texts from the report:

*/W* WARNING -- 4 PADS ARE FLOATING, AND DROPPED FROM INITIAL

CORRESPONDING PAIRS! PLEASE CHECK .lvs DISCREPANCY REPORT

NUMBER OF VALID CORRESPONDENCE NODE PAIRS = 89

1 ***************************************************

********** DISCREPANCY POINTS LISTING **********

***************************************************


** WARNING ** LAYOUT PAD : INAPHI2 155 CONNECTED TO NOTHING


** WARNING ** LAYOUT PAD : INAPHI1 154 CONNECTED TO NOTHING


Discrepancy Points Analysis

General Methods:

■ Familiarity with the layout will save lots of time

■ Scan the report for repetition of problem nodes or devices.

■ Look for numeric coincidence with devices or nodes

— Unmatched devices

— Problem nodes with the same number of connections

■ Associate multiple discrepancy points

■ If you find a major error - fix it and run LVS again

— You save lots of time debugging

— Resolution of big errors open up trace paths

— Propagation of errors is greatly reduced





Specific Methods:

■ Start with a matched node as a reference point (error types 4, 5 and 6)

— Focus on specific occurrences for a different ‘flavor’

■ Start with a matched device as a reference point (error type 2)

— Focus on specific occurrences

■ Find the X:Y location of other unmatched layout devices (error type 7)

— Devices which are blocked from tracing by discrepancy points

■ Locate schematic nodes by hierarchical name

■ Use matched portions of key nodes or devices as reference




Methods Summary

Before you run LVS

■ Check your texting

After you run LVS

■ Start with text checks

■ Make sure numbers of reduced devices match between schematic andlayout

■ Use a combination of general and specific methods during analysis ofdiscrepancy points


Methods Summary

Before LVS

Text can never be checked too much. For every text error, hundreds more may occur.

After LVS

Start with checking text. Then continue with checking numbers of devices after reduction.


Labs

Lab 9-1. Create an LVS Command File


Parasitic Device Extraction 10-1

Parasitic Device Extraction

Objectives

■ Learn Command Syntax and Applications

■ Create Command Files for General Parasitic Extraction

■ Edit Command Files for Resistive Parasitic Extraction



LPE Layout Parasitic Extraction – the general extraction of parasiticdevices.

PRE Parasitic Resistance Extraction – the extraction ofresistive/capacitive networks.


Parasitic Extraction Overview

■ Generates Parasitic Netlists in SPICE or CDL Format

■ Optional Back-annotation uses Net Names from Schematic Netlists

■ Extracts Parasitic Capacitors, Diodes and Resistors

Netlist Formatting

Parasitic Device

Extraction

LVS and

Device Checking

1 2

3

and Creation


Parasitic Extraction Overview

Parasitic device extraction is the process of finding all components formed through theinteraction of layers created during fabrication of the design. Because of the qualities inherentin parasitic devices, circuit performance can be adversely affected. Therefore, modeling adesign with its parasitic devices is important.

The first step includes parasitic device recognition and parasitic device extraction.

Second, an LVS comparison is performed on the design. Checking the scope of deviceparameters is optional; LVS is mandatory. Forcing LVS to run on any design prior to LPEinsures the physical design is correct before proceeding with LPE.

Third, you determine what devices get printed in the netlist, whether the netlist uses schematicnet names and how the netlist is formatted.


Parasitic Capacitance Extraction

parasitic cap[m] metal1 metal1 metal1

and metal1 poly1 mpcap

attribute cap[m] 2.5 .00025

parasitic cap[n] mpcap metal1 poly1

attribute cap[n] .0005 .00025

Fringe Capacitance

Plate Capacitance


Parasitic Capacitance ExtractionPlate capacitance is formed between two overlapping layers on different nets. There can bemany different plate capacitances extracted in a design and they can share the same nets.Plate capacitance is measured by the area of layer overlap and the oxide permittivity andthickness.

Fringe capacitance is formed between two adjacent layers on different nets. There can bemany different fringe capacitances extracted in a design and they can share the same nets.Fringe capacitance is measured by the distance between the edges of adjacent layers,adjacent edges length and the oxide permittivity.


Parasitic Diode Extraction

parasitic dio[n] ndio pwell ndio

and pwell nres ndio

Diode Effects

Source/Drain Area and Perimeter

lextract pcard nsd by node xnsd

attach mos[n] xnsd

parset pcard area peri ; set in the desc block

for SPICE simulation


Parasitic Diode ExtractionDiode effects are found between P-type and N-type junctions. Commonly, modeling isperformed on the junctions of source/drain diffusions and their wells. Perimeter of thediffusion shape and the diffusion area can be modeled.

Diodes can also be formed between resistors and the resistor’s body. With changes inbiasing voltage junction effects may influence circuit performance.


General Parasitic Extraction

and metal1 poly1 mpcap

parasitic cap[n] mpcap metal1 poly1

attribute cap[n] .0005 .00025

Parasitic Layer

Parasitic Device

lpeselect[s] mos output lpenet

lpeselect[s] cap[n] gt .1e-12 &

lpechk[k]

lextract pcard nsd by node xnsd

attach mos[n] xnsd

Identification

Extraction

Source and DrainArea/Perimeter

Netlist Creation

ParameterDeclaration

parset pcard area peri ; desc block


General Parasitic Extraction

Parameter Declaration - parset declares variables to be used with lextract. You put parset inthe description block. parset is used in order to print area and perimeter of source/drains in theSPICE netlist.

Parasitic Layer Identification - You use layer processing commands to derive layers thatwould uniquely identify the parasitic devices. This technique is the same as finding therecognition layer for designed devices.

Parasitic Device Extraction - You use the parasitic cap, dio and res commands to extractdevices. You use attribute to assign properties for each device type. These properties will beused later to create a netlist.

Source and Drain Area/Perimeter - You use the parset to define the internal equations for areaand perimeter. You use lextract to extract the values of source/drain regions and you useattach to fix the values on their corresponding devices.

Netlist Creation - You use lpeselect to print all required elements to form a suitable netlist forsubsequent simulation. With lpeselect cap you specify a threshold value for parasitic capacitorsize. Values below the this threshold will not be included in the netlist. The output netlistfilename is limited to six characters and will be created with .DAT extension. If you do notspecify a device type lpeselect prints all types of the named device.


Parasitic Resistance Extraction

■ Extraction of Resistive/Capacitive Networks

■ ‘PI’ Model of Coupling and Fringe Capacitances

■ User-threshold Shorts Insignificant Parasitic Resistances

metal1metal1 metal1


Parasitic Resistance Extraction

The parasitic resistance extraction process fractures the input resistor material into twopieces.The first piece is the resistive element. The second piece are the resistor terminals.

You can extract capacitance of the resistive elements. This capacitance is distributed over eachresistive element using a ‘PI’ model. Coupling capacitance can also be extracted and lumpedinto the ‘PI’ model.

You specify a threshold value to ignore resistive elements too small to consider.


Command File forParasitic Resistance Extraction (PRE)

First Phase Second Phase

Cross Reference Map

LVS

Device Extraction

Node Connections

Device Re-extraction

Node Re-connection

Resistor andTerminal Creation

Parasitic Extraction

Final Netlist Creation

for Back-annotation(Automatically Made)

Command File


Command File for Parasitic Resistance Extraction (PRE)

The first phase of the command file contains commands for extraction of designed devices andconnectivity. After LVS comparison an internal map is built which will be used forcross-reference of node names.

The second phase of the command file contains all PRE-related commands. These commandsextract the parasitic resistances and redefine various parts of the database with the updatedlayers that PRE requires.

Redefinition of connectivity and layers is necessary because PRE changes nets into devices.This reorders the entire database network.


Second Phase of PRE Command File

pad-layer = Vapox

Pad Layer Terminal Creation

rconnect-layer pwell psd nsd ptrm mtrm

Redefine Connectivity with New Terminal Layers

rconnect metal1 mtrm by contact

stamp mtrm by metal1

cut-term metal1 contact mres mtrm

Parasitic Resistor and Resistor Terminal Creation1

2

3

cut-term poly1 contact pres ptrm gate

; above command is set in the input-layer block



Step1 - You use cut-term to find all areas of terminals and bodies of parasitic resistances. Youspecify the input layer, contact layer, resistor body layer and the terminal layer (the terminallayers will be used later during PRE redefinition).

Step 2 - For termination of resistances at pads you use pad-layer. You specify the layerrepresenting oxide openings where bonding will take place.

Step 3 - You redefine connectivity with rconnect-layer. You use the same format as theconnect-layer and connect commands, except you use the new resistance layers derived withcut-term.



element mos[n] ngate ptrm nsd pwell

Extract Designed Devices and

Parasitic Devices with New Terminal Layers

parasitic res[m] mres mtrm

lpeselect[s] mos &

Generate Final Netlist

4

5

lpeselect[s] res gt .01 output prenet

attribute res[m] .04


Second Phase (continued)

Step 4 - You extract designed devices and parasitic devices using the new resistance layers youderived with cut-term. You specify the sheet resistance with the attribute command.

Step 5 - You create the PRE netlist using lpeselect. You specify a threshold under whichparasitic resistors will not be printed.


Netlist Formatting Options

■ Model Naming

■ Unit Scaling of Parameters

■ Parasitic Device Character Prefixing

■ Top-level Circuit Naming


Netlist Formatting Options

You set these options in the description block.

Model Naming - You use model to specify an equivalence between the model names in thenetlist to the models used by the simulator:model = mos[n],nmos mos[p],pmos

Unit Scaling of Parameters - Use of unit is mutually exclusive with the specification of unitsin calculations in the command file:unit = capacitance,pf area,p perimeter,u resistance,r

Parasitic Device Character Prefixing - You use prefix-parasitic to specify initial characters fora device in the netlist:prefix-parasitic = cap,c dio,d res,rn

Top-level Circuit Naming - You use subckt-name to provide a name for the top-level subcktname in the output SPICE or CDL netlist file. The default top-level subcircuit name will bethe same as the netlist file name. subckt-name uses a maximum of 16 characters:subckt-name = fifo


Labs

10-1. Create and Execute a Command File for General Parasitic Extraction

10-2. Execute and Modify a Command File for Parasitic Resistance Extraction



Appendix A

Dracula Flat Master Command File

Appendix Title sg.Template.app Appendix A

8/11/94 Cadence Design Systems, Inc. A-1

;******************************************************;;File: dracula.master;;Description:Dracula flat master command file for; bicmos process ArtLib library;;Author: Craig Thayer;;Date: 5/6/94;;******************************************************;*description;;Data related parametersindisk = /usr1/mnt/user1/Dracula ;Current working directorylibrary = artLibprimary = artchip ;Top celloutdisk = artchip ;Error file nameschematic = LVSLOGIC;Compiled netlist file name;;System related parameterssystem = cadencemode = exec nowprogram-dir = /usr1/cadence/tools/dracula/bin/resolution = .25 micron;Minimum working resolutionscale = .001 micron ;DBU per user unitstext-pri-only = yes ;Use top level text onlykeepdata = yes ;No .DAT files will be deleted;;Parasitic related commandssubckt-name = artchipunit = capacitance,pf area,p perimeter,umodel = mos[n],n mos[p],p bjt[n],npn bjt[p],pnp res[p],p cap[n],ncap[mp],mp;; Cell Deletion Listdelcel = logo;*end

*input-layer;nwell = nwellpwell = pwell

Appendix A Appendix Title sg.Template.app

A-2 Cadence Design Systems, Inc. 8/11/94

epi = epiPRES = PRESNPLUS = NPLUSPPLUS = PPLUSthinox = thinoxactive = activepbase = pbasepoly1 = poly1contact = contactmetal1 = metal1 text = text attach metal1Vapox = Vapoxmask = mask;; Temporary Layer Assignmenttemporary-layer = contact psd tmp1;; Mask Sequenceconnect-layer = epi nwell pwell pemit psd termres pbase nsd poly1 metal1;*end

*operation;; device recognition layers and terminals;; mosfetand active NPLUS ndiffand active PPLUS pdiffnot ndiff poly1 nsd ;n-source/drainnot pdiff poly1 psd ;p-source/drainand ndiff poly1 ngate;n-channeland pdiff poly1 pgate;p-channel;; p-resistorand contact PRES tmp1 ;resistor contactsize tmp1 by 1.5 termres;resistor terminalnot PRES termres resp ;pres rec. layer;; n-capacitorand thinox metal1 tmp1and tmp1 nsd ncap ;ncap rec. layer;; npnand nsd pbase npn ;npn recognition layer;; pnp



and psd epi tmp1ext[hr] tmp1 le 10 pnp ;pnp recognition layerand pnp psd pemit ;pnp emitter terminalnot psd pemit psd ;adjusted psd layer;; pseudo contact for pbasenot pbase nsd tmp1 ;block out nsd contactand contact tmp1 pcont ;pbase contactnot contact pcont contact;adjusted contact; pseudo contact for well tiesor nwell epi nminus ;epi and nwell combinednot nsd pbase tmp1 ;block out nsd in pbaseand tmp1 nminus ntap ; n-type well tiesand psd pwell ptap ; p-type well ties;;; connectivity extraction;connect metal1 poly1 by contactconnect metal1 nsd by contactconnect metal1 psd by contactconnect metal1 pemit by contactconnect metal1 termres by contactconnect metal1 pbase by pcont;all soft-connect layers using pseudo-contactsconnect nsd epi by ntapsconnect nsd nwell by ntapsconnect psd pwell by ptap;;*break DRC;;well checkswidth pwell lt 2.5 output pwwid 1enc active pwell lt .5 output pwenc 1width nwell lt 2.5 output nwwid 1enc active nwell lt .5 output nwenc 1;;diffusion checkswidth[p] active lt 1.5 output acwid 2ext active lt 1.5 output acext 2enc active PPLUS lt .25 output ppenc 2enc active NPLUS lt .25 output npenc 2enc contact active lt .5 output acenc 2;;poly1 checks

Appendix A Appendix Title sg.Template.app

A-4 Cadence Design Systems, Inc. 8/11/94

width poly1 lt 1 output p1wid 3ext poly1 lt 1 output p1ext 3enc active poly1 lt 1.5 output p1aenc 3enc contact poly1 lt .75 output p1cenc 3;;metal1 checkswidth metal1 lt .75 output m1wid 4ext metal1 lt .75 output m1ext 4enc contact metal1 lt .5 output m1cenc 4ext[t] metal1 poly1 lt .75 &length metal1 gt 20 output fm1sep 4;;contact checkswidth contact lt 1 output cowid 5ext contact lt 1 output coext 5;;pad checkswidth Vapox lt 18 output vawid 6enc metal1 Vapox lt 1 output vaenc 6;;; device extraction;; moselement mos[n] ngate poly1 nsd pwellelement mos[p] pgate poly1 psd nwell; p-reselement res[p] resp termresparameter res[p] 200 ;sheet resistance of 200 ohms/square; n-capelement cap[n] ncap metal1 nsdparameter cap[n] 9e-15 ;nine femto farads capacitance/square; n-cap; npnelement bjt[n] npn epi pbase nsd; pnpelement bjt[p] pnp psd epi pemit;;; erc commands;*break ERC;;detect opens and shortssamelab output open 1multilab output short 1



;;detect incorrectly connected or floating wellslconnect pwell disc gnd output flpwel 1lconnect nwell disc vdd output flnwel 1;;detect floating gatespathchk level 4 output flgate 1;;detect soft-connect problemssoftchk pwell output[u] err 1;;; lpe commands;*break LPE;;and metal1 poly1 mpcap;parasitic cap[mp] mpcap metal1 poly1;attribute cap[mp] .05e-12 .01e-12;;lpechk[k];lpeselect[skn] mos corner = .56 &;lpeselect[sn] bjt &;lpeselect[sn] cap[n] &;lpeselect[sn] cap[mp] gt .1e-12 &;lpeselect[sn] res[p] output lpenet;;; lvs command;*break LVS;lvschk[cars] wpercent=10 lpercent=10 resval=10 capval=10;*end

Appendix B

Command Quick Reference

Command Quick Reference Appendix B

2/16/95 Cadence Design Systems, Inc. B-1


and layerA layerB outLayer

or layerA layerB outLayer

xor layerA layerB outLayer

not layerA layerB outLayer

select layerA relation [[lowrange:uprange]] layerB outLayer[output name num]

size[[options]] layerA [within layerB] by value [outLayer][output name num]

grow layerA xvalue yvalue [outLayer] [output name num]

shrink layerA xvalue yvalue [outLayer] [output name num]

probe label [outLayer] [output name num]

plength layerA range n1 n2 [outLayer] [output name num]

substrate = layerA n

relation insideoutsideenclosevertexcuttouchholelabel[r]overlap

option a - outputs data with acute angles onlyb - error flag widthg - outputs data with no problems onlyl - error flag lengthn - for mask fractureo - inhibits merge on oversizep - inhibits merge before undersizer - outputs data with potential integrity problems onlys - avoids creation of data sliverst - outputs trapezoid format dataw - forces cut line width to .5 microns


B-2 Cadence Design Systems, Inc. 2/16/95

DRC Commands

Specific options are different and are listed for each command.

measure refers to one of: lt, le, gt, ge, sellt, selle, selgt or selge.

area layerA range n1 n2 [outLayer] [output name num]

width[[options]] layerA measure n1 [n2] [outLayer] [output name num]

ext[[options]] layerA [layerB] measure n1 [n2] [outLayer][output name num]

enc[[options]] layerA layerB measure n1 [n2] [outLayer][output name num]

option c, c’ - parallel edges only, non-parallel edges onlyp, p’ - projecting edges only, non-projecting edges onlyr, r’ - generate error region, trapezoid errorss - square corner checking

option c, c’ - parallel edges only, non-parallel edges onlye - flags complete enclosureg - flags overlapping shapes’ areash - notch checking onlyn, n’ - checks connected shapes, unconnected shapes - all hierarchical levelso - overlapping edgesp, p’ - projecting edges only, non-projecting edges onlyr, r’ - generate error region, trapezoid errorss - square corner checkingt - adds touching edges to error flagsu, u’ - checks connected shapes, unconnected shapes - composite level onlyv - checks through ’walls’ of edges

option c, c’ - parallel edges only, non-parallel edges onlye - flags complete enclosuren, n’ - checks connected shapes, unconnected shapes - all hierarchical levelso - overlapping edgesp, p’ - projecting edges only, non-projecting edges onlyr, r’ - generate error region, trapezoid errorss - square corner checkingt - adds touching edges to error flagsu, u’ - checks connected shapes, unconnected shapes - composite level onlyv - checks through ’walls’ of edges



DRC Commands (continued)

int[[options]] layerA layerB measure n1 [n2] [outLayer][output name num]

length layerA measure n1 [n2] [output name num](must be used in conjunction with width, int, enc or ext)

plength layerA range n1 n2 [outLayer] [output name num](must be used with a layer generated with t and r options)

option c, c’ - parallel edges only, non-parallel edges onlye - flags complete enclosuren, n’ - checks connected shapes, unconnected shapes - all hierarchical levelsp, p’ - projecting edges only, non-projecting edges onlyr, r’ - generate error region, trapezoid errorss - square corner checkingt - adds touching edges to error flagsu, u’ - checks connected shapes, unconnected shapes - composite level onlyv - checks through ’walls’ of edges



ERC Commands

econnect dev[[type]] termLayer conn/disc label [outLayer]output name num

elcount dev[[type]] termLayer measure n1 [outLayer] output name num(measure is one of lt, le, eq, ne, gt or ge)

lconnect layerA conn/disc label [outLayer] output name num

multilab [outLayer] output name num

ndcount dev[[type]] physTerm measure n1 [outLayer] output name num(measure is one of lt, le, eq, ne, gt or ge)

pathchk[[f/x]] level 1-4 [outLayer] output name num(f or x options are for level 4 only)

probe netName output name num

pull-up = label [label...]

pull-down = label [label...]

samelab [outLayer] output name num

softchk wellLayer [outLayer] output[u/a] name num



LVS Commands

lvschk[[options]] [subcommands]

options a - reduces series capacitorsb - inhibits reduction of bipolar devicesc - reduces circuit to CMOS gate-level (nand, nor ...)e - uses device sizes to eliminate circuit mapping ambiguity during comparisonf - filters unused devicesg - filters devices from schematic and layoutk - inhibits reduction of parallel devicesl - inhibits reduction of circuit to CMOS complex gates (and/or, nor/nand ...)o - reduces circuit to standard structures without need of power/ground connectionsp - inhibits terminal swapping of capacitors during comparisonr - reduces resistors in both parallel and seriess - reduces series-stacked MOS configurationsu - reports only matched schematic and unmatched layout devices on matched nodesx - inhibits terminal swappingz - filters devices with no connection to a texted pad

subcommands wpercent = n - tolerance for comparison of MOS widthlpercent = n - tolerance for comparison of MOS lengthw/l-percent = n - tolerance for comparison of MOS width and lengthcaparea = n -tolerance for comparison of capacitor areacapval = n - tolerance for comparison of capacitor value in faradsdioarea = n - tolerance for comparison of diode areadioperi = n - tolerance for comparison of diode perimeterressize = n - tolerance for comparison of resistor squaresresval = n - tolerance for comparison of resistor value in ohmseaper = n - tolerance for comparison of emitter areamoscap-area = n - tolerance for comparison of capacitive area of MOS devicesmuldelw = n - value for compensation of multiple finger MOS deviceslistunmatch = n - maximum number of unmatched devices reportedprintline = n - maximum number of disciplines to be reportedweffect = n - value to compensate width measurements for corner effectbjtwpercent = n - tolerance for comparison of bipolar base widthbjtlpercent = n - tolerance for comparison of bipolar base lengthreslpercent = n - tolerance for comparison of resistor lengthreswpercent = n - tolerance for comparison of resistor width



LVS Commands (continued)

lvs-option = a/b/c/d/e/f/g/h/i/j/l/m

lvsrpt-only = yes/no

parameter cap[[type]] areaCoefficient perimeterCoefficient

parameter res[[type]] ohmsPerSquare

schematic = filename

smash-cap-type = yes/no

unspec-sch-para = yes/no/except-substrate

unspec-lay-para = yes/no/except-substrate

unspec-para = yes/no/except-substrate



Device Extraction Commands

element mos[[type]] recogLayer gate source/drain [substrate]

element bjt[[type]] recogLayer collector base emitter [substrate]

element res[[type]] recogLayer resTerm [substrate]

element cap[[type]] recogLayer pos neg [substrate]

element dio[[type]] recogLayer anode cathode [substrate]

element <macro name> recogLayer term1 [term2 term3 term4]

element pad vapoxLayer metalLayer

element ldd[[type]] recogLayer gate source/drain [substrate]

Connectivity Extraction Commands

connect layerA layerB by contactLayer

sconnect diffLayer wellLayer by tapLayer

connect-layer = layerA layerB ...

text-sequence = layerA layerB ...

stamp layerA by layerB [output[[u]] name num]

link layerA to label



Parasitic Extraction Functions

model = device[type],modelName ...

unit = name,scale ...

prefix-parasitic = parasitic,prefix ...

subckt-name = topSubcircuitName

diodeseq = a1 p1 [a2 p2 a3 p3]

parasitic dio[type] recogLayer anode cathode [notLayer1 notLayer2]

Parasitic resistance:

rconnect-layer = layerA layerB ...

pad-layer = layerName

cut-term inputLayer contactLayer resLayer termLayer [devTerms...][maxns=<value>] [maxwidth=<number>]

rconnect layerA layerB by contactLayer

parasitic res[type] recogLayer termLayer negLayer

attribute res[type] sheetRes

Parasitic plate capacitance:

parasitic cap[type] recogLayer posLayer negLayer

attribute cap[type] areaCapacitance perimeterCapacitance

Parasitic fringe capacitance:

parasitic cap[type] layerA layerA layerA

attribute cap[type] distanceCoefficient lengthCoefficient



lpeselect[[options]] device[[type]] [ge/gt/range value1 [value2]][corner = n] [output filename] [&]

options a - includes selection of parasitic capacitances on power and ground netsc - selects coupling capacitanceg - uses schematic names for ground netsk - inhibits reduction of parallel devicesl - inhibits terminal swappingn - requests SPICE formatp - selects coupling capacitors as a percentage of total load capacitancer - prints area and perimeter of capacitors to netlists - backannotate schematic net names to netlisty - reports x/y location of transistors in the lpeselect listing

device mosdiocapbjtres



Parasitic Extraction Functions (continued)

lpechk[[options]] [subcommands]

options b - inhibits reduction of bipolar devicesc - reduces circuit to CMOS gate-level (nand, nor ...)e - uses device sizes to eliminate circuit mapping ambiguity during comparisonf - filters unused devicesk - inhibits reduction of parallel devicesl - inhibits reduction of circuit to CMOS complex gates (and/or, nor/nand ...)o - reduces circuit to standard structures without need of power/ground connectionsp - inhibits terminal swapping of capacitors during comparisonr - reduces resistors in both parallel and seriess - reduces series-stacked MOS configurationsu - reports only matched schematic and unmatched layout devices on matched nodesx - inhibits terminal swapping

subcommands wpercent = n - tolerance for comparison of MOS widthlpercent = n - tolerance for comparison of MOS lengthw/l-percent = n - tolerance for comparison of MOS width and lengthcaparea = n -tolerance for comparison of capacitor areacapval = n - tolerance for comparison of capacitor value in faradsdioarea = n - tolerance for comparison of diode areadioperi = n - tolerance for comparison of diode perimeterressize = n - tolerance for comparison of resistor squaresresval = n - tolerance for comparison of resistor value in ohmseaper = n - tolerance for comparison of emitter areamuldelw = n - value for compensation of multiple finger MOS deviceslistunmatch = n - maximum number of unmatched devices reportedprintline = n - maximum number of disciplines to be reportedweffect = n - value to compensate width measurements for corner effectbjtwpercent = n - tolerance for comparison of bipolar base widthbjtlpercent = n - tolerance for comparison of bipolar base lengthreslpercent = n - tolerance for comparison of resistor lengthreswpercent = n - tolerance for comparison of resistor width



Hierarchical Dracula C-1

Hierarchical Dracula

Objectives

■ Learn DRC Hierarchical Methods

■ Learn LVS Hierarchical Methods

2/16/95 Cadence Design Systems, Inc. C-2



DRC Hierarchy Concept

TOP

CELL1

TOP

CELL2 CELL1 CELL2


DRC Hierarchy Concept

Dracula can only check two levels of hierarchy. The system creates hierarchical cells (Hcells)with its own algorithm from your design which, of course, may contain many levels.

Hcell Creation

Hcells are created automatically by Dracula with the following (abbreviated) criteria:

■ Cells’ boundary must be greater than twice the largest value used by a DRC command.

■ Cells must contain a number of edges exceeding 4 times the number of input layers.

■ Cells must be placed more than once.

If you wish to override the default conditions which Dracula uses there are several commandsprovided. You can indirectly declare your own Hcells through the following commands:

■ hcell-rule command - override the default minimum number of cell placements andedges required by the system.hcell-rule = 1,10 ; one instance and ten edges in cell

■ not-hcell command - prevent creating an Hcell from a specified cell.not-hcell = pnp ; prevent pnp from becoming an Hcell

■ hcell and hcell-file commands - provides priority consideration for named cells whendecisions involving parent-child relationships exist.hcell = inv2 or hcell-file = hcells.list


Hierarchical DRC Error Output

Composite to Composite

Hcell to Hcell

Hcell to Composite

Inside Hcell

Environment Area

Detailed Summary For Cell And Cell-comp Errors


Hierarchical DRC Error Output

Hierarchical processing decreases runtimes for designs using repetitive cell patterns throughthe hierarchy. There are three modes of hierarchical error reporting using cell-error-rep:

■ once - default operation. All errors found inside multiple instances of Hcells are storedonce in the top level overlay cell.

■ hier - creates error cells you overlay in the Hcell as well as the top level.

■ all - creates an error cell with all errors sent to the top level. Renders hierarchical errorsas flat error checking would display them.

Hierarchical Checking

Each Hcell of the design hierarchy is checked independently and errors found are written tothe error cell. If cell-error-rep = hier is set each Hcell will have its own error cell created.

Dracula checks Hcell to Hcell at various levels of hierarchy and writes the errors to thetop-level error cell in which both the checked cells are placed.

For Hcell to composite checks an environment area is defined by the system. The environmentarea is determined by the largest DRC value specified in the command file. Composite tocomposite checks are also made. Errors are written to the top level.

Hierarchical Summary

Hierarchical DRC creates Hcell listings in summary files. A matrix of total errors found byerror type, checking relationship and Hcell name is created.


Multi-level DRC Operation

Initial Compilation

Directory Creation

Multi-level Runfile

Data Directoriesand

Final Compilation

Runfile Creation

and

Data Directory

xflatram1inv2pnpdff

User Defined Name

System Defined Hcells

(4 Placements and1024 *# of Input Layers)

1 2


Multi-level DRC Operation

First, change check-mode = multi in your description block. The initial PDRACULAcompilation runs CDSIN and EXPAND modules and stops. This stage finds all Hcells andcreates directories for them. A directory is also created for all flat data. A control file namedjxmult.com is created to submit all individual directory runs at once.

The final compilation creates the jxrun.com files for all multi-level Hcells and stores them intheir directories. Multi-level Hcell requirements are different than two-level Hcells: 4placements and number of edges = 1024 * number of input layers. This program is designedfor really big designs.

Errors are found in the same fashion as in two-level HDRC. This script demonstrates use ofmulti-level DRC:

cd DataPDRACULA << ! > pdrac.log/g ../$1 multi/f!jxrun.com > drcmult.logPDRACULA << ! >> pdrac.log/g ../$1/f!jxmult.com >>& drcmult.log &


LVS Hierarchical Concept

comp Modecell Mode(Using frame by )

comp Mode

(Using black-box )

Run cell ModeRun comp Modeand Generate

Hcell Text File

Create black-box

OR

File or

cellbndy Layer


LVS Hierarchical Concept

Cell Mode

Checks only Hcells. Each Hcell master is checked once. The Hcells may be defined by the useror the system.

Composite Mode

Checks only composite or top-level data. Treats all Hcells like ‘black boxes’. No data of anyHcell is checked. Composite mode does not check over-the-cell routing.

The frame by command permits a ‘halo’ of data around the periphery of an Hcell to beincluded for LVS. If you have non-rectangle cells use the cellbndy command. It specifies alayer that can be used to draw the non-rectangle shape HLVS uses as the cell boundary.

For cells with internal pins black-box command can be used. This command references a fileyou create containing Hcell names and their respective I/Os including pin names, x and ycoordinates and pin dimensions.


Hierarchical LVS Operation(Automatic Hcell Selection)

Initial Compilation

Runfile Creation

Final Hcell File

and Initial

hcell.file

ram1

inv2

User Defined Hcell File Name

System Defined Hcells

(1 Placement and2 *# of Input Layers)

ramcell frame by 2

Final Compilation

Runfile Creation

and

Run LOGLVS

Hcell File Creation

and Final

1 3

4

Processed Netlist

Runfile Execution2

Hcell File Creation

and Initial

Runfile Execution

5

inv2


Hierarchical LVS Operation

1. You run the initial PDRACULA compilation with the auto keyword. This creates thejxauto.com file:

:/g lvs.hier auto

2. You start the job. This step finds all HCELLs.

3. You run LOGLVS. This cross-references the HCELLs and creates a final HCELL list.The schematic netlist is also created:

:cell/auto hcell.file

4. You make another compilation of the run file with PDRACULA using the HCELL filethat was created in the last step.

5. You start the final run.

The final compilation creates the jxrun.com files for all multi-level HCELLs. Hcellrequirements are : 1 placements and number of edges = 2 * number of input layers.

Errors are found in the same fashion as in flat LVS.


Automatic Texting of Cellsfor Hierarchical LVS

Minimal Texting

Database

Final Hcell Text File

of Cells in

hcell_text.file

CLK x=34 y=50 Attach=metal1 inv2

• • •

User Defined Hcell Text File Name

System Defined Cell Texts

Run LVS

in comp Mode

1

3

Run LVS2

Create Hcell Text

in cell Mode and

CLK x=34 y=50 Attach=metal1 dff


Automatic Texting of Cells for Hierarchical LVS

Minimum Cell Texting

You must text ground, power and one input or output of each cell before automatic textgeneration will work. You determine the Hcell text file name.

Run LVS in cell Mode

Then you run LVS in cell mode. LVS will generate a hierarchical Hcell text file usingGen-text. All cells in the top-level design selected as Hcells will be checked against theirrespective schematic cells. At this time the system ensures cell text between schematic andlayout matches.

After this the final Hcell file is created.

Run LVS in comp Mode

Now you run LVS in comp mode to check the interface areas of all Hcells including thecomposite interconnect between your layout and schematic designs.


Hierarchical Lab

Lab C-1. Running Hierarchical DRC



Appendix D

LVS Error Types

LVS Error Types D-1

LVS Error Types

Objectives

■ Understand the Various Error Types

■ Learn to Interpret Error Types

2/16/95 Cadence Design Systems, Inc. D-2


LVS Error Types D-3

Error Type Overview

■ There are 15 Error Types

■ All Errors are Found in the Discrepancy Points Listing

■ Each Error Type Found Indicates One Error

■ Each Error may be Represented by Several Error Types

■ Each Discrepancy Point Represents One Error

■ Each Error may be Represented by Many Discrepancy Points


Error Type OverviewError Type # Error Type Description

1 Matched node to no device

2 Matched device to unmatched node

3 Inconsistently matched devices

4 Matched node to extra layout devices (missing schematic devices)

5 Matched node to extra schematic devices (missing layout devices)

6 Matched node to unmatched layout and schematic devices

7 Other unmatched layout devices

8 Other unmatched schematic devices

9 Device sub-type mismatch

10 Device size mismatch

11 MOS reversibility error

12 Device substrate connection mismatch

13 Device power connection mismatch (multiple power supplies)

14 Reduced layout parallel MOS devices

15 Filtered-out layout MOS devices

LVS Error Types D-5

Error Type 1

Matched Node to No Device

Schematic Layout

Open


Error Type 1

Matched Node to No Device

Check your initial correspondence nodes for proper connection to the circuit (perhaps inputprotection or buffers are disconnected). Check layout texts for the correct layer and location.

1 ***************************************************

********** DISCREPANCY POINTS LISTING **********

***************************************************


************************* DISCREPANCY 1 ********************************

--- NODE INAPHI2

( 636)-CONNECT TO NO DEVICE------

LVS Error Types D-7

Error Type 2

Matched Device to Unmatched Node

Schematic Layout

?numberA3


Error Type 2

Matched Device to Unmatched Node

LVS reports a node name prefixed by ‘?’ instead of the schematic name. Applies to bothschematic and layout. Search for this error node elsewhere in the discrepancy points section.

************************** DISCREPANCY 1 **********************************

----------------------------------------MATCHED DEVICE UN-MATCHED NODE---------

OCCURRENCE NAME MVWRSELB<5>

*DEV7328 INV : *DEV10250 INV

: X=611.70 Y=475.40

MVWRSELB<5>, ?IR1E3MVSETSEL<5> MVWRSELB<5>, IR1E3MVSETSEL<4>

LVS Error Types D-9

Error Type 3

Inconsistently Matched Devices

Schematic Layout

A3 ?A4


Error Type 3

Inconsistently Matched Devices

Parts of the circuit may be blocked from further tracing by the establishment of discrepancypoints. Dracula will take a guess at identifying those blocked portions. Differences betweenlocal blocked portions and the surrounding circuitry are implied here.

************************** DISCREPANCY 2 **********************************

-----------------------------------------INCONSISTENTLY MATCHED DEVICE------


*DEV7328 INV : *DEV10250 INV

: X=611.70 Y=475.40

MVWRSELB<5>, ?IR1E3MVSETSEL<5> MVWRSELB<5>, IR1E3MVSETSEL<4>

LVS Error Types D-11

Error Type 4

Matched Node to Extra Layout Devices

Schematic Layout

Key matched node


Error Type 4Matched Node to Extra Layout Devices

Specific nodes that have found a match during the comparison are ‘key’ nodes with respect tothe error type. Flags extra layout devices on key nodes.


Error Type 5

Matched Node to Extra Schematic Devices

Schematic LayoutKey Matched Node


Error Type 5

Matched Node to Extra Schematic Devices

Specific nodes that have found a match during the comparison are ‘key’ nodes with respect tothe error type. Flags extra schematic devices on key nodes.

*************************** DISCREPANCY 4 *********************************

--- NODE IRLPHI1<1>

---WITH EXTRA SCH DEVICES--------

OCCURRENCE NAME N8048

?DEV172915 INV : ***** UN-MATCHED *****

N8048, IRLPHI1<1>

OCCURRENCE NAME N7775

?DEV172918 INV : ***** UN-MATCHED *****

N7775, IRLPHI1<1>


Error Type 6

Matched Node to Unmatched Layout

Schematic Layout

Key matched node

and Schematic Devices


Error Type 6

Matched Node to Unmatched Layout and Schematic Devices

Specific nodes that have found a match during the comparison are ‘key’ nodes with respect tothe error type. Flags devices on key nodes that are connected to different nodes.

*************************** DISCREPANCY 3 *********************************

--- NODE IR1E3MVSETSEL<4>

---WITH UN-MATCHED DEVICES-------


DEV7327 INV : DEV10251 INV

: X=616.30 Y=475.40

MVWRSELB<4>, IR1E3MVSETSEL<4> MVWRSELB<4>, IR1E3MVSETSEL<4>

***** UN-MATCHED ***** : *DEV10250 INV

: X=611.70 Y=475.40

MVWRSELB<5>, IR1E3MVSETSEL<4>


Error Type 7

Other Unmatched Layout Devices

?

Layout Discrepancies Block Trace


Error Type 7

Other Unmatched Layout Devices

Parts of the layout circuit may be blocked from further tracing by the establishment ofdiscrepancy points. Dracula will take a guess at identifying those blocked portions. Theseerrors result when no resolution is achieved between local blocked portions and thesurrounding circuitry.


Error Type 8

Other Unmatched Schematic Devices

?

Schematic Discrepancies Block Trace


Error Type 8

Other Unmatched Schematic Devices

Parts of the schematic circuit may be blocked from further tracing by the establishment ofdiscrepancy points. Dracula will take a guess at identifying those blocked portions. Theseerrors result when no resolution is achieved between local blocked portions and thesurrounding circuitry.


Error Type 9

Device Sub-type Mismatch

N P

Schematic Layout


Error Type 9Device Sub-type Mismatch

Where two matched devices use different sub-types. Check for improper material implants ordevices.


Error Type 10

Device Size Mismatch

W = 10

L = .5

W = 6

L = .5

Schematic Layout


Error Type 10

Device Size Mismatch

Where two matched devices have different device sizes. Check for schematic values, improperlayout devices (or parameters if it’s a pcell) or unusually tight comparison tolerance.

************************** DISCREPANCY 264 **********************************

DEV5860 MOS N ---- M5860 : DEV6364 MOS N

: X=309.60 Y=322.50

N2561, VSS, ALLPHI1<1> N2561, VSS, ALLPHI1<1>

W = 91.00 L = .50 W = 76.00 L = .50

** WARNING ** 2 SCHEMATIC MOS DID NOT SPECIFY LENGTH


Error Type 11

MOS Reversibility Error

Schematic Layout

A

B

C

C

A

B


Error Type 11

MOS Reversibility Error

Where the structure of a stack (or group of parallel structures in a stack) is rearranged betweenthe schematic and layout with relationship to the output of the structure. Using the reductionoption to construct MOS parallel/series structures avoids this error.


Error Type 12

Device Substrate Connection Mismatch

Schematic Layout

gndagnd


Error Type 12

Device Substrate Connection Mismatch

Where two matched MOS devices’ substrate terminals are connected to different nodes.Check for improper well ties.


Error Type 13

Device Power Connection Mismatch

Schematic Layout

vcc2:P vcc1:P


Error Type 13Device Power Connection Mismatch

Where matched devices are connected to the wrong power supply of a multiple-power supplydesign. These power supplies must be suffixed with :P.


Error Type 14

Reduced Layout Parallel MOS Devices


Error Type 14Reduced Layout Parallel MOS Devices

When the option to inhibit parallel reduction of devices is off (default behavior), all devicesin parallel are reduced to one device. All other devices originally used for the reduction arenow disregarded. This error type flags those devices. This is only for reference and is not anderror condition.


Error Type 15

Filtered-out Layout MOS Devices

vdd

vdd


Error Type 15

Filtered-out Layout MOS Devices

When the option to filter specific devices is on, unused MOS devices are filtered out (in gatearray applications, for instance). This error type flags those devices. This is only for referenceand is not and error condition.

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