Upload
hadien
View
302
Download
8
Embed Size (px)
Citation preview
NXP Semiconductors
Document Number: DPAA2_User_ManualRev. 2, 05/2016
DPAA2 User Manual
Freescale, the Freescale logo, CodeWarrior, and QorIQ are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the
property of their respective owners. ARM, ARM Powered, and Cortex are registered
trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved.
© 2015–2016 Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers
to use Freescale products. There are no express or implied copyright licenses granted
hereunder to design or fabricate any integrated circuits based on the information in this
document. Freescale reserves the right to make changes without further notice to any
products herein.
Freescale makes no warranty, representation, or guarantee regarding the suitability of its
products for any particular purpose, nor does Freescale assume any liability arising out of
the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters that
may be provided in Freescale data sheets and/or specifications can and do vary in different
applications, and actual performance may vary over time. All operating parameters, including
“typicals,” must be validated for each customer application by customer's technical experts.
Freescale does not convey any license under its patent rights nor the rights of others.
Freescale sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: freescale.com/SalesTermsandConditions.
DPAA2_User_ManualRev. 2, 05/2016
How to Reach Us:
Home Page: nxp.com
Web Support: nxp.com/support
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 1
ContentsParagraphNumber Title
PageNumber
Contents
Chapter 1 Introduction
1.1 Intended audience ............................................................................................................ 1-21.2 Definitions and acronyms ................................................................................................ 1-2
Chapter 2 Overview
2.1 Introduction to DPAA2 objects........................................................................................ 2-12.1.1 Network objects ........................................................................................................... 2-22.1.1.1 Data Path Network Interface (DPNI) ...................................................................... 2-22.1.1.2 Data Path MAC (DPMAC)...................................................................................... 2-22.1.1.3 Data Path Switch (DPSW)....................................................................................... 2-22.1.1.4 Data Path Demux (DPDMUX)................................................................................ 2-32.1.1.5 Data Path Link Aggregator (DPLAG)..................................................................... 2-32.1.2 DPAA2 infrastructure objects ...................................................................................... 2-42.1.2.1 Data Path Buffer Pool (DPBP) ................................................................................ 2-42.1.2.2 Data Path I/O Portal (DPIO).................................................................................... 2-42.1.2.3 Data Path Concentrator (DPCON)........................................................................... 2-42.1.3 Accelerator interfaces .................................................................................................. 2-52.1.3.1 Data Path Security Interface (DPSECI)................................................................... 2-52.1.3.2 Data Path De/Compression Interface (DPDCEI) .................................................... 2-52.1.3.3 Data Path DMA Interface (DPDMAI)..................................................................... 2-62.1.4 Management and control objects ................................................................................. 2-72.1.4.1 Data Path Communication Interface (DPCI) ........................................................... 2-72.1.4.2 Data Path Resource Container (DPRC)................................................................... 2-72.1.4.3 Data Path MC Portal (DPMCP)............................................................................... 2-72.2 Objects topology and inter-connect ................................................................................. 2-82.2.1 Connection and link state........................................................................................... 2-102.2.2 Typical object connections......................................................................................... 2-102.2.3 How and when to connect.......................................................................................... 2-12
Chapter 3 Boot and Initialization Process
3.1 Loading the MC firmware ............................................................................................... 3-13.2 Data Path Configuration (DPC)....................................................................................... 3-13.3 Data Path Layout (DPL) .................................................................................................. 3-13.4 Starting MC...................................................................................................................... 3-2
DPAA2 User Manual, Rev. 2, 05/2016
2 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
Chapter 4 MC Firmware Versions
4.1 Firmware command reference ......................................................................................... 4-24.1.1 DPMNG_GET_VERSION.......................................................................................... 4-2
Chapter 5 Management Command Portals
5.1 Overview of command portals......................................................................................... 5-15.2 Command portal usage .................................................................................................... 5-15.3 DPAA2 objects control through command portals .......................................................... 5-25.4 Command portals memory map....................................................................................... 5-25.5 Management command portal definition ......................................................................... 5-35.6 MC General Command Portals command reference ....................................................... 5-65.6.1 DPMNG_GET_CONT_ID .......................................................................................... 5-6
Chapter 6 DPRC: Data Path Resource Container
6.1 DPRC features ................................................................................................................. 6-16.2 DPRC functional description ........................................................................................... 6-26.2.1 Resource container creation......................................................................................... 6-26.2.2 Objects assignment ...................................................................................................... 6-26.2.3 Objects discovery......................................................................................................... 6-26.3 DPRC command reference .............................................................................................. 6-36.3.1 DPRC_OPEN............................................................................................................... 6-36.3.2 DPRC_CLOSE ............................................................................................................ 6-46.3.3 DPRC_CREATE_CONTAINER ................................................................................. 6-56.3.4 DPRC_DESTROY_CONTAINER.............................................................................. 6-66.3.5 DPRC_RESET_CONTAINER.................................................................................... 6-86.3.6 DPRC_SET_IRQ......................................................................................................... 6-96.3.7 DPRC_GET_IRQ ...................................................................................................... 6-106.3.8 DPRC_SET_IRQ_ENABLE ..................................................................................... 6-126.3.9 DPRC_GET_IRQ_ENABLE..................................................................................... 6-136.3.10 DPRC_SET_IRQ_MASK ......................................................................................... 6-156.3.11 DPRC_GET_IRQ_MASK......................................................................................... 6-166.3.12 DPRC_GET_IRQ_STATUS...................................................................................... 6-186.3.13 DPRC_CLEAR_IRQ_STATUS................................................................................. 6-206.3.14 DPRC_GET_ATTRIBUTES ..................................................................................... 6-216.3.15 DPRC_SET_RES_QUOTA....................................................................................... 6-236.3.16 DPRC_GET_RES_QUOTA ...................................................................................... 6-246.3.17 DPRC_ASSIGN......................................................................................................... 6-266.3.18 DPRC_UNASSIGN................................................................................................... 6-27
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 3
ContentsParagraphNumber Title
PageNumber
6.3.19 DPRC_GET_POOL_COUNT................................................................................... 6-286.3.20 DPRC_GET_POOL................................................................................................... 6-306.3.21 DPRC_GET_OBJ_COUNT ...................................................................................... 6-326.3.22 DPRC_GET_OBJ ...................................................................................................... 6-346.3.23 DPRC_GET_OBJ_DESC.......................................................................................... 6-366.3.24 DPRC_GET_RES_COUNT ...................................................................................... 6-386.3.25 DPRC_GET_RES_IDS ............................................................................................. 6-406.3.26 DPRC_GET_OBJ_REGION..................................................................................... 6-426.3.27 DPRC_SET_OBJ_LABEL........................................................................................ 6-446.3.28 DPRC_SET_OBJ_IRQ.............................................................................................. 6-456.3.29 DPRC_GET_OBJ_IRQ ............................................................................................. 6-466.3.30 DPRC_CONNECT .................................................................................................... 6-486.3.31 DPRC_DISCONNECT.............................................................................................. 6-496.3.32 DPRC_GET_CONNECTION ................................................................................... 6-50
Chapter 7 DPNI: Data Path Network Interface
7.1 DPNI features .................................................................................................................. 7-17.2 DPNI functional description ............................................................................................ 7-27.2.1 Ingress frame processing ............................................................................................. 7-27.2.2 Egress frame processing .............................................................................................. 7-47.2.3 Relationship with DPIO and DPCON objects ............................................................. 7-57.2.4 Relationship with DPBP objects.................................................................................. 7-67.2.5 Ingress QoS.................................................................................................................. 7-67.2.6 Ingress distribution ...................................................................................................... 7-67.3 DPNI command reference ............................................................................................... 7-77.3.1 DPNI_CREATE........................................................................................................... 7-77.3.2 DPNI_DESTROY...................................................................................................... 7-117.3.3 DPNI_OPEN.............................................................................................................. 7-127.3.4 DPNI_CLOSE ........................................................................................................... 7-127.3.5 DPNI_ENABLE ........................................................................................................ 7-137.3.6 DPNI_DISABLE ....................................................................................................... 7-147.3.7 DPNI_IS_ENABLED................................................................................................ 7-157.3.8 DPNI_RESET............................................................................................................ 7-177.3.9 DPNI_SET_IRQ ........................................................................................................ 7-187.3.10 DPNI_GET_IRQ ....................................................................................................... 7-197.3.11 DPNI_SET_IRQ_ENABLE ...................................................................................... 7-217.3.12 DPNI_GET_IRQ_ENABLE...................................................................................... 7-227.3.13 DPNI_SET_IRQ_MASK........................................................................................... 7-247.3.14 DPNI_GET_IRQ_MASK.......................................................................................... 7-257.3.15 DPNI_GET_IRQ_STATUS ....................................................................................... 7-27
DPAA2 User Manual, Rev. 2, 05/2016
4 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
7.3.16 DPNI_CLEAR_IRQ_STATUS.................................................................................. 7-297.3.17 DPNI_GET_ATTRIBUTES ...................................................................................... 7-307.3.18 DPNI_SET_ERRORS_BEHAVIOR ......................................................................... 7-337.3.19 DPNI_GET_RX_BUFFER_LAYOUT...................................................................... 7-357.3.20 DPNI_SET_RX_BUFFER_LAYOUT ...................................................................... 7-367.3.21 DPNI_GET_TX_BUFFER_LAYOUT...................................................................... 7-387.3.22 DPNI_SET_TX_BUFFER_LAYOUT ...................................................................... 7-397.3.23 DPNI_GET_TX_CONF_BUFFER_LAYOUT ......................................................... 7-417.3.24 DPNI_SET_TX_CONF_BUFFER_LAYOUT.......................................................... 7-427.3.25 DPNI_SET_L3_CHKSUM_VALIDATION ............................................................. 7-447.3.26 DPNI_GET_L3_CHKSUM_VALIDATION............................................................. 7-447.3.27 DPNI_SET_L4_CHKSUM_VALIDATION ............................................................. 7-467.3.28 DPNI_GET_L4_CHKSUM_VALIDATION............................................................. 7-487.3.29 DPNI_GET_QDID .................................................................................................... 7-497.3.30 DPNI_GET_SP_INFO............................................................................................... 7-517.3.31 DPNI_GET_TX_DATA_OFFSET ............................................................................ 7-537.3.32 DPNI_GET_COUNTER ........................................................................................... 7-557.3.33 DPNI_SET_COUNTER ............................................................................................ 7-577.3.34 DPNI_SET_LINK_CFG............................................................................................ 7-587.3.35 DPNI_GET_LINK_STATE ....................................................................................... 7-597.3.36 DPNI_SET_TX_SHAPING ...................................................................................... 7-617.3.37 DPNI_SET_MAX_FRAME_LENGTH .................................................................... 7-627.3.38 DPNI_GET_MAX_FRAME_LENGTH.................................................................... 7-637.3.39 DPNI_SET_MTU ...................................................................................................... 7-657.3.40 DPNI_GET_MTU ..................................................................................................... 7-667.3.41 DPNI_SET_MULTICAST_PROMISC..................................................................... 7-687.3.42 DPNI_GET_MULTICAST_PROMISC .................................................................... 7-697.3.43 DPNI_SET_UNICAST_PROMISC .......................................................................... 7-717.3.44 DPNI_GET_UNICAST_PROMISC ......................................................................... 7-727.3.45 DPNI_SET_PRIMARY_MAC_ADDR..................................................................... 7-747.3.46 DPNI_GET_PRIMARY_MAC_ADDR.................................................................... 7-757.3.47 DPNI_ADD_MAC_ADDR....................................................................................... 7-777.3.48 DPNI_REMOVE_MAC_ADDR............................................................................... 7-787.3.49 DPNI_CLEAR_MAC_FILTERS .............................................................................. 7-797.3.50 DPNI_SET_VLAN_FILTERS .................................................................................. 7-807.3.51 DPNI_ADD_VLAN_ID ............................................................................................ 7-817.3.52 DPNI_REMOVE_VLAN_ID.................................................................................... 7-827.3.53 DPNI_CLEAR_VLAN_FILTERS ............................................................................ 7-837.3.54 DPNI_SET_TX_SELECTION.................................................................................. 7-847.3.55 DPNI_SET_RX_TC_DIST ....................................................................................... 7-857.3.56 DPNI_SET_RX_TC_POLICING.............................................................................. 7-90
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5
ContentsParagraphNumber Title
PageNumber
7.3.57 DPNI_GET_RX_TC_POLICING............................................................................. 7-927.3.58 DPNI_SET_RX_TC_EARLY_DROP....................................................................... 7-947.3.59 DPNI_GET_RX_TC_EARLY_DROP ...................................................................... 7-967.3.60 DPNI_SET_TX_TC_EARLY_DROP....................................................................... 7-987.3.61 DPNI_GET_TX_TC_EARLY_DROP .................................................................... 7-1007.3.62 DPNI_SET_RX_TC_CONGESTION_NOTIFICATION....................................... 7-1027.3.63 DPNI_GET_RX_TC_CONGESTION_NOTIFICATION ...................................... 7-1037.3.64 DPNI_SET_TX_TC_CONGESTION_NOTIFICATION ....................................... 7-1057.3.65 DPNI_GET_TX_TC_CONGESTION_NOTIFICATION....................................... 7-1077.3.66 DPNI_SET_TX_CONF........................................................................................... 7-1097.3.67 DPNI_GET_TX_CONF ...........................................................................................7-1117.3.68 DPNI_SET_TX_CONF_CONGESTION_NOTIFICATION.................................. 7-1147.3.69 DPNI_GET_TX_CONF_CONGESTION_NOTIFICATION................................. 7-1157.3.70 DPNI_SET_TX_FLOW .......................................................................................... 7-1187.3.71 DPNI_GET_TX_FLOW.......................................................................................... 7-1217.3.72 DPNI_SET_RX_FLOW .......................................................................................... 7-1237.3.73 DPNI_GET_RX_FLOW ......................................................................................... 7-1267.3.74 DPNI_SET_RX_ERR_QUEUE .............................................................................. 7-1287.3.75 DPNI_GET_RX_ERR_QUEUE ............................................................................. 7-1297.3.76 DPNI_SET_TX_CONF_REVOKE......................................................................... 7-1327.3.77 DPNI_SET_QOS_TABLE ...................................................................................... 7-1337.3.78 DPNI_ADD_QOS_ENTRY .................................................................................... 7-1367.3.79 DPNI_REMOVE_QOS_ENTRY ............................................................................ 7-1377.3.80 DPNI_CLEAR_QOS_TABLE ................................................................................ 7-1387.3.81 DPNI_ADD_FS_ENTRY........................................................................................ 7-1397.3.82 DPNI_REMOVE_FS_ENTRY................................................................................ 7-1407.3.83 DPNI_CLEAR_FS_ENTRIES ................................................................................ 7-1417.3.84 DPNI_SET_VLAN_INSERTION ........................................................................... 7-1427.3.85 DPNI_SET_VLAN_REMOVAL............................................................................. 7-1437.3.86 DPNI_SET_IPR....................................................................................................... 7-1447.3.87 DPNI_SET_IPF ....................................................................................................... 7-145
Chapter 8 DPBP: Data Path Buffer Pool
8.1 DPBP features.................................................................................................................. 8-18.2 DPBP command reference............................................................................................... 8-28.2.1 DPBP_OPEN............................................................................................................... 8-28.2.2 DPBP_CLOSE............................................................................................................. 8-38.2.3 DPBP_CREATE .......................................................................................................... 8-48.2.4 DPBP_DESTROY....................................................................................................... 8-58.2.5 DPBP_ENABLE.......................................................................................................... 8-6
DPAA2 User Manual, Rev. 2, 05/2016
6 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
8.2.6 DPBP_DISABLE......................................................................................................... 8-78.2.7 DPBP_IS_ENABLED ................................................................................................. 8-88.2.8 DPBP_RESET ........................................................................................................... 8-108.2.9 DPBP_SET_IRQ ....................................................................................................... 8-118.2.10 DPBP_GET_IRQ....................................................................................................... 8-128.2.11 DPBP_SET_IRQ_ENABLE...................................................................................... 8-148.2.12 DPBP_GET_IRQ_ENABLE..................................................................................... 8-158.2.13 DPBP_SET_IRQ_MASK.......................................................................................... 8-178.2.14 DPBP_GET_IRQ_MASK ......................................................................................... 8-188.2.15 DPBP_GET_IRQ_STATUS ...................................................................................... 8-208.2.16 DPBP_CLEAR_IRQ_STATUS ................................................................................. 8-228.2.17 DPBP_GET_ATTRIBUTES...................................................................................... 8-238.2.18 DPBP_SET_NOTIFICATIONS ................................................................................ 8-258.2.19 DPBP_GET_NOTIFICATIONS................................................................................ 8-26
Chapter 9 DPIO: Data Path I/O
9.1 DPIO features .................................................................................................................. 9-19.2 DPIO command reference ............................................................................................... 9-29.2.1 DPIO_OPEN................................................................................................................ 9-29.2.2 DPIO_CLOSE ............................................................................................................. 9-39.2.3 DPIO_CREATE........................................................................................................... 9-49.2.4 DPIO_DESTROY........................................................................................................ 9-59.2.5 DPIO_ENABLE .......................................................................................................... 9-69.2.6 DPIO_DISABLE ......................................................................................................... 9-79.2.7 DPIO_IS_ENABLED.................................................................................................. 9-89.2.8 DPIO_RESET............................................................................................................ 9-109.2.9 DPIO_SET_IRQ ........................................................................................................ 9-119.2.10 DPIO_GET_IRQ ....................................................................................................... 9-129.2.11 DPIO_SET_IRQ_ENABLE ...................................................................................... 9-149.2.12 DPIO_GET_IRQ_ENABLE...................................................................................... 9-159.2.13 DPIO_SET_IRQ_MASK........................................................................................... 9-179.2.14 DPIO_GET_IRQ_MASK.......................................................................................... 9-189.2.15 DPIO_GET_IRQ_STATUS ....................................................................................... 9-209.2.16 DPIO_CLEAR_IRQ_STATUS.................................................................................. 9-229.2.17 DPIO_GET_ATTRIBUTES ...................................................................................... 9-239.2.18 DPIO_SET_STASHING_DESTINATION ............................................................... 9-259.2.19 DPIO_GET_STASHING_DESTINATION............................................................... 9-269.2.20 DPIO_ADD_STATIC_DEQUEUE_CHANNEL ...................................................... 9-289.2.21 DPIO_REMOVE_STATIC_DEQUEUE_CHANNEL.............................................. 9-30
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7
ContentsParagraphNumber Title
PageNumber
Chapter 10 DPCON: Data Path Concentrator
10.1 DPCON features ............................................................................................................ 10-110.2 DPCON command reference ......................................................................................... 10-210.2.1 DPCON_OPEN ......................................................................................................... 10-210.2.2 DPCON_CLOSE ....................................................................................................... 10-310.2.3 DPCON_CREATE..................................................................................................... 10-410.2.4 DPCON_DESTROY ................................................................................................. 10-510.2.5 DPCON_ENABLE .................................................................................................... 10-610.2.6 DPCON_DISABLE................................................................................................... 10-710.2.7 DPCON_IS_ENABLED............................................................................................ 10-810.2.8 DPCON_RESET...................................................................................................... 10-1010.2.9 DPCON_SET_IRQ.................................................................................................. 10-1110.2.10 DPCON_GET_IRQ ................................................................................................. 10-1210.2.11 DPCON_SET_IRQ_ENABLE ................................................................................ 10-1410.2.12 DPCON_GET_IRQ_ENABLE ............................................................................... 10-1510.2.13 DPCON_SET_IRQ_MASK .................................................................................... 10-1710.2.14 DPCON_GET_IRQ_MASK.................................................................................... 10-1810.2.15 DPCON_GET_IRQ_STATUS................................................................................. 10-2010.2.16 DPCON_CLEAR_IRQ_STATUS ........................................................................... 10-2210.2.17 DPCON_GET_ATTRIBUTES ................................................................................ 10-2310.2.18 DPCON_SET_NOTIFICATION............................................................................. 10-25
Chapter 11 DPCI: Data Path Communication Interface
11.1 DPCI features................................................................................................................. 11-111.2 DPCI functional description .......................................................................................... 11-111.2.1 Connecting DPCI objects........................................................................................... 11-111.2.2 Relationship with DPIO and DPCON objects ........................................................... 11-111.2.3 Buffer requirements ................................................................................................... 11-211.3 DPCI command reference.............................................................................................. 11-211.3.1 DPCI_OPEN.............................................................................................................. 11-211.3.2 DPCI_CLOSE............................................................................................................ 11-311.3.3 DPCI_CREATE ......................................................................................................... 11-511.3.4 DPCI_DESTROY...................................................................................................... 11-611.3.5 DPCI_ENABLE......................................................................................................... 11-711.3.6 DPCI_DISABLE ....................................................................................................... 11-811.3.7 DPCI_IS_ENABLED ................................................................................................ 11-911.3.8 DPCI_RESET ...........................................................................................................11-1111.3.9 DPCI_SET_IRQ ...................................................................................................... 11-1211.3.10 DPCI_GET_IRQ...................................................................................................... 11-13
DPAA2 User Manual, Rev. 2, 05/2016
8 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
11.3.11 DPCI_SET_IRQ_ENABLE..................................................................................... 11-1511.3.12 DPCI_GET_IRQ_ENABLE.................................................................................... 11-1611.3.13 DPCI_SET_IRQ_MASK......................................................................................... 11-1811.3.14 DPCI_GET_IRQ_MASK ........................................................................................ 11-1911.3.15 DPCI_GET_IRQ_STATUS ..................................................................................... 11-2111.3.16 DPCI_CLEAR_IRQ_STATUS................................................................................ 11-2311.3.17 DPCI_GET_ATTRIBUTES..................................................................................... 11-2411.3.18 DPCI_GET_PEER_ATTRIBUTES......................................................................... 11-2611.3.19 DPCI_GET_LINK_STATE ..................................................................................... 11-2811.3.20 DPCI_SET_RX_QUEUE ........................................................................................ 11-3011.3.21 DPCI_GET_RX_QUEUE ....................................................................................... 11-3111.3.22 DPCI_GET_TX_QUEUE........................................................................................ 11-33
Chapter 12 DPDMUX: Data Path Network DeMux
12.1 DPDMUX features ........................................................................................................ 12-112.2 DPDMUX functional description .................................................................................. 12-212.2.1 Demux database......................................................................................................... 12-212.2.2 Broadcast and multicast support ................................................................................ 12-212.2.3 Promiscuous interfaces .............................................................................................. 12-212.2.4 Frames acceptance policy .......................................................................................... 12-312.3 DPDMUX command reference ..................................................................................... 12-312.3.1 DPDMUX_OPEN...................................................................................................... 12-312.3.2 DPDMUX_CLOSE ................................................................................................... 12-412.3.3 DPDMUX_CREATE................................................................................................. 12-512.3.4 DPDMUX_DESTROY.............................................................................................. 12-712.3.5 DPDMUX_ENABLE ................................................................................................ 12-812.3.6 DPDMUX_DISABLE ............................................................................................... 12-912.3.7 DPDMUX_IS_ENABLED...................................................................................... 12-1012.3.8 DPDMUX_RESET.................................................................................................. 12-1112.3.9 DPDMUX_SET_IRQ .............................................................................................. 12-1212.3.10 DPDMUX_GET_IRQ ............................................................................................. 12-1312.3.11 DPDMUX_SET_IRQ_ENABLE ............................................................................ 12-1512.3.12 DPDMUX_GET_IRQ_ENABLE............................................................................ 12-1612.3.13 DPDMUX_SET_IRQ_MASK................................................................................. 12-1812.3.14 DPDMUX_GET_IRQ_MASK................................................................................ 12-1912.3.15 DPDMUX_GET_IRQ_STATUS ............................................................................. 12-2112.3.16 DPDMUX_CLEAR_IRQ_STATUS........................................................................ 12-2312.3.17 DPDMUX_GET_ATTRIBUTES ............................................................................ 12-2412.3.18 DPDMUX_UL_SET_MAX_FRAME_LENGTH................................................... 12-2612.3.19 DPDMUX_IF_SET_ACCEPTED_FRAMES......................................................... 12-27
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9
ContentsParagraphNumber Title
PageNumber
12.3.20 DPDMUX_IF_GET_ATTRIBUTES....................................................................... 12-2812.3.21 DPDMUX_IF_REMOVE_L2_RULE..................................................................... 12-3012.3.22 DPDMUX_IF_ADD_L2_RULE............................................................................. 12-3112.3.23 DPDMUX_IF_GET_COUNTER............................................................................ 12-3212.3.24 DPDMUX_UL_RESET_COUNTERS ................................................................... 12-3412.3.25 DPDMUX_IF_SET_LINK_CFG ............................................................................ 12-3512.3.26 DPDMUX_IF_GET_LINK_STATE ....................................................................... 12-36
Chapter 13 DPSW: Data Path L2 Switch
13.1 DPSW features............................................................................................................... 13-113.2 DPSW functional description ........................................................................................ 13-213.2.1 Creating L2 switch instance....................................................................................... 13-213.2.2 VLAN configuration.................................................................................................. 13-213.2.3 Learning modes.......................................................................................................... 13-213.2.4 FDB configuration ..................................................................................................... 13-313.3 DPSW command reference............................................................................................ 13-313.3.1 DPSW_OPEN............................................................................................................ 13-313.3.2 DPSW_CLOSE.......................................................................................................... 13-413.3.3 DPSW_CREATE ....................................................................................................... 13-513.3.4 DPSW_DESTROY.................................................................................................... 13-713.3.5 DPSW_ENABLE....................................................................................................... 13-813.3.6 DPSW_DISABLE ..................................................................................................... 13-913.3.7 DPSW_IS_ENABLED ............................................................................................ 13-1013.3.8 DPSW_RESET ........................................................................................................ 13-1213.3.9 DPSW_SET_IRQ .................................................................................................... 13-1313.3.10 DPSW_GET_IRQ.................................................................................................... 13-1413.3.11 DPSW_SET_IRQ_ENABLE................................................................................... 13-1613.3.12 DPSW_GET_IRQ_ENABLE.................................................................................. 13-1713.3.13 DPSW_SET_IRQ_MASK....................................................................................... 13-1913.3.14 DPSW_GET_IRQ_MASK ...................................................................................... 13-2013.3.15 DPSW_GET_IRQ_STATUS ................................................................................... 13-2213.3.16 DPSW_CLEAR_IRQ_STATUS.............................................................................. 13-2413.3.17 DPSW_GET_ATTRIBUTES................................................................................... 13-2513.3.18 DPSW_SET_REFLECTION_IF ............................................................................. 13-2713.3.19 DPSW_IF_SET_FLOODING ................................................................................. 13-2813.3.20 DPSW_IF_SET_BROADCAST ............................................................................. 13-2913.3.21 DPSW_IF_SET_MULTICAST ............................................................................... 13-3013.3.22 DPSW_IF_SET_TCI ............................................................................................... 13-3113.3.23 DPSW_IF_GET_TCI............................................................................................... 13-3213.3.24 DPSW_IF_SET_STP............................................................................................... 13-34
DPAA2 User Manual, Rev. 2, 05/2016
10 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
13.3.25 DPSW_IF_SET_ACCEPTED_FRAMES ............................................................... 13-3513.3.26 DPSW_SET_IF_ACCEPT_ALL_VLAN................................................................ 13-3613.3.27 DPSW_IF_GET_COUNTER .................................................................................. 13-3713.3.28 DPSW_IF_SET_COUNTER................................................................................... 13-3913.3.29 DPSW_IF_SET_TX_SELECTION......................................................................... 13-4013.3.30 DPSW_IF_ADD_REFLECTION............................................................................ 13-4113.3.31 DPSW_IF_REMOVE_REFLECTION ................................................................... 13-4213.3.32 DPSW_IF_SET_FLOODING_METERING........................................................... 13-4313.3.33 DPSW_IF_SET_METERING................................................................................. 13-4413.3.34 DPSW_IF_SET_EARLY_DROP ............................................................................ 13-4513.3.35 DPSW_ADD_CUSTOM_TPID .............................................................................. 13-4713.3.36 DPSW_REMOVE_CUSTOM_TPID...................................................................... 13-4813.3.37 DPSW_IF_ENABLE............................................................................................... 13-4913.3.38 DPSW_IF_DISABLE.............................................................................................. 13-5013.3.39 DPSW_IF_GET_ATTRIBUTES............................................................................. 13-5113.3.40 DPSW_IF_SET_MAX_FRAME_LENGTH........................................................... 13-5313.3.41 DPSW_IF_SET_LINK_CFG .................................................................................. 13-5413.3.42 DPSW_IF_GET_LINK_STATE.............................................................................. 13-5513.3.43 DPSW_IF_GET_MAX_FRAME_LENGTH .......................................................... 13-5713.3.44 DPSW_VLAN_ADD............................................................................................... 13-5913.3.45 DPSW_VLAN_ADD_IF ......................................................................................... 13-6013.3.46 DPSW_VLAN_ADD_IF_UNTAGGED ................................................................. 13-6113.3.47 DPSW_VLAN_ADD_IF_FLOODING................................................................... 13-6213.3.48 DPSW_VLAN_REMOVE_IF................................................................................. 13-6313.3.49 DPSW_VLAN_REMOVE_IF_UNTAGGED......................................................... 13-6413.3.50 DPSW_VLAN_REMOVE_IF_FLOODING .......................................................... 13-6513.3.51 DPSW_VLAN_REMOVE ...................................................................................... 13-6613.3.52 DPSW_VLAN_GET_ATTRIBUTES ..................................................................... 13-6713.3.53 DPSW_VLAN_GET_IF.......................................................................................... 13-6913.3.54 DPSW_VLAN_GET_IF_FLOODING ................................................................... 13-7113.3.55 DPSW_VLAN_GET_IF_UNTAGGED.................................................................. 13-7313.3.56 DPSW_FDB_ADD.................................................................................................. 13-7513.3.57 DPSW_FDB_REMOVE.......................................................................................... 13-7713.3.58 DPSW_FDB_ADD_UNICAST............................................................................... 13-7813.3.59 DPSW_FDB_GET_UNICAST ............................................................................... 13-7913.3.60 DPSW_FDB_REMOVE_UNICAST ...................................................................... 13-8113.3.61 DPSW_FDB_ADD_MULTICAST ......................................................................... 13-8213.3.62 DPSW_FDB_GET_MULTICAST .......................................................................... 13-8313.3.63 DPSW_FDB_REMOVE_MULTICAST ................................................................. 13-8513.3.64 DPSW_FDB_SET_LEARNING_MODE ............................................................... 13-8613.3.65 DPSW_FDB_GET_ATTRIBUTES......................................................................... 13-87
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11
ContentsParagraphNumber Title
PageNumber
13.3.66 DPSW_ACL_ADD.................................................................................................. 13-8913.3.67 DPSW_ACL_REMOVE ......................................................................................... 13-9113.3.68 DPSW_ACL_PREPARE_ENTRY_CFG ................................................................ 13-9213.3.69 DPSW_ACL_ADD_ENTRY................................................................................... 13-9413.3.70 DPSW_ACL_REMOVE_ENTRY .......................................................................... 13-9513.3.71 DPSW_ACL_ADD_IF ............................................................................................ 13-9813.3.72 DPSW_ACL_REMOVE_IF.................................................................................... 13-9913.3.73 DPSW_ACL_GET_ATTRIBUTES....................................................................... 13-10013.3.74 DPSW_CTRL_IF_GET_ATTRIBUTES............................................................... 13-10213.3.75 DPSW_CTRL_IF_SET_POOLS........................................................................... 13-10413.3.76 DPSW_CTRL_IF_ENABLE................................................................................. 13-10513.3.77 DPSW_CTRL_IF_DISABLE................................................................................ 13-106
Chapter 14 DPMAC: Data Path MAC
14.1 DPMAC features............................................................................................................ 14-114.2 DPMAC command reference......................................................................................... 14-214.2.1 DPMAC_OPEN......................................................................................................... 14-214.2.2 DPMAC_CLOSE....................................................................................................... 14-314.2.3 DPMAC_CREATE .................................................................................................... 14-414.2.4 DPMAC_DESTROY................................................................................................. 14-514.2.5 DPMAC_SET_IRQ ................................................................................................... 14-614.2.6 DPMAC_GET_IRQ................................................................................................... 14-714.2.7 DPMAC_SET_IRQ_ENABLE ................................................................................. 14-914.2.8 DPMAC_GET_IRQ_ENABLE............................................................................... 14-1014.2.9 DPMAC_SET_IRQ_MASK.................................................................................... 14-1214.2.10 DPMAC_GET_IRQ_MASK................................................................................... 14-1314.2.11 DPMAC_GET_IRQ_STATUS ................................................................................ 14-1514.2.12 DPMAC_CLEAR_IRQ_STATUS........................................................................... 14-1714.2.13 DPMAC_GET_ATTRIBUTES ............................................................................... 14-1814.2.14 DPMAC_MDIO_READ.......................................................................................... 14-2014.2.15 DPMAC_MDIO_WRITE........................................................................................ 14-2214.2.16 DPMAC_GET_LINK_CFG .................................................................................... 14-2314.2.17 DPMAC_SET_LINK_STATE................................................................................. 14-2514.2.18 DPMAC_GET_COUNTER..................................................................................... 14-26
Chapter 15 DPRTC: Data Path Real Time Clock
15.1 DPRTC features ............................................................................................................. 15-115.2 DPRTC command reference .......................................................................................... 15-115.2.1 DPRTC_OPEN .......................................................................................................... 15-1
DPAA2 User Manual, Rev. 2, 05/2016
12 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
15.2.2 DPRTC_CLOSE ........................................................................................................ 15-215.2.3 DPRTC_CREATE...................................................................................................... 15-315.2.4 DPRTC_DESTROY .................................................................................................. 15-515.2.5 DPRTC_SET_IRQ..................................................................................................... 15-615.2.6 DPRTC_GET_IRQ .................................................................................................... 15-715.2.7 DPRTC_SET_IRQ_ENABLE................................................................................... 15-915.2.8 DPRTC_GET_IRQ_ENABLE ................................................................................ 15-1015.2.9 DPRTC_SET_IRQ_MASK ..................................................................................... 15-1215.2.10 DPRTC_GET_IRQ_MASK..................................................................................... 15-1315.2.11 DPRTC_GET_IRQ_STATUS.................................................................................. 15-1515.2.12 DPRTC_CLEAR_IRQ_STATUS ............................................................................ 15-1715.2.13 DPRTC_GET_ATTRIBUTES ................................................................................. 15-1815.2.14 DPRTC_SET_CLOCK_OFFSET............................................................................ 15-2015.2.15 DPRTC_SET_FREQ_COMPENSATION............................................................... 15-2115.2.16 DPRTC_GET_FREQ_COMPENSATION.............................................................. 15-2215.2.17 DPRTC_GET_TIME ............................................................................................... 15-2415.2.18 DPRTC_SET_TIME................................................................................................ 15-2615.2.19 DPRTC_SET_ALARM ........................................................................................... 15-27
Chapter 16 DPSECI: Data Path SEC Interface
16.1 DPSECI features ............................................................................................................ 16-116.2 DPSECI functional description...................................................................................... 16-116.2.1 Setting DPSECI for SEC operation ........................................................................... 16-116.2.2 Relationship with DPIO and DPCON objects ........................................................... 16-216.2.3 Buffer requirements ................................................................................................... 16-216.3 DPSECI command reference ......................................................................................... 16-316.3.1 DPSECI_OPEN ......................................................................................................... 16-316.3.2 DPSECI_CLOSE....................................................................................................... 16-416.3.3 DPSECI_CREATE..................................................................................................... 16-516.3.4 DPSECI_DESTROY ................................................................................................. 16-616.3.5 DPSECI_ENABLE.................................................................................................... 16-716.3.6 DPSECI_DISABLE................................................................................................... 16-816.3.7 DPSECI_IS_ENABLED ........................................................................................... 16-916.3.8 DPSECI_RESET ..................................................................................................... 16-1116.3.9 DPSECI_SET_IRQ.................................................................................................. 16-1216.3.10 DPSECI_GET_IRQ................................................................................................. 16-1316.3.11 DPSECI_SET_IRQ_ENABLE................................................................................ 16-1516.3.12 DPSECI_GET_IRQ_ENABLE ............................................................................... 16-1616.3.13 DPSECI_SET_IRQ_MASK .................................................................................... 16-1816.3.14 DPSECI_GET_IRQ_MASK ................................................................................... 16-19
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13
ContentsParagraphNumber Title
PageNumber
16.3.15 DPSECI_GET_IRQ_STATUS................................................................................. 16-2116.3.16 DPSECI_CLEAR_IRQ_STATUS ........................................................................... 16-2316.3.17 DPSECI_GET_ATTRIBUTES................................................................................ 16-2416.3.18 DPSECI_SET_RX_QUEUE ................................................................................... 16-2616.3.19 DPSECI_GET_RX_QUEUE................................................................................... 16-2716.3.20 DPSECI_GET_TX_QUEUE................................................................................... 16-2916.3.21 DPSECI_GET_SEC_ATTR..................................................................................... 16-3116.3.22 DPSECI_GET_SEC_COUNTERS ......................................................................... 16-33
Chapter 17 DPDCEI: Data Path DCE Interface
17.1 DPDCEI features ........................................................................................................... 17-117.2 DPDCEI command reference ........................................................................................ 17-117.2.1 DPDCEI_OPEN......................................................................................................... 17-217.2.2 DPDCEI_CLOSE ...................................................................................................... 17-317.2.3 DPDCEI_CREATE.................................................................................................... 17-417.2.4 DPDCEI_DESTROY................................................................................................. 17-517.2.5 DPDCEI_ENABLE ................................................................................................... 17-617.2.6 DPDCEI_DISABLE .................................................................................................. 17-717.2.7 DPDCEI_IS_ENABLED........................................................................................... 17-817.2.8 DPDCEI_RESET..................................................................................................... 17-1017.2.9 DPDCEI_SET_IRQ................................................................................................. 17-1117.2.10 DPDCEI_GET_IRQ ................................................................................................ 17-1217.2.11 DPDCEI_SET_IRQ_ENABLE ............................................................................... 17-1417.2.12 DPDCEI_GET_IRQ_ENABLE............................................................................... 17-1517.2.13 DPDCEI_SET_IRQ_MASK ................................................................................... 17-1717.2.14 DPDCEI_GET_IRQ_MASK................................................................................... 17-1817.2.15 DPDCEI_GET_IRQ_STATUS................................................................................ 17-2017.2.16 DPDCEI_CLEAR_IRQ_STATUS........................................................................... 17-2217.2.17 DPDCEI_GET_ATTRIBUTES ............................................................................... 17-2317.2.18 DPDCEI_SET_RX_QUEUE................................................................................... 17-2517.2.19 DPDCEI_GET_RX_QUEUE .................................................................................. 17-2617.2.20 DPDCEI_GET_TX_QUEUE .................................................................................. 17-28
Chapter 18 DPDMAI: Data Path DMA Interface
18.1 DPDMAI features .......................................................................................................... 18-118.2 DPDMAI command reference ....................................................................................... 18-218.2.1 DPDMAI_OPEN ....................................................................................................... 18-218.2.2 DPDMAI_CLOSE..................................................................................................... 18-318.2.3 DPDMAI_CREATE................................................................................................... 18-4
DPAA2 User Manual, Rev. 2, 05/2016
14 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
18.2.4 DPDMAI_DESTROY ............................................................................................... 18-518.2.5 DPDMAI_ENABLE.................................................................................................. 18-618.2.6 DPDMAI_DISABLE................................................................................................. 18-718.2.7 DPDMAI_IS_ENABLED ......................................................................................... 18-818.2.8 DPDMAI_RESET ................................................................................................... 18-1018.2.9 DPDMAI_SET_IRQ................................................................................................ 18-1118.2.10 DPDMAI_GET_IRQ............................................................................................... 18-1218.2.11 DPDMAI_SET_IRQ_ENABLE.............................................................................. 18-1418.2.12 DPDMAI_GET_IRQ_ENABLE ............................................................................. 18-1518.2.13 DPDMAI_SET_IRQ_MASK .................................................................................. 18-1718.2.14 DPDMAI_GET_IRQ_MASK ................................................................................. 18-1818.2.15 DPDMAI_GET_IRQ_STATUS............................................................................... 18-2018.2.16 DPDMAI_CLEAR_IRQ_STATUS ......................................................................... 18-2218.2.17 DPDMAI_GET_ATTRIBUTES.............................................................................. 18-2318.2.18 DPDMAI_SET_RX_QUEUE ................................................................................. 18-2518.2.19 DPDMAI_GET_RX_QUEUE................................................................................. 18-2618.2.20 DPDMAI_GET_TX_QUEUE................................................................................. 18-28
Chapter 19 DPAIOP: Data Path AIOP Control
19.1 DPAIOP features............................................................................................................ 19-119.2 DPAIOP command reference......................................................................................... 19-219.2.1 DPAIOP_OPEN......................................................................................................... 19-219.2.2 DPAIOP_CLOSE....................................................................................................... 19-319.2.3 DPAIOP_CREATE .................................................................................................... 19-419.2.4 DPAIOP_DESTROY................................................................................................. 19-519.2.5 DPAIOP_RESET ....................................................................................................... 19-619.2.6 DPAIOP_SET_IRQ ................................................................................................... 19-719.2.7 DPAIOP_GET_IRQ................................................................................................... 19-819.2.8 DPAIOP_SET_IRQ_ENABLE................................................................................ 19-1019.2.9 DPAIOP_GET_IRQ_ENABLE............................................................................... 19-1119.2.10 DPAIOP_SET_IRQ_MASK.................................................................................... 19-1319.2.11 DPAIOP_GET_IRQ_MASK ................................................................................... 19-1419.2.12 DPAIOP_GET_IRQ_STATUS ................................................................................ 19-1619.2.13 DPAIOP_CLEAR_IRQ_STATUS ........................................................................... 19-1819.2.14 DPAIOP_GET_ATTRIBUTES................................................................................ 19-1919.2.15 DPAIOP_LOAD ...................................................................................................... 19-2119.2.16 DPAIOP_RUN......................................................................................................... 19-2219.2.17 DPAIOP_GET_SL_VERSION................................................................................ 19-2319.2.18 DPAIOP_GET_STATE............................................................................................ 19-2519.2.19 DPAIOP_SET_TIME_OF_DAY ............................................................................. 19-27
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15
ContentsParagraphNumber Title
PageNumber
19.2.20 DPAIOP_GET_TIME_OF_DAY ............................................................................ 19-28
Chapter 20 DPMCP: Data Path MC Portal
20.1 DPMCP features ............................................................................................................ 20-120.2 DPMCP command reference ......................................................................................... 20-220.2.1 DPMCP_OPEN ......................................................................................................... 20-220.2.2 DPMCP_CLOSE ....................................................................................................... 20-320.2.3 DPMCP_CREATE..................................................................................................... 20-320.2.4 DPMCP_DESTROY ................................................................................................. 20-520.2.5 DPMCP_RESET........................................................................................................ 20-620.2.6 DPMCP_SET_IRQ.................................................................................................... 20-720.2.7 DPMCP_GET_IRQ ................................................................................................... 20-820.2.8 DPMCP_SET_IRQ_ENABLE ................................................................................ 20-1020.2.9 DPMCP_GET_IRQ_ENABLE ............................................................................... 20-1120.2.10 DPMCP_SET_IRQ_MASK .................................................................................... 20-1320.2.11 DPMCP_GET_IRQ_MASK.................................................................................... 20-1320.2.12 DPMCP_GET_IRQ_STATUS................................................................................. 20-1620.2.13 DPMCP_GET_ATTRIBUTES ................................................................................ 20-18
Chapter 21 Memory Map and Register Definition
21.1 General Control Register 1 (GCR1) .............................................................................. 21-121.2 General Status Register (GSR) ...................................................................................... 21-321.3 MC Firmware Base Address Low Register (MCFBALR) ............................................ 21-421.4 MC Firmware Base Address High Register (MCFBAHR) ........................................... 21-421.5 MC Firmware Attributes and Partitioning Register (MCFAPR) ................................... 21-521.6 Parameter Summary Register (PSR).............................................................................. 21-621.7 Block Revision Register 1 (BRR1)................................................................................ 21-621.8 Block Revision Register 2 (BRR2)................................................................................ 21-7
Chapter 22 Data Path Layout (DPL) Reference
22.1 High-level DPL structure............................................................................................... 22-122.2 Node: containers ............................................................................................................ 22-122.2.1 Child node: dprc......................................................................................................... 22-222.2.1.1 Child node: resources ............................................................................................ 22-322.2.1.1.1 Child node: res................................................................................................... 22-322.2.1.2 Child node: objects ................................................................................................ 22-522.2.1.2.1 Child node: obj .................................................................................................. 22-522.2.1.2.2 Child Node: obj_set ........................................................................................... 22-5
DPAA2 User Manual, Rev. 2, 05/2016
16 NXP Semiconductors
ContentsParagraphNumber Title
PageNumber
22.3 Node: objects ................................................................................................................. 22-622.3.1 Child node: dpni......................................................................................................... 22-622.3.2 Child node: dpio......................................................................................................... 22-922.3.3 Child node: dpbp...................................................................................................... 22-1022.3.4 Child node: dpcon.................................................................................................... 22-1022.3.5 Child node: dpci....................................................................................................... 22-1022.3.6 Child node: dpseci ................................................................................................... 22-1122.3.7 Child node: dpdmux................................................................................................. 22-1122.3.8 Child node: dpsw ..................................................................................................... 22-1322.3.9 Child node: dpmac ................................................................................................... 22-1322.3.10 Child node: dpdcei ................................................................................................... 22-1422.3.11 Child node: dpdmai.................................................................................................. 22-1422.3.12 Child node: dpmcp................................................................................................... 22-1522.3.13 Child node: dpaiop................................................................................................... 22-1522.4 Node: connections........................................................................................................ 22-1522.4.1 Child node: connection ............................................................................................ 22-15
Chapter 23 Data Path Configuration (DPC) Reference
23.1 High-level DPC structure............................................................................................... 23-123.2 Node: mc_general .......................................................................................................... 23-223.2.1 Child node: log........................................................................................................... 23-223.3 Node: resources.............................................................................................................. 23-323.3.1 Child node: icid_pools ............................................................................................... 23-323.3.1.1 Child node: icid_pool ............................................................................................ 23-323.4 Node: controllers............................................................................................................ 23-423.4.1 Child node: qbman..................................................................................................... 23-423.5 Node: board_info ........................................................................................................... 23-523.5.1 Child node: ports........................................................................................................ 23-523.5.1.1 Child node: mac..................................................................................................... 23-5
Introduction
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 1-1
Chapter 1 IntroductionDPAA2 is a hardware-level networking architecture found on some NXP SoCs. The document provides technical information on this architecture mainly for software developers. DPAA2 SoCs contain the following hardware IP blocks:
• Management Complex (required)
• WRIOP (required)
• QBMan (required)
• Accelerators, such as SEC, DCE, and PME (all optional)
• AIOP, a programmable packet engine (optional)
The following block diagram shows the hardware IP blocks of the DPAA2:
Figure 1-1. DPAA2 Hardware Blocks
The Management Complex (MC) is a key component of DPAA2. As is explained in detail in this document, the MC runs a NXP-supplied firmware image that abstracts and simplifies the allocation and configuration of the other hardware elements by means of DPAA2 “objects”. These objects provide familiar services such as providing the core of network interfaces, providing switching services, providing access to accelerators, etc.
The MC subjects within the scope of the document are:
• Definition of the DPAA2 objects: what they do, their configuration interfaces, and how the objects work with each other.
Introduction
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 1-2
• Error reporting and handling for the objects.
• How to load and start the MC at the hardware level (needed to load the firmware) as well as how to allocate memory for it, ICIDs, etc.
• The hardware programming model of the MC's command portals. They are used to convey commands to work with objects.
• Interrupts and error indications from the MC itself (as opposed to objects)
The MC and objects abstract configuration. They do not abstract the actual I/O operations. These are done using QBMan software portals (allocated and configured by means of DPIO objects). However, software must directly use software portals for actual I/O.
Status Note
For now, readers must consult the full QBMan documentation in the low-level hardware reference manual. This documentation contains more information than is needed for software development on general purpose cores and AIOP. Eventually, the subset of the QBMan hardware-level information that is needed will be available in this document. In addition, coverage of MC commands and objects usage will be enhanced.
1.1 Intended audienceThe purpose of this document is to describe the DPAA2 Management Complex services and describe the best usage practices. This document contains an overview of the functions, interfaces, and recommended use of the Management Complex to enable the DPAA2 hardware capabilities; including the programming models for the various DPAA2 objects.
1.2 Definitions and acronyms• AIOP: Advanced I/O Processor hardware
• DCE: Decompression and Compression Engine
• DPAA2: Data Path Acceleration Architecture, second version.
• DPC: Data Path Configuration
• DPL: Data Path Layout
• GPP: General Purpose Processor
• MC: Management Complex
• QBMan: Queue Manager and Buffer Manager hardware
• SEC: Security Engine hardware
• WRIOP: Wire-Rate I/O Processor
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-1
Chapter 2 OverviewThe Management Complex (MC) is an SoC hardware block that simplifies DPAA2 device management - network objects (network interfaces, L2 switches), accelerators, etc. The MC provides object abstractions and a command interface that simplify software’s use of DPAA2 objects; it also provides resource management capabilities that can create and assign these objects to different software contexts (applications, virtual machines). This action allows the direct access by the software contexts to hardware resources, while at the same time providing isolation for the objects from other contexts; this ensures that malicious software can not impact the objects.
GPP and AIOP processes do not have direct access to most DPAA2 resources, and instead they perform the necessary DPAA2 management operations using MC commands that carry out the actual hardware interaction on behalf of that process.
2.1 Introduction to DPAA2 objectsThe primary purpose of the MC provided DPAA2 objects is to simplify DPAA2 hardware block usage through abstraction and encapsulation. DPAA2 objects are objects in that they:
• Encapsulate specific functionality
• Abstract that functionality from the DPAA2 hardware
• Present functionality in terms of well-defined attributes and methods
The MC exports a set of logical objects to enable DPAA2, as explained in the following sections. The objects can be created dynamically through dedicated API calls, or statically during initialization using the Data Path Layout (DPL) configuration file.
This section:
• Presents the DPAA2 object model at a concept level and describes how objects are created, destroyed, conveyed, configured, and used.
• Lists the objects types and their purposes.
The “users” are often application software running on general purpose processors (cores) or on the AIOP. Driver-level software on GPPs (and sometimes AIOP) work with the abstracted objects, rather than directly with the hardware. For example, the GPP software deals with L2 switches and network interfaces rather than directly with WRIOP.
DPAA2 objects express and abstract the DPAA2 hardware into software-managed objects that are:
• Application-oriented in terminology and use, rather than hardware-oriented.
• Based on concepts that are generally familiar to programmers and system architects.
• Simpler than direct management of the hardware.
• Indicate the architectural intent of the hardware blocks.
The DPAA2 object services are provided by software that runs as firmware on a DPAA2 hardware block called the Management Complex. Users do not need to program the Management Complex in order to use the Network Object Services; they simply use the NXP-supplied firmware. This firmware runs on the Management Complex instead of a general purpose core in order to simplify the integration of NXP
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-2
software with customer software. The Management Complex provides objects that perform specific services; the objects have attributes and interfaces that appear as hardware.
2.1.1 Network objects
The primary goal of DPAA2 is advanced networking, and MC exports several objects that allow users to define their topology for “network on a chip”. The network topology may contain network interfaces with varying capabilities as well as several types of switches and aggregators, linked together in a straight-forward manner, defined by the user.
2.1.1.1 Data Path Network Interface (DPNI)
The MC exports a standard network interface that is configurable to support a wide range of features, starting from as low as a basic Ethernet interface up to a high-functioning network interface. The DPNI supports standard features such as filtering, QoS, checksum validation, and time-stamping; It can also offload tasks from the GPP by performing functions such as VLAN header removal/insertion, IP Reassembly, and IP Fragmentation.
On ingress, the DPNI receives frames from a DPMAC or another object such as a DPSW, parses headers, determines the frame’s traffic class, and enqueues the frame onto a frame queue selected based on the traffic class and other header values. This supports both hash-based distribution of frames to multiple cores, and also direct flow steering of frames to specific cores. The DPNI can generate a per-queue data availability notification when a frame is enqueued.
On egress, the DPNI dequeues frames from frame queues and transmits them using a DPMAC, or to another DPAA2 object such as a DPSW.
Normally, the DPNI assumes that traffic consists of standard network packets (L2, L3, L4, etc.); however, it is also possible to configure the DPNI as a generic network interface, and the traffic profile will be based on packet format starting at higher layers. Example formats for this profile can include L5+L6+Payload (as in GTP or CAPWAP applications). In this mode, the DPNI is not intended to interact with a standard network stack, but instead it can be used in fast-path or tunnel applications, therefore suitable for network connections between GPP applications and AIOP applications.
2.1.1.2 Data Path MAC (DPMAC)
The DPMAC represents an Ethernet MAC, a hardware device that connects to a PHY and allows physical transmission and reception of Ethernet frames; since DPAA2 allows configuration of internal interfaces, the total number of network interfaces may exceed the number of MAC objects. The DPMAC object also exposes MDIO access that is used for configuration of external PHY devices.
2.1.1.3 Data Path Switch (DPSW)
The DPSW object provides the functionality of a general layer 2 switch. It receives packets on one port and sends them on another. It can also send packets out on multiple ports for the purposes of broadcast, multicast, or mirroring.
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-3
2.1.1.4 Data Path Demux (DPDMUX)
The DPDMUX is another type of switch. It differs from a DPSW in several ways. A DPDMUX has a single “uplink” port. Also, it can be programmed to direct packets based on header fields beyond layer 2.
2.1.1.5 Data Path Link Aggregator (DPLAG)
The DPLAG object provides link aggregation. It combines two or more physical (slave) interfaces into a single host-side (bonded) interface with aggregated bandwidth.
NOTE:DPLAG object is not supported in LS2085A revision 1.0.
The figure below summarizes the DPAA2 network objects and their associated symbols for illustrations.
Figure 1. DPAA2 Network objects summary and symbols
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-4
2.1.2 DPAA2 infrastructure objects
The MC exports a set of supporting objects that provide access to the DPAA2 QBMan in a way that is both easy to configure, and flexible enough to allow optimal utilization and sharing of resources within software contexts.
2.1.2.1 Data Path Buffer Pool (DPBP)
The DPBP represents a QBMan buffer pool. It is used mainly as a resource by DPAA2 network interfaces and accelerators, but it is also an active entity because it can send buffer pool depletion notifications to GPP core software. DPBP owners are responsible for seeding it with buffers
2.1.2.2 Data Path I/O Portal (DPIO)
The DPIO object allows QBMan software portal configuration with an optional notification channel; its main purpose is to enable the GPP to perform I/O through QBMan – hardware queuing operations, such as enqueue and dequeue, and hardware buffer management operations, such as acquire and release. It also allows data availability notifications and buffer pool depletion notifications to be received. Each DPIO object will be usually affined to a GPP core thread.
2.1.2.3 Data Path Concentrator (DPCON)
The DPCON object allows ingress packets from multiple interfaces to be aggregated into a single device that appears to a GPP core as single interface. The DPCON utilizes scheduling options of the QBMan channels to provide hardware-based scheduling offload of ingress packets, including scheduling between different network interfaces.
The DPCON is also useful for software that polls for input frames; it allows a single interface to be polled instead of multiple interfaces.
The figure below summarizes the DPAA2 infrastructure objects and their associated symbols for illustrations.
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-5
Figure 2. DPAA2 Infrastructure objects summary and symbols
2.1.3 Accelerator interfaces
DPAA2 features several hardware accelerators to assist GPP in data processing tasks. The MC exports accelerator interface objects that enable GPP software to send requests to these accelerators and receive their data processing output.
2.1.3.1 Data Path Security Interface (DPSECI)
The Security engine (SEC) contains high-performance hardware for cryptographic acceleration and offloading, designed to operate in a data path environment. It implements:
• Block encryption algorithms
• Stream cipher algorithms
• Hashing algorithms
• Public key algorithms
• Run time integrity checking
• Random number generator
The DPSECI object provides GPP software with an interface for sending requests to SEC and receiving output responses.
2.1.3.2 Data Path De/Compression Interface (DPDCEI)
The Decompression and Compression Engine (DCE) contains high-performance hardware for decompression and compression functionality, designed to operate in a data path environment. Its functionality includes the following:
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-6
• Offloading and acceleration of DEFLATE decompression and compression as defined in RFC1951
• Offloading and acceleration of GZIP decompression and compression as defined in RFC1952
• Offloading and acceleration of ZLIB decompression and compression as defined in RFC1950
The DPDCEI object provides GPP software with an interface for sending requests to the DCE and receiving output responses.
2.1.3.3 Data Path DMA Interface (DPDMAI)
The qDMA controller contains high-performance hardware for data transfer functionality, designed to operate in a data path environment. The controller can transfer blocks of data between one source and one or more destinations. The blocks of data transferred can be represented in memory as contiguous or non-contiguous using scatter/gather tables.
The DPDMAI object provides GPP software with an interface for sending requests to the qDMA and receiving completion responses.
The figure below summarizes the DPAA2 accelerator interface objects and their associated symbols for illustrations.
Figure 3. DPAA2 Accelerator Interface objects summary and symbols
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-7
2.1.4 Management and control objects
2.1.4.1 Data Path Communication Interface (DPCI)
The MC exports a generic interface for inter-partition communication (IPC). The DPCI enables frame-based communication between different software contexts, utilizing the QBMan infrastructure of DPAA2. The communication protocol is kept undefined and the interface does not provide any parsing or classification of the frames (unlike DPNI, which is a fully-featured standard network interface).
DPCI objects should be connected in pairs (one DPCI in each software context) to form a communication link. This type of communication may serve basic management/control needs between GPP software and AIOP software, or between two GPP software contexts.
2.1.4.2 Data Path Resource Container (DPRC)
The DPRC object allows the management complex to track sets of objects in use by the same software component. The objects in the set are said to be in same container. The DPRC operates as a virtual bus, and a software context may query it for DPAA2 objects and associate them with OS device drivers. The DPRC also allows a software context to create descendant software contexts, assign resources and objects to these contexts, and build the internal network topology by connecting DPAA2 network objects.
Some objects include DMA-capable hardware. All objects in the same DPRC share a common ICID, and a common set of IO-MMU mappings. A number of key features of DPRCs include:
• Direct access – All the objects and resources in a container are private to the container, and software components get direct access to the “registers” (as abstracted by the management complex) of the hardware objects.
• Dynamic discovery – A software context that is given a DPRC can dynamically discover the objects and resources placed in the container using MC commands.
• Hot plug/unplug – Objects can be dynamically plugged and unplugged into DPRCs
• Security – A software context can only see the objects its DPRC, and cannot affect other containers or the proper operation of other software contexts. DMA transactions from MC objects are isolated using the system IOMMU.
2.1.4.3 Data Path MC Portal (DPMCP)
The DPMCP object is associated with Management Complex Portals, and allows GPP software to configure command completion interrupts for these portals. The DPMCP object is optional if the GPP software is polling the portal and not using portal interrupts. However, for consistency and for better tracking of MC portals that are in use, it is recommended to always create DPMCP objects for MC portals used by GPP.
The figure below summarizes the DPAA2 management objects and their associated symbols for illustrations.
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-8
Figure 4. DPAA2 Management objects summary and symbols
2.2 Objects topology and inter-connectDPAA2 network objects can be connected to each other, creating a ‘network on a chip’ topology; connections are virtual network cables between two endpoints, where an endpoint may be a network interface (DPNI), a DPMAC (external port), a DPSW interface, a DPDMUX interface, etc. As in real network, an endpoint is not necessarily aware of the peer endpoint’s type or identity, but it can query its link state and receive notifications on link up/down events.
The figure below demonstrates a simple network topology. The network topology is shown in the greyed box with dotted outline. The rest of the elements in the figure are shown for better understanding of the system context.
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-9
Figure 5. Object topology example
The system in the example above involves only two external ports (DPMAC objects), but contains three network interfaces (DPNI objects) that are completely independent of each other.
One DPNI is connected directly to a DPMAC object, in a way similar to traditional Ethernet controller. This network interface can only communicate outside of the SoC.
The other two DPNI objects, as well as the second DPMAC object, are connected to DPSW interfaces. This allows both network interfaces to communicate outside of the SoC using the DPMAC, and also to communicate with each other.
Note, that the DPNI objects in the example are also associated with DPIO objects, enabling GPP software to get notifications on data availability and perform I/O operations on these network interfaces. This type
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-10
of relation is not considered a connection with regards to the description in this section. The association of DPIO objects to DPNI objects and other objects is explained in more detail later in this document.
The dashed configuration lines show what software component owns the configuration and management of each object. Two network interfaces are owned by instances of the Linux Kernel Ethernet driver and interact with the Linux network stack. One network interface is assigned to a user space process, and is controlled by a user space Ethernet driver. The switch is managed independently of the network interfaces that connect to it.
2.2.1 Connection and link state
The terminology of a Link is slightly different from a Connection. Connections between network objects are a necessary condition to achieve a network link between the objects, but they are not a satisfying condition. For the link to be up, both connected objects must be in enabled state. The software component that owns each of the objects can enable or disable the object at any time – this is done by submitting the corresponding commands to the MC. If either of the connected objects is disabled, the link state is considered down, and packets cannot go through this link. Similarly, if the controlling software decides to disconnect the two objects, the connection will be terminated and both objects will encounter a link down event, even if both are still enabled.
The MC is responsible for propagating link state to objects. Considering the previous example, if the DPMAC connected to the DPSW loses its external link, the peer DPSW interface gets a link down notification; however, the two network interfaces connected to the DPSW are not affected – their link state remains up and they can continue to communicate with each other through the switch.
2.2.2 Typical object connections
A DPNI object must be connected to another network object in order to have packets flowing through it. As explained in the previous section, the connection alone is not sufficient. For the purpose of explaining the allowed network connections, this section assumes that all objects are enabled and only discusses the validity of connecting different types of objects.
The figure below shows typical connection options.
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-11
Figure 6. Typical connections of network objects
Configuration (a) shows a traditional Ethernet controller, where the DPNI is directly connected to the DPMAC object. All DPMAC objects in this figure are assumed to be connected to external network (not explicitly shown).
Configuration (b) shows two DPNI objects connected in a point-to-point manner, allowing network communication between two software contexts. This type of connection is typical in GPP-to-AIOP communication, or between two different GPP processes.
Configuration (c) shows a DPSW object connected to two DPMAC objects and two DPNI objects. All DPSW interfaces are identical, so there is no significance to interface selection when connecting any of the objects to a switch.
Configuration (d) shows a DPDMUX object that can split ingress traffic from a single DPMAC to multiple network interfaces. While the DPDMUX single uplink interface is usually connected to a DPMAC, its multiple internal interfaces are basically identical and are usually connected to internal DPNI objects.
Overview
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 2-12
Configuration (e) shows two layers of DPDMUX objects that can split ingress traffic by different criteria; a typical example is an EVB (Edge Virtual Bridging) setup, where the lower DPDMUX functions as S-Component (splits ingress traffic by S-VLAN) and the upper DPDMUX objects serve as Edge Relays (splits the traffic by C-VLAN).
Configuration (f) shows a DPLAG object, aggregating three external slave interfaces into a single bonded interface connected to a DPNI object.
NOTEWhile cascading of multiple DPSW and/or DPDMUX objects is allowed, it does impact the consumption of hardware resources in the device and reduces the total number of DPNI objects that can be supported; it may also degrade the overall performance. Therefore, it is always recommended to set up the minimal required configuration to support a requested use case.
2.2.3 How and when to connect
Endpoints may be connected or disconnected at any phase, including:
• At MC initialization, through declaration of ‘connections’ in the DPL
• At runtime, by invoking connect/disconnect commands that are part of the DPRC object’s API.
GPP software contexts may be given privileges to perform topology changes through its own DPRC object. A software context is only allowed to connect/disconnect endpoints in its own scope (container) or in its descendants’ scope.
Boot and Initialization Process
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 3-1
Chapter 3 Boot and Initialization ProcessMC initialization is a mandatory part of the boot process – the MC performs the configuration of key DPAA2 hardware resources, such as QBMan, Ethernet ports, and others that are needed early in the boot process. For example, a network interface may be needed to retrieve the OS image from the network; therefore the MC initialization must complete before the main OS image is loaded. The SoC POR signal leaves the DPAA2 in a known idle state, with all of the DPAA2 resources uninitialized and ready to be allocated; the MC is kept in the boot hold-off (reset) state.
3.1 Loading the MC firmwareThe MC firmware itself should be retrieved from a location that does not require DPAA2 network interfaces, and can include an on-board memory, or alternatively a network location accessed using an attached network card (PCI-Express network card, for example). MC requires the allocation of an isolated block taken from main system memory for firmware storage and general DPAA use; This memory space must not be accessible by any other device after MC initialization in order to guarantee MC’s isolation and trust. The SoC boot program (for example, U-Boot) must configure the MC’s private memory space base address and size in the MCFBALR and MCFBAHR registers. The size of memory allocated for MC is configurable, but must be allocated in multiples of 256MB.
The boot program must validate the authenticity of the MC firmware before loading the firmware into the MC memory space; the MC firmware is provided in FIT (Flattened Image Tree) image format and includes checksum and version information, so that the boot program can make sure a proper image is loaded into MC memory space.
3.2 Data Path Configuration (DPC)The “Data Path Configuration” (DPC) is based on a text source file (similar to DTS) and compiled with DTC to form a binary structure (blob, similar to DTB). The DPC file is an optional input to MC and contains board-specific and system-specific information that may override the default DPAA hardware configuration. The DPC file should be compiled to a binary blob using standard DTC tool. For some systems, DPC may be optional.
The boot program should place the DPC blob at offset 0x00F00000 from MC memory base (MCFBALR/HR).
3.3 Data Path Layout (DPL)Many systems have little or no need to dynamically create and destroy DPAA2 objects. MC is able to consume a data structure called the “Data Path Layout” (DPL) – that describes a set of objects to be created when the system is initialized.
The DPL is based on a text source file (similar to DTS) and compiled with DTC to form a binary structure (blob, similar to DTB). This binary structure is loaded by the boot program as an optional input to MC. Unlike the Linux Device Tree, the purpose of the DPL is not to describe hardware attributes, but rather to describe the initial topology of logical objects that the MC firmware should create.
Boot and Initialization Process
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 3-2
Nevertheless, and to satisfy the needs of more dynamic systems, MC also supports dynamic setup of objects. Therefore, all contents of the DPL are considered optional – the same topology of software contexts and logical objects can also be created dynamically. A software context may spawn, via its management portal, a child software context, and assign objects to it. As explained in the resource management chapter, root/parent software may dictate a limiting policy on its child software contexts.
The boot program should place the DPL blob at offset 0x00F20000 from MC memory base (MCFBALR/HR).
3.4 Starting MCAfter the firmware is loaded, the SoC boot program deasserts P1_RST_b and Mn_RST_b bits in the General Control Register 1 (GCR1) to release the MC from reset; immediately the MC begins to retrieve and execute the loaded firmware.
When the MC has completed its configuration and the DPAA2 initial configuration, it is ready to service commands from the GPP. MC initialization completion is signaled by the MC to the SoC boot program by writing the MSC status field in the General Status Register (GSR); if the returned status indicates successful initialization, the system boot process can continue normally. If an MC error code is returned, the DPAA2 subsystem cannot be used, and the system boot should be halted to analyze the problem.
The boot program can request MC to postpone the processing of the DPL; this allows the boot program to utilize some MC objects for its own use, regardless of which objects have been defined in the DPL. After the boot program has completed its tasks it must destroy any MC objects that it previously created and signal MC to load the system DPL.
Below is a summary of the expected handshake between the boot program and MC:
1. Boot program allocates system memory for MC, in N multiples of 256MB
2. Boot program sets MCFBALR and MCFBAHR with the physical base address of the memory allocated for MC, and programs MCFBALR[MEMSZ] to indicate the size of the allocated memory.
3. Boot program loads DPC blob at offset 0x00F00000 from MC firmware base.
4. Boot program loads DPL blob at offset 0x00F20000 from MC firmware base (optional).
5. Before kicking MC core, the boot program may set GSR[BC] with a value of 0xDD (indicates a request to delay DPL processing). If this code is not set, DPL is deployed immediately after MC completes its initial boot (steps 7 and 8 below are skipped).
6. Boot program kicks MC by writing to GCR.
7. If GSR[BC] was set to indicate delayed DPL processing, MC sets GSR[MCS] to indicate ready status (0x1) or error status after it completes its initial boot. If no error is reported, the boot program may issue MC commands (through MC portal #0) to create DPAA objects for its own use.
8. After the boot program completes its network activities it must destroy all created objects and clear the GSR – this signals MC to deploy the DPL.
9. Once MC deploys the DPL, it sets GSR[MCS] to ready status (0x1) once again (or reports an error status). The boot program should wait for such status before continuing to boot the main OS.
MC Firmware Versions
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 4-1
Chapter 4 MC Firmware VersionsThe MC firmware uses global versions that use the following rules:
• Major version number – incremented on API compatibility changes (updates to any DPAA2 object or any other MC API).
• Minor version number – incremented on API additions that are backward compatible;The minor version number is reset to 0 when the major version number is incremented.
• Revision number – incremented on internal changes and/or bug fixes that have no impact on API definition. The revision number is reset when either the major version or minor version is incremented.
MC exposes the API to get the compiled firmware version. In addition, the MC API header files contain matching major and minor numbers defined as preprocessor macros that allow the GPP/AIOP software to verify the defined version numbers against the information retrieved from the MC API call; this check can expose version conflicts between the GPP/AIOP software and the actual loaded firmware.
In addition to the global version, each DPAA2 object has its own version information (major and minor numbers). The object version is incremented according to the same rules as described previously for the global version, but the change scope applies only to changes in that specific object.
MC Firmware Versions
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 4-2
4.1 Firmware command referenceThis section contains the detailed programming model of firmware commands.
4.1.1 DPMNG_GET_VERSION
The command format is shown in the figure below.
Command structure
Figure 4-1. DPMNG_GET_VERSION Command Description
The following table describes the command fields.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x831 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 4-1. DPMNG_GET_VERSION Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
MC Firmware Versions
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 4-3
Response structure
Figure 4-2. DPMNG_GET_VERSION Response Description
The following table describes the response fields.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x831 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MAJOR REVISION
63 32 31 0
0x10 — MINOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 4-2. DPMNG_GET_VERSION Response Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 REVISION Internal revision number: incremented on implementation changes and/or bug fixes that have no impact on API
32-63 MAJOR Major version number: incremented on API compatibility changes
0x10 0-31 MINOR Minor version number: incremented on API additions (backward compatible); reset when major version is incremented
MC Firmware Versions
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 4-4
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-1
Chapter 5 Management Command PortalsThis section describes the MC command portals memory structure and their usage.
5.1 Overview of command portalsThe MC interface contains 256 management portals that are contiguously mapped in the SoC address map. Each portal is implemented in its own physical memory 64kB page within the SoC internal address map so that the Hypervisor can properly manage GPP process allocation and access control portals. MC portals must not be shared between different software contexts.
NOTE:The portal page GPP memory management attribute should be set to cache-inhibited.
Commands are submitted by GPP processes (or AIOP tasks) to a portal using non-cacheable store instructions, similar to accessing typical I/O device registers. MC portals can only support one outstanding command at a time, so all commands on the same portal are issued and completed serially. The command portals can also be read by the GPP/AIOP processes. Misaligned word accesses of a portal, split burst transactions, and accesses outside the 64 bytes of the portal are not performed.
The MC maintains an ICID attribute for every portal that is used to identify the isolation context for command execution; a GPP process can only submit a command for the isolation context it is currently executing within. Any memory address specified by the submitter, as input or output, is authenticated and translated by the IOMMU when the data structure is accessed with the ICID assigned to that command portal.
The MC uses a fair policy to determining which command portal is serviced next; the MC implements a simple round-robin arbitration mechanism to select and prepare the next command to be processed. The submitter may assign either a high or low priority for a command; outstanding high priority commands are processed before any outstanding low priority commands.
5.2 Command portal usageThe MC uses a simple flow control mechanism – a portal command must be completed before a subsequent command can be issued to that same portal; therefore, each portal can only have a single outstanding command at any point in time. If a user submits a new command to its portal prior to that portal being marked as available, the new command may be treated by the MC as an error, or simply ignored.
Commands submitted by the GPP/AIOP processors cause the MC to perform specific management services; the available MC commands are documented in the corresponding MC objects sections. The submitter prepares the specific command and its parameters, and afterwards writes the command header that contains the command ID and other attributes; the actual command word field (the least significant 4-byte word at offset 0x0 of the portal address) should be written last. The MC waits for a command word field write that indicates that a new command has been submitted, then starts processing that command.
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-2
NOTE: The portal’s status field is used as the handshake mechanism between the MC and the command submitter. The submitter must set the ready status (0x01) when writing the command header (only after all parameters for the specific command were written); the MC reports command completion with success/error code in the same status field. The MC can also return command response information in the portal’s memory, as documented for each of the commands.
While a write of any word in an already serviced portal will be discarded, reads of any portal word are always allowed; the submitter may poll the status word freely.
The submitting process/task may use polling to query for command completion and final status; it writes the desired command to a command portal, and polls the portal’s status word until it indicates that it is completed and that the portal is made available. Only once the portal is available does a process/task issue a subsequent command to that command portal. Other OS-specific wait mechanisms are also accepted, as long as no other command is written to the portal before the previous command is completed.
5.3 DPAA2 objects control through command portalsDPAA2 object operations require GPP/AIOP software to open an object control session for the object, by submitting either a CREATE or an OPEN MC command; each object has dedicated CREATE and OPEN commands (DPNI_CREATE, DPNI_OPEN, etc.). A CREATE command creates a new DPAA2 object type with the specified attributes used in the command. An OPEN command can be used to open a control session for the newly created object; an object may have been declared in the DPL or created by a parent software context. Both CREATE and OPEN commands generate a unique authentication token, associated with the specific object ID and the specific command portal; this token must be used in all subsequent commands for this specific object. Object control sessions are dismissed by submitting a CLOSE command (corresponding to OPEN) or a DESTROY command (corresponding to CREATE).
A single command portal can be used to control multiple DPAA2 objects, as long as both the command portal and the object are assigned to the same software context, i.e. to the same resource container, and the user makes sure that the commands are submitted to the portal one at a time. GPP/AIOP software should submit separate OPEN/CREATE commands for each object it wishes to control in order for a single command portal to control multiple objects in the same software context.
5.4 Command portals memory mapThe MC command portals are accessible to GPP and AIOP software through the SoC internal address map, and the 64MB MC portal space is presented within the 512MB DPAA2 external address map that also contains other DPAA2 portals. Each MC portal is mapped on a 64kB boundary, and the MC Portal is Little-Endian. The MC Portal Space is laid out as shown in Figure 7.
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-3
Figure 7. MC Portal Map
The address map of a single MC Portal is also summarized in Table 1.
5.5 Management command portal definitionThe format of the management command portal is shown in Figure 8.
Table 1. MC Portal Map
Offset rangeBlockSize
Description
0x0_0000 - 0x0_003F 64B Management Command Portal.See Section 5.5, “Management command portal definition”
0x0_0040 - 0x0_FFFF remainder of 64kB Reserved.
Management Command Portal 1023
Management Command Portal 1Management Command Portal 0
Management Command Portal 2
MC Portals offset: 0x3FF_0000
MC Portals offset: 0x002_0000
MC Portals offset: 0x001_0000MC Portals offset: 0x000_0000
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-4
Figure 8. Management Command Portal
Table 2 describes the Management Command Portal fields.1-5
Offset 0x0 from Management Command Portal base (64kB aligned) Read-Write Access
63 52 51 48 47 38 37 32 31 24 23 16 15 14 8 7 0
CMDID — TOKEN
—
—
INT
R_D
IS
STATUS P
— SRCID
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
127 64
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
191 128
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
255 192
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
319 256
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
383 320
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
447 384
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
511 448
PARAMS
Reset 64’b0000_0000_0000_0000_0000_0000_0000_0000
Table 2. Management Command Portal Field Descriptions
Bits Name Description
0-7 SRCID The SoC architected source ID of the submitter. This is the same 8-bit source ID used throughout the SoC.This field is reserved. It cannot be written by a GPP processor.
8-14 — Reserved. Set to zero for forward compatibility.
15 P Priority. This is the command priority class. Outstanding high priority commands are serviced before low priority commands.1’b0 – low priority1’b1 – high priority
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-5
16-23 STATUS Command ready/status.This field is used as the handshake field between MC and the command submitter. The submitter must set the ready status (0x01) when writing the command header (after the PARAMS area was initialized with the specific command parameters). MC reports command completion with success/error codes in this field, as listed below.
0x00 – Command ended successfully (set by MC on successful command completion)0x01 – Command is ready for processing (must be set by the submitter)0x03 – Authentication error (illegal object-portal-icid combination)0x04 – No privilege (operation not permitted for current user) 0x05 – DMA or I/O error0x06 – Configuration error (invalid/conflicting parameters)0x07 – Command timed out (unexpected long execution time)0x08 – No DPAA2 resources for completing the command0x09 – No memory available for completing the command0x0A – Busy (operation cannot be completed temporarily)0x0B – Unsupported/unknown operation0x0C – Invalid state (may indicate incorrect calling sequence)
24 INTR_DIS Interrupt disable.Set to disable interrupt generation on command completion.Note that command completion interrupts are managed through DPMCP object.
25-37 — Reserved. Set to zero for forward compatibility.
38-47 TOKEN Authentication token – for “CREATE” and “OPEN” commands, set this field to zero.The token is updated by MC after a successful completion of a “CREATE” or “OPEN” command.The generated token is valid for the specific object and specific command portal, until a “DESTROY” or “CLOSE” command is completed.User must keep the generated token and set it in the TOKEN field for every subsequent command for the same object and on the same command portal.
48-51 — Reserved. Set to zero for forward compatibility.
52-63 CMDID Command ID. This is the predefined command code for the submitted command (see command code definition in command specifications).
64-511 PARAMS Command parameters (56 bytes).Each command defines specific set of parameters (see command specifications in this document). Unused bits in this area should be cleared for forward compatibility.Each of the seven 64-bits words is organized in memory in Little-Endian format.
Table 2. Management Command Portal Field Descriptions
Bits Name Description
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-6
5.6 MC General Command Portals command referenceThis section contains the detailed programming model of MC general command portals commands.
5.6.1 DPMNG_GET_CONT_ID
Obtains the container id associated with a given portal.
The command format is shown in the figure below.
Command structure
Figure 5-1. DPMNG_GET_CONT_ID Command Description
The following table describes the command fields.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x830 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 5-1. DPMNG_GET_CONT_ID Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-7
Response structure
Figure 5-2. DPMNG_GET_CONT_ID Response Description
The following table describes the response fields.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x830 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — CONTAINER_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 5-2. DPMNG_GET_CONT_ID Response Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CONTAINER_ID Requested container ID
Management Command Portals
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 5-8
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-1
Chapter 6 DPRC: Data Path Resource ContainerA GPP/AIOP software context (e.g. Kernel, user-space application, virtual machine, AIOP application) can be associated with a single DPRC (Data Path Resource Container) object that holds all the resource and object information that the software context can access or use.
A software context may need to spawn descendant software contexts (e.g. applications, virtual machines) and grant them resources and objects; to support this process, a software context can create ‘child’ containers. The parent software context may assign resources and/or objects to that child container, and it may also set resource management policies and reset and destroy the descendant container.
Each container holds three main components:
a) DPAA2 objects inventory for objects assigned to the container. Objects may be assigned either by the parent software through DPRC commands, or through the DPL during initialization.
b) DPAA2 free resource pool inventory. Resource pools contain primitive resources that are assigned to the container, and are not yet associated with any DPAA2 object.
c) Attributes that specify container properties and policies. Attributes are set by the software context that creates the container (the parent), and cannot be changed by the descendant software context.
Please refer to the API book for complete reference of available functions.
6.1 DPRC featuresThe following list summarizes the DPRC main features and capabilities:
• Supports container queries – provides information on the following:
— DPAA2 objects assigned to the container
— For each object, provides the object’s ID, version, mappable regions, supported IRQs and other attributes
— Free resources assigned to the container
— Descendant (child) containers of this container
— The container’s policies and other attributes
• Supports creating and destroying descendant resource containers
• Supports assigning resources and objects to descendant containers
• Supports unassigning resources and objects from descendant containers
• Supports setting global policies to descendant containers
• Supports setting policies per free resource pool of descendant containers
• Supports connecting and disconnecting of DPAA2 network and communication interfaces – allows users to create their required ‘network-on-chip’ topology
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-2
6.2 DPRC functional description
6.2.1 Resource container creation
During MC initialization, the boot program provides an initial DPL structure to the MC that defines the initial container topology and their assigned DPAA2 objects and resources. Privileged software may also perform dynamic descendant container creation for its supervised software contexts; a new DPRC object is created for each descendant container. By issuing the corresponding commands to its own DPRC object, the parent software context can control assignment of DPAA2 resources, objects, and management policies.
A software context that creates descendant containers should set the following container attributes:
• Isolation Context ID (ICID) for the child container; alternatively, the ICID can be selected by the MC from a pool of ICIDs that was predetermined in the DPL
• Spawning policy – determines if the child container is allowed to create its own child containers
• Allocation policy – determines if the child container is allowed to allocate resources from its parent
• Object creation policy – determines if the child container is allowed to create new DPAA2 objects
• Topology change policy – determines if the child container is allowed to change the DPAA2 objects topology by connecting or disconnecting DPAA2 network objects
6.2.2 Objects assignment
A parent software context may assign DPAA2 objects to its child containers; an assigned object can be declared as ‘plugged’ or ‘unplugged’ during assignment. The owner software context may query its associated DPRC object, see the following section on object discovery for more information, and associate a device driver to the discovered object. A software context may also control the ‘plugged’ state of its own objects by reassigning the object to itself and changing the state.
6.2.3 Objects discovery
The DPRC follows the concept of a probeable bus, that may be very useful during the software context’s boot time; by sending the appropriate commands, GPP software can query the DPRC to probe/discover DPAA2 objects in its domain and associate these objects with device drivers.
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-3
6.3 DPRC command referenceThis section contains the detailed programming model of DPRC commands.
6.3.1 DPRC_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPRC_CREATE_CONTAINER command on the parent DPRC object.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object..
Command structure
The command format is shown in the figure below.
Figure 9. DPRC_OPEN Command Description
The following table describes the command fields.1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x805 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — CONTAINER_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 3. DPRC_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CONTAINER_ID Container ID to open
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-4
6.3.2 DPRC_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 10. DPRC_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-5
6.3.3 DPRC_CREATE_CONTAINER
This command creates and initializes an instance of DPRC according to the specified command parameters. This command is not required for DPRC instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 11. DPRC_CREATE_CONTAINER Command Description
The following table describes the command fields.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x200 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 0
0x08 — ICID OPTIONS
63 32 31 0
0x10 PORTAL_ID —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 LABEL7 LABEL6 LABEL5 LABEL4 LABEL3 LABEL2 LABEL1 LABEL0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 LABEL15 LABEL14 LABEL13 LABEL12 LABEL11 LABEL10 LABEL9 LABEL8
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 4. DPRC_CREATE_CONTAINER Command Field Descriptions1
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-32 OPTIONS Combination of 'DPRC_CFG_OPT_<X>' options:bit 0: DPRC_CFG_OPT_SPAWN_ALLOWED - Spawn Policy Option allowed - Indicates that the new container is allowed to spawn and have its own child containersbit 1: DPRC_CFG_OPT_ALLOC_ALLOWED - General Container allocation policy - Indicates that the new container is allowed to allocate requested resources from its parent container; if not set, the container is only allowed to use resources in its own pools; Note that this is a container's global policy, but the parent container may override it and set specific quota per resource type.bit 2: DPRC_CFG_OPT_OBJ_CREATE_ALLOWED - Object initialization allowed - software context associated with this container is allowed to invoke object initialization operations.bit 3: DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED - Topology change allowed - software context associated with this container is allowed to invoke topology operations, such as attach/detach of network objects.bit 5: DPRC_CFG_OPT_AIOP - AIOP -Indicates that container belongs to aiop.
32-47 ICID Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a freeICID value is allocated by the DPRC
0x10 32-63 PORTAL_ID Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a freeportal ID is allocated by the DPRC
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-6
Response structure
Figure 12. DPRC_CREATE_CONTAINER Response Description
The following table describes the response fields.1-5
6.3.4 DPRC_DESTROY_CONTAINER
0x18 0-63 LABEL[0-7] Object label
0x20 0-63 LABEL[8-15]
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x200 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 32 31 0
0x10 — CHILD_CONTAINER_ID
63 0
0x18 CHILD_PORTAL_PADDR
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 5. DPRC_CREATE_CONTAINER Response Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-31 CHILD_CONTAINER_ID Child container ID
0x18 0-63 CHILD_PORTAL_PADDR Base physical address of the child portal
Table 4. DPRC_CREATE_CONTAINER Command Field Descriptions1 (continued)
Offset Bits Name Description
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-7
Command structure
Figure 13. DPRC_DESTROY_CONTAINER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — CHILD_CONTAINER_ID
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CHILD_CONTAINER_ID ID of the container to destroy
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-8
6.3.5 DPRC_RESET_CONTAINER
Command structure
Figure 14. DPRC_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — CHILD_CONTAINER_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CHILD_CONTAINER_ID ID of the container to reset
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-9
6.3.6 DPRC_SET_IRQ
Set IRQ information for the DPRC to trigger an interrupt.
Command structure
Figure 15. DPRC_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 8 7 0
0x08 IRQ_VAL IRQ_INDEX
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 IRQ_INDEX Identifies the interrupt index to configure
32-63 IRQ_VAL Value to write into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-10
6.3.7 DPRC_GET_IRQ
Get IRQ information from the DPRC.
Command structure
Figure 16. DPRC_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-11
Response structure
Figure 17. DPRC_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-12
6.3.8 DPRC_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 18. DPRC_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-13
6.3.9 DPRC_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 19. DPRC_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-14
Response structure
Figure 20. DPRC_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-15
6.3.10 DPRC_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 21. DPRC_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-16
6.3.11 DPRC_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 22. DPRC_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-17
Response structure
Figure 23. DPRC_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-18
6.3.12 DPRC_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 24. DPRC_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPRC_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-19
Response structure
Figure 25. DPRC_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 0: DPRC_IRQ_EVENT_OBJ_ADDED – indicates that an object was added to the containerBit 1: DPRC_IRQ_EVENT_OBJ_REMOVED – indicates that an object was removed from the containerBit 2: DPRC_IRQ_EVENT_RES_ADDED – indicates that resources were added to the containerBit 3: DPRC_IRQ_EVENT_RES_REMOVED – indicates that resources were removed from the containerBit 4: DPRC_IRQ_EVENT_CONTAINER_DESTROYED – indicates that one of the descendant containers was destroyed Bit 5: DPRC_IRQ_EVENT_OBJ_DESTROYED – indicates that one of the container’s objects was destroyedBit 6: DPRC_IRQ_EVENT_OBJ_CREATED – indicates that an object was created in the container
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-20
6.3.13 DPRC_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 26. DPRC_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-21
6.3.14 DPRC_GET_ATTRIBUTES
Command structure
Figure 27. DPRC_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-22
Response structure
Figure 28. DPRC_GET_ATTRIBUTES Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 0
0x08 — ICID CONTAINER_ID
63 32 31 0
0x10 PORTAL_ID OPTIONS
63 32 31 16 15 0
0x18 — VERSION_MINOR VERSION_MAJOR
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CONTAINER_ID Container's ID
32-47 ICID Container's ICID
0x10 0-31 OPTIONS Container's options as set at container's creation
32-63 PORTAL_ID Container's portal ID
0x18 0-15 VERSION_MAJOR DPRC major version
16-31 VERSION_MINOR DPRC minor version
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-23
6.3.15 DPRC_SET_RES_QUOTA
Command structure
Figure 29. DPRC_SET_RES_QUOTA Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x155 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 0
0x08 — QUOTA CHILD_CONTAINER_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CHILD_CONTAINER_ID ID of the child container
32-47 QUOTA Sets the maximum number of resources of the selected type that the child container is allowed to allocate from its parent;when quota is set to -1, the policy is the same as container's general policy.
0x10 0-63 TYPE[0-5] Resource/object type
0x18 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-24
6.3.16 DPRC_GET_RES_QUOTA
Command structure
Figure 30. DPRC_GET_RES_QUOTA Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x156 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — CHILD_CONTAINER_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CHILD_CONTAINER_ID ID of the child container
0x10 0-63 TYPE[0-5] Resource/object type
0x18 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-25
Response structure
Figure 31. DPRC_GET_RES_QUOTA Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x156 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 0
0x08 — QUOTA —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-47 QUOTA Sets the maximum number of resources of the selected type that the child container is allowed to allocate from its parent;when quota is set to -1, the policy is the same as container's general policy.
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-26
6.3.17 DPRC_ASSIGN
Command structure
Figure 32. DPRC_ASSIGN Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x157 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 OPTIONS CONTAINER_ID
63 32 31 0
0x10 ID_BASE_ALIGN NUM
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CONTAINER_ID ID of the child container
32-63 OPTIONS Request options: combination of DPRC_RES_REQ_OPT_ options:bit 0: DPRC_RES_REQ_OPT_EXPLICIT - Explicit resource ID request - The requested objects/resources are explicit and sequential (in case of resources). The base ID is given at res_req at base_align fieldbit 1: DPRC_RES_REQ_OPT_ALIGNED - Aligned resources request - Relevant only for resources request (and not objects). Indicates that resources base ID should be sequential and aligned to the value given at dprc_res_req base_align fieldbit 2: DPRC_RES_REQ_OPT_PLUGGED - Plugged Flag - Relevant only for object assignment request. Indicates that after all objects assigned. An interrupt will be invoked at the relevant GPP. The assigned object will be marked as plugged. Plugged objects can't be assigned from their container
0x10 0-31 NUM Number of resources
32-63 ID_BASE_ALIGN In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT is set at option), this field represents the required base ID for resource allocation;In case of aligned assignment (DPRC_RES_REQ_OPT_ALIGNED is set atoption), this field indicates the required alignment for theresource ID(s) - use 0 if there is no alignment or explicit IDrequirements
0x18 0-63 TYPE[0-5] Resource/object type: Represent as a NULL terminated string.This string may received by using dprc_get_pool() to get resourcetype and dprc_get_obj() to get object type;Note: it is not possible to assign/un-assign DPRC objects
0x20 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-27
6.3.18 DPRC_UNASSIGN
Command structure
Figure 33. DPRC_UNASSIGN Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x158 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 OPTIONS CHILD_CONTAINER_ID
63 32 31 0
0x10 ID_BASE_ALIGN NUM
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 CHILD_CONTAINER_ID ID of the child container
32-63 OPTIONS Request options: combination of DPRC_RES_REQ_OPT_ options:bit 0: DPRC_RES_REQ_OPT_EXPLICIT - Explicit resource ID request - The requested objects/resources are explicit and sequential (in case of resources). The base ID is given at res_req at base_align fieldbit 1: DPRC_RES_REQ_OPT_ALIGNED - Aligned resources request - Relevant only for resources request (and not objects). Indicates that resources base ID should be sequential and aligned to the value given at dprc_res_req base_align fieldbit 2: DPRC_RES_REQ_OPT_PLUGGED - Plugged Flag - Relevant only for object assignment request. Indicates that after all objects assigned. An interrupt will be invoked at the relevant GPP. The assigned object will be marked as plugged. Plugged objects can't be assigned from their container
0x10 0-31 NUM Number of resources
32-63 ID_BASE_ALIGN In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT is set at option), this field represents the required base ID for resource allocation;In case of aligned assignment (DPRC_RES_REQ_OPT_ALIGNED is set atoption), this field indicates the required alignment for theresource ID(s) - use 0 if there is no alignment or explicit IDrequirements
0x18 0-63 TYPE[0-5] Resource/object type: Represent as a NULL terminated string.This string may received by using dprc_get_pool() to get resourcetype and dprc_get_obj() to get object type;Note: it is not possible to assign/un-assign DPRC objects
0x20 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-28
6.3.19 DPRC_GET_POOL_COUNT
Command structure
Figure 34. DPRC_GET_POOL_COUNT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x16A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-29
Response structure
Figure 35. DPRC_GET_POOL_COUNT Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x16A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — POOL_COUNT
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 POOL_COUNT Number of resource pools in the DPRC
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-30
6.3.20 DPRC_GET_POOL
Command structure
Figure 36. DPRC_GET_POOL Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x169 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — POOL_INDEX
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 POOL_INDEX Index of the pool to be queried (< pool_count)
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-31
Response structure
Figure 37. DPRC_GET_POOL Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x169 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 TYPE[0-7] The type of the pool
0x18 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-32
6.3.21 DPRC_GET_OBJ_COUNT
Command structure
Figure 38. DPRC_GET_OBJ_COUNT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x159 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-33
Response structure
Figure 39. DPRC_GET_OBJ_COUNT Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x159 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 OBJ_COUNT —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 OBJ_COUNT Number of objects assigned to the DPRC
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-34
6.3.22 DPRC_GET_OBJ
Command structure
Figure 40. DPRC_GET_OBJ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — OBJ_INDEX
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-32 OBJ_INDEX Index of the object to be queried (< obj_count)
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-35
Response structure
Figure 41. DPRC_GET_OBJ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ID —
63 32 31 24 23 16 15 0
0x10 STATE REGION_COUNT
IRQ_COUNT VENDOR
63 32 31 0
0x18 — VERSION_MINOR VERSION_MAJOR
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x30 LABEL7 LABEL6 LABEL5 LABEL4 LABEL3 LABEL2 LABEL1 LABEL0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x38 LABEL15 LABEL14 LABEL13 LABEL12 LABEL11 LABEL10 LABEL9 LABEL8
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 ID ID of logical object resource
0x10 0-15 VENDOR Object vendor identifier
16-23 IRQ_COUNT Number of interrupts supported by the object
24-31 REGION_COUNT Number of mappable regions supported by the object
32-63 STATE Object state: combination of DPRC_OBJ_STATE_ states:bit 0: DPRC_OBJ_STATE_OPEN - Opened state - Indicates that an object is open by at least one owner bit 1: DPRC_OBJ_STATE_PLUGGED - Plugged state - Indicates that the object is plugged
0x18 0-15 VER_MINOR Minor version number
16-31 VER_MAJOR Major version number
0x20 0-63 TYPE[0-7] Type of object: NULL terminated string
0x28 0-63 TYPE[8-15]
0x30 0-63 LABEL[0-7] Object label
0x38 0-63 LABEL[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-36
6.3.23 DPRC_GET_OBJ_DESC
Command structure
Figure 42. DPRC_GET_OBJ_DESC Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x162 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — OBJ_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 OBJ_TYPE7 OBJ_TYPE6 OBJ_TYPE5 OBJ_TYPE4 OBJ_TYPE3 OBJ_TYPE2 OBJ_TYPE1 OBJ_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 OBJ_TYPE15 OBJ_TYPE14 OBJ_TYPE13 OBJ_TYPE12 OBJ_TYPE11 OBJ_TYPE10 OBJ_TYPE9 OBJ_TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-32 OBJ_ID The ID of the object to get its descriptor
0x10 0-63 OBJ_TYPE[0-7] The type of the object to get its descriptor
0x18 0-63 OBJ_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-37
Response structure
Figure 43. DPRC_GET_OBJ_DESC Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x162 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ID —
63 32 31 24 23 16 15 0
0x10 STATE REGION_COUNT
IRQ_COUNT VENDOR
63 32 31 0
0x18 — VERSION_MINOR VERSION_MAJOR
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x30 LABEL7 LABEL6 LABEL5 LABEL4 LABEL3 LABEL2 LABEL1 LABEL0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x38 LABEL15 LABEL14 LABEL13 LABEL12 LABEL11 LABEL10 LABEL9 LABEL8
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 ID ID of logical object resource
0x10 0-15 VENDOR Object vendor identifier
16-23 IRQ_COUNT Number of interrupts supported by the object
24-31 REGION_COUNT Number of mappable regions supported by the object
32-63 STATE Object state: combination of DPRC_OBJ_STATE_ states:bit 0: DPRC_OBJ_STATE_OPEN - Opened state - Indicates that an object is open by at least one owner bit 1: DPRC_OBJ_STATE_PLUGGED - Plugged state - Indicates that the object is plugged
0x18 0-15 VER_MINOR Minor version number
16-31 VER_MAJOR Major version number
0x20 0-63 TYPE[0-7] Type of object: NULL terminated string
0x28 0-63 TYPE[8-15]
0x30 0-63 LABEL[0-7] Object label
0x38 0-63 LABEL[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-38
6.3.24 DPRC_GET_RES_COUNT
Command structure
Figure 44. DPRC_GET_RES_COUNT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 TYPE[0-7] pool type
0x18 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-39
Response structure
Figure 45. DPRC_GET_RES_COUNT Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — RES_COUNT
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 RES_COUNT Number of free resources of the givenresource type that are assigned to this DPRC
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-40
6.3.25 DPRC_GET_RES_IDS
Command structure
Figure 46. DPRC_GET_RES_IDS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15C — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 49 48 42 41 0
0x08 ITER_STATUS —
63 32 31 0
0x10 LAST_ID BASE_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 42-48 ITER_STATUS Iteration status - should be set to DPRC_ITER_STATUS_FIRST atfirst iteration; while the returned marker is DPRC_ITER_STATUS_MORE,additional iterations are needed, until the returned marker isDPRC_ITER_STATUS_LAST
0x10 0-31 BASE_ID Base resource ID of this range
32-63 LAST_ID Last resource ID of this range
0x18 0-63 TYPE[0-7] pool type
0x20 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-41
Response structure
Figure 47. DPRC_GET_RES_IDS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15C — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 0
0x08 — ITER_STATUS —
63 32 31 0
0x10 LAST_ID BASE_ID
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 40-47 ITER_STATUS Iteration status - should be set to DPRC_ITER_STATUS_FIRST atfirst iteration; while the returned marker is DPRC_ITER_STATUS_MORE,additional iterations are needed, until the returned marker isDPRC_ITER_STATUS_LAST
0x10 0-31 BASE_ID Base resource ID of this range
32-63 LAST_ID Last resource ID of this range
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-42
6.3.26 DPRC_GET_OBJ_REGION
Command structure
Figure 48. DPRC_GET_OBJ_REGION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15E — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 32 31 0
0x08 — REGION_INDEX — OBJ_ID
63 0
0x10 —
63 0
0x18 —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 OBJ_TYPE7 OBJ_TYPE6 OBJ_TYPE5 OBJ_TYPE4 OBJ_TYPE3 OBJ_TYPE2 OBJ_TYPE1 OBJ_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 OBJ_TYPE15 OBJ_TYPE14 OBJ_TYPE13 OBJ_TYPE12 OBJ_TYPE11 OBJ_TYPE10 OBJ_TYPE9 OBJ_TYPE8
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 OBJ_ID Unique object instance as returned in dprc_get_obj()
48-55 REGION_INDEX The specific region to query
0x20 0-63 OBJ_TYPE[0-7] Object type as returned in dprc_get_obj()
0x28 0-63 OBJ_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-43
Response structure
Figure 49. DPRC_GET_OBJ_REGION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15E — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 BASE_PADDR
63 32 31 0
0x18 — SIZE
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 BASE_PADDR Region base physical address
0x18 0-31 SIZE Region size (in bytes)
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-44
6.3.27 DPRC_SET_OBJ_LABEL
Command structure
Figure 50. DPRC_SET_OBJ_LABEL Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x161 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — OBJ_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 LABEL7 LABEL6 LABEL5 LABEL4 LABEL3 LABEL2 LABEL1 LABEL0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 LABEL15 LABEL14 LABEL13 LABEL12 LABEL11 LABEL10 LABEL9 LABEL8
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 OBJ_TYPE7 OBJ_TYPE6 OBJ_TYPE5 OBJ_TYPE4 OBJ_TYPE3 OBJ_TYPE2 OBJ_TYPE1 OBJ_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 OBJ_TYPE15 OBJ_TYPE14 OBJ_TYPE13 OBJ_TYPE12 OBJ_TYPE11 OBJ_TYPE10 OBJ_TYPE9 OBJ_TYPE8
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 OBJ_ID Unique object instance as returned in dprc_get_obj()
0x10 0-63 LABEL[0-7] Object label
0x18 0-63 LABEL[8-15]
0x20 0-63 OBJ_TYPE[0-7] Object type as returned in dprc_get_obj()
0x28 0-63 OBJ_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-45
6.3.28 DPRC_SET_OBJ_IRQ
Command structure
Figure 51. DPRC_SET_OBJ_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15F — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 — IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 OBJ_ID IRQ_NUM
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 OBJ_TYPE7 OBJ_TYPE6 OBJ_TYPE5 OBJ_TYPE4 OBJ_TYPE3 OBJ_TYPE2 OBJ_TYPE1 OBJ_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 OBJ_TYPE15 OBJ_TYPE14 OBJ_TYPE13 OBJ_TYPE12 OBJ_TYPE11 OBJ_TYPE10 OBJ_TYPE9 OBJ_TYPE8
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into irq_addr address
32-39 IRQ_INDEX The interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-31 IRQ_NUM A user defined number associated with this IRQ
32-63 OBJ_ID ID of the object to set its IRQ
0x20 0-63 OBJ_TYPE[0-7] Type of the object to set its IRQ
0x28 0-63 OBJ_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-46
6.3.29 DPRC_GET_OBJ_IRQ
Command structure
Figure 52. DPRC_GET_OBJ_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15F — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 — IRQ_INDEX OBJ_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 OBJ_TYPE7 OBJ_TYPE6 OBJ_TYPE5 OBJ_TYPE4 OBJ_TYPE3 OBJ_TYPE2 OBJ_TYPE1 OBJ_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 OBJ_TYPE15 OBJ_TYPE14 OBJ_TYPE13 OBJ_TYPE12 OBJ_TYPE11 OBJ_TYPE10 OBJ_TYPE9 OBJ_TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 OBJ_ID ID of the object to get its IRQ
32-39 IRQ_INDEX The interrupt index to configure
0x10 0-63 OBJ_TYPE[0-7] Type of the object to get its IRQ
0x18 0-63 OBJ_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-47
Response structure
Figure 53. DPRC_GET_OBJ_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x15F — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into irq_addr address
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-31 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type: 0 represents message interrupttype (both irq_addr and irq_val are valid)
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-48
6.3.30 DPRC_CONNECT
Command structure
Figure 54. DPRC_CONNECT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x167 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ENDPOINT1_INTERFACE_ID ENPOINT1_ID
63 32 31 0
0x10 ENDPOINT2_INTERFACE_ID ENPOINT2_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 EP1_TYPE7 EP1_TYPE6 EP1_TYPE5 EP1_TYPE4 EP1_TYPE3 EP1_TYPE2 EP1_TYPE1 EP1_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 EP1_TYPE15 EP1_TYPE14 EP1_TYPE13 EP1_TYPE12 EP1_TYPE11 EP1_TYPE10 EP1_TYPE9 EP1_TYPE8
63 32 31 0
0x28 COMMITTED_RATE MAX_RATE
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x30 EP2_TYPE7 EP2_TYPE6 EP2_TYPE5 EP2_TYPE4 EP2_TYPE3 EP2_TYPE2 EP2_TYPE1 EP2_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x38 EP2_TYPE15 EP2_TYPE14 EP2_TYPE13 EP2_TYPE12 EP2_TYPE11 EP2_TYPE10 EP2_TYPE9 EP2_TYPE8
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ENDPOINT1_ID Endpoint object ID
32-63 ENDPOINT1_INTERFACE_ID Interface ID; should be set for endpoints with multiple interfaces("dpsw", "dpdmux"); for others, always set to 0
0x10 0-31 ENDPOINT2_ID Endpoint object ID
32-63 ENDPOINT2_INTERFACE_ID Interface ID; should be set for endpoints with multiple interfaces("dpsw", "dpdmux"); for others, always set to 0
0x18 0-63 ENDPOINT1_TYPE[0-5] Endpoint object type: NULL terminated string
0x20 0-63 ENDPOINT1_TYPE[8-15]
0x18 0-31 MAX_RATE Maximum rate (Mbits/s)
32-63 COMMITTED_RATE Committed rate (Mbits/s)
0x30 0-63 ENDPOINT2_TYPE[0-5] Endpoint object type: NULL terminated string
0X38 0-63 ENDPOINT2_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-49
6.3.31 DPRC_DISCONNECT
Command structure
Figure 55. DPRC_DISCONNECT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x168 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 INTERFACE_ID ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 TYPE7 TYPE6 TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 TYPE15 TYPE14 TYPE13 TYPE12 TYPE11 TYPE10 TYPE9 TYPE8
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID Endpoint object ID
32-63 INTERFACE_ID Interface ID; should be set for endpoints with multiple interfaces("dpsw", "dpdmux"); for others, always set to 0
0x10 0-63 TYPE[0-5] Endpoint object type: NULL terminated string
0x18 0-63 TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-50
6.3.32 DPRC_GET_CONNECTION
Command structure
Figure 56. DPRC_GET_CONNECTION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x16C — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ENDPOINT1_INTERFACE_ID ENPOINT1_ID
63 32 31 0
0x10 EP1_TYPE7 EP1_TYPE6 EP1_TYPE5 EP1_TYPE4 EP1_TYPE3 EP1_TYPE2 EP1_TYPE1 EP1_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 EP1_TYPE15 EP1_TYPE14 EP1_TYPE13 EP1_TYPE12 EP1_TYPE11 EP1_TYPE10 EP1_TYPE9 EP1_TYPE8
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ENDPOINT1_ID Endpoint object ID
32-63 ENDPOINT1_INTERFACE_ID Interface ID; should be set for endpoints with multiple interfaces("dpsw", "dpdmux"); for others, always set to 0
0x10 0-63 ENDPOINT1_TYPE[0-5] Endpoint object type: NULL terminated string
0x18 0-63 ENDPOINT1_TYPE[8-15]
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-51
Response structure
Figure 57. DPRC_GET_CONNECTION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x20F — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 ENDPOINT2_INTERFACE_ID ENPOINT2_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 EP2_TYPE7 EP2_TYPE6 EP2_TYPE5 EP2_TYPE4 EP2_TYPE3 EP2_TYPE2 EP2_TYPE1 EP2_TYPE0
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x30 EP2_TYPE15 EP2_TYPE14 EP2_TYPE13 EP2_TYPE12 EP2_TYPE11 EP2_TYPE10 EP2_TYPE9 EP2_TYPE8
63 0
0x38 — STATE
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x20 0-31 ENDPOINT2_ID Endpoint object ID
32-63 ENDPOINT2_INTERFACE_ID Interface ID; should be set for endpoints with multiple interfaces("dpsw", "dpdmux"); for others, always set to 0
0x28 0-63 ENDPOINT2_TYPE[0-5] Endpoint object type: NULL terminated string
0X30 0-63 ENDPOINT2_TYPE[8-15]
0x38 0-31 STATE Link state: 1 - link is up, 0 - link is down
DPRC: Data Path Resource Container
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 6-52
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-1
Chapter 7 DPNI: Data Path Network InterfaceThe MC exports a standard network interface that is configurable to support a wide range of features from a very basic Ethernet interface up to a high-functioning network interface. The DPNI supports standard features that are expected by standard network stacks, and also offers various offload functions, such as filtering, QoS, checksum validation/generation, time-stamping, VLAN add/remove operations, IP Reassembly and IP Fragmentation.
DPNI assumes that traffic consists of standard network packets (L2, L3, L4, etc.).
Please refer to the API book for complete reference of available functions.
7.1 DPNI featuresThe following list summarizes the DPNI main features and capabilities:
• Supports Ethernet network interfaces at different rates
• Supports maximum frame size of 10KB
• Allows association with up to eight different Data Path Buffer Pools (DPBP objects)
• Allows interaction with one or more Data Path I/O (DPIO) objects for dequeueing/enqueueing frame descriptors (FD) and for acquiring/releasing buffers.
• Supports connection to various DPAA2 network objects: DPMAC, DPSW interface, DPDMUX interface, as well as another DPNI
• Supports wire-speed frame parsing; parsing results may be visible in the frame annotation area
• Supports unicast promiscuous and multicast promiscuous modes
• Supports filtering of received frames:
— Exact-match filtering based on unicast destination MAC address
— Exact-match filtering based on multicast destination MAC address
— Exact-match filtering based on VLAN
• QoS support:
— Packet classification to up to eight traffic classes
— Classification based on user-defined keys (with key size up to 56 bytes)
• Supports distribution over frame queues:
— Statistical distribution based on hash-generated key
— Explicit distribution based on user-defined flow selection (with key size up to 56 bytes)
• Supports different scheduling options for processing received packets:
— Queues can be configured either in ‘parked’ mode (default), or attached to a DPIO object, or attached to DPCON object
• Supports traffic shaping of transmitted packets:
— Up to eight transmit queues matching eight traffic classes
• Supports transmit confirmation of all packets or transmission errors only
• Supports L3 and L4 checksum generation
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-2
• Supports L3 and L4 checksum validation
• Supports network interface statistics:
— Ingress frames count
— Ingress bytes count
— Ingress frames dropped due to explicit ‘drop’ setting
— Ingress frames discarded due to errors
— Ingress multicast frames count
— Ingress multicast bytes count
— Ingress broadcast frames count
— Ingress broadcast bytes count
— Egress frames count
— Egress bytes count
— Egress frames discarded due to errors
• Supports link state indication – a network link is up only when the DPNI is initialized and enabled (this statement is assuming that the peer network entity is also enabled).
• Supports network interface interrupts:
— Link change events
• Supports enable, disable, and reset operations
7.2 DPNI functional description
7.2.1 Ingress frame processing
The figure and paragraphs below describe the DPNI processing phases on ingress.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-3
Figure 58. DPNI Processing Phases for Ingress Frames
a) A frame arrives at the DPNI from another object, such as DPMAC, DPSW or other object.
b) Parsing: The frame is parsed to locate the headers from which lookup keys can be generated.
c) Filtering: The Destination MAC address and VLAN (if exists) are matched against user-defined filters; frames that do not match the filters are dropped.
NOTEDPNI allows configuration of promiscuous mode for unicast and/or multicast addresses; these modes, if enabled, override the MAC filter.
d) VLAN Removal [Optional]: The VLAN header may be removed from the frame (requires active AIOP)
e) IP Reassembly [Optional]: IP fragments may be reassembled into a full IP frame (requires active AIOP)
f) QoS: The DPNI supports up to eight ingress traffic classes and a variable number of QMan frame queues per traffic class. The frame is classified to one of the traffic classes based on user-defined lookup keys; the selected traffic class causes a specific set of queues to be selected.
g) Policing: The frame is ‘colored’ based on the policing profile defined for the traffic class, followed by WRED algorithm that discards lowest priority frames if needed.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-4
h) Distribution: The DPNI selects a destination frame queue for the frame, using either another user-defined lookup (explicit flow steering) or an RSS-style hashing operation; this lookup selects the final destination queue within the previously selected set (of the selected traffic class).
i) The frame is enqueued onto the queue, and the queue represents the destination indirectly. At this point, DPIO objects enter the process. Every queue is configured to deliver data availability notifications to a specific DPIO, and these notifications tell the driver software using the DPIO that one or more frames are available to read from a specific queue. Driver software responds by using a DPIO (actually any of its DPIOs) to read a burst of one or more frames from the queue.
The GPP driver software may steer any set of receive queues to DPIO or DPCON objects; the DPNI configures the relevant queue to generate notifications through the associated DPIO or DPCON, as explained below.
Any DPNI receive queue can be associated with a DPIO object. A DPIO object may operate with notifications enabled, and in this case the queues associated with the DPIO generate FQDAN (Frame Queue Data Available Notification) messages to GPP software when data is available.
DPNI receive queues can alternatively be associated with a DPCON object. When DPCON objects are connected to a DPIO object where notifications are enabled, the DPCON generates CDAN (Channel Data Available Notification) messages to GPP software when data is available.
GPP software may apply any of the following ingress scheduling options on the network interface:
a) Poll the DPNI queues using explicit dequeue requests through DPIO. In this case, the network interface driver is self-scheduling the dequeue calls.
b) Use the DPIO object to get FQDAN notifications on the data availability in the DPNI queues, and then dequeue from those queues. Driver may control scheduling by prioritizing the queues (FQDAN messages will be prioritized).
c) An alternating method of options (a) and (b), such as in NAPI mode.
d) Use the DPCON object to employ hardware-assisted scheduling of different receive queues. DPCON also allows the driver to schedule ingress traffic between different network interfaces. GPP software may select specific flows to go through DPCON, and to get CDAN notifications on data availability for those flows. Other flows can be scheduled according to any of the former three options.
Options (a), (b), and (c) above do not require a DPCON object; the combination of DPNI and DPIO is sufficient.
7.2.2 Egress frame processing
The figure and paragraphs below describe the DPNI processing phases on ingress.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-5
Figure 59. DPNI Processing Phases for Egress Frames
a) Driver software enqueues a frame onto one of the transmit queues, by indicating the desired transmit priority (traffic class); the DPNI supports one logical transmit queue per traffic class
b) IP Fragmentation [optional]: IP packet may be split into fragments according to selected MTU value (requires active AIOP).
c) VLAN Insertion [optional]: a user-defined VLAN header may be added to the frame before transmission (requires active AIOP).
d) Scheduling and shaping: the frame is scheduled for transmission based the relative priority of its traffic class among other transmitted frames. DPNI may also apply user-defined rate limitation on egress.
e) The frame leaves the DPNI and is sent through DPMAC to an external port, or alternatively to another network object such as DPSW.
The egress configuration involves up to eight traffic classes, each having its own transmit queue.
Transmit confirmation involves a dedicated confirmation queue per DPIO – the confirmation queue is used to transmit confirmation of all packets, or optionally to only transmit errors, that were transmitted using that DPIO. Transmit confirmation queues are configured to deliver packets through the respective DPIO. The DPIO object may operate with notifications enabled or disabled, and the DPIO has its own dedicated channel for passing notifications.
7.2.3 Relationship with DPIO and DPCON objects
A DPNI object can be fully operational only by association with at least one DPIO object. Mainly, DPIO objects provide configuration of a QBMan software portal, with an option for data availability notifications. GPP software is free to relate DPIO objects to threads, or to share them between cores in SMP mode but this requires synchronized access to the QBMan software portal. It is possible to associate multiple DPIO objects with the same DPNI, in order to spread traffic from this DPNI across multiple QBMan software portals.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-6
GPP software may decide to enable DPIO notifications, or it may dequeue frames based on its own scheduled polling logic. It is also possible for one GPP entity to receive the notification from one DPIO and alert another entity that will dequeue the packets using a different DPIO.
DPCON objects are used for concentrating traffic from several interfaces into sub-interfaces, mainly for scheduling purposes. It is possible to connect DPCON with DPIO so it generates notifications to the GPP.
Note that the QBMan software portal is used both for enqueue/dequeue operations on packets, and for acquire/release buffer operations. GPP software is responsible for the portal’s operation mode and usage i.e. sharing vs. affinity, NAPI mode vs. other modes, association of queue context, etc.
DPIO objects may serve multiple interfaces. This is not limited to multiple DPNI objects; it can also be combined with communication interfaces and accelerator interfaces. For example, the same DPIO may serve both a DPNI and a DPCI, assuming they are assigned to the same software context (container).
7.2.4 Relationship with DPBP objects
A DPNI object can be fully operational only by association with at least one DPBP object. Each DPNI must be associated with at least one and up to eight DPBP objects, which allows the flexible use of different buffer pools.
A DPBP object may be associated with several DPNI objects from the same software context. It is also possible to initialize and associate a private DPBP object per DPNI; the GPP/AIOP software context has to decide whether sharing is required.
7.2.5 Ingress QoS
The DPNI supports classification of received frames to traffic classes (up to 8). This is done by matching the incoming frame with a user-defined lookup key (optionally with a mask). The result of the lookup in the QoS table determines the traffic class for the received frame.
Each traffic class has its own set of attributes, for example distribution options, policing options
All QoS-related functions require that the DPNI is created with multiple traffic classes (refer to MAX_TCS setting in DPNI_CREATE).
The user may select a flexible lookup key for the QoS table. This is done by invoking the DPNI_SET_QOS_TABLE command. Following that step, the user may add and remove QoS entries using the DPNI_ADD_QOS_ENTRY and DPNI_REMOVE_QOS_ENTRY commands.
7.2.6 Ingress distribution
The ingress distribution phase selects a final destination queue within the previously selected set (of chosen traffic class). The DPNI selects a destination frame queue for the frame using one of the following methods:
• Explicit flow steering – based on user-defined lookup, or
• RSS-style hashing operation – hashing is based on user-defined key
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-7
Distribution functionality is valid only if the DPNI_OPT_DIST_FS and/or DPNI_OPT_DIST_HASH options were set at DPNI creation; otherwise, each traffic class has exactly (and only) one flow. Refer to the DPNI_CREATE for description of these options and of DPNI_DIST_SIZE_TC0..7, which defines the maximum distribution size per traffic class.
The first step in applying any type of distribution is to invoke the DPNI_SET_RX_TC_DIST command to select the distribution mode (DIST_MODE = DPNI_DIST_MODE_FS / DPNI_DIST_MODE_HASH / DPNI_DIST_MODE_NONE). The distribution mode is selected per traffic class, so each traffic class may have different distribution method. User must also define the distribution size for each traffic class. For GPP software, the distribution size determines the number of receive queues in that traffic class.
If flow steering distribution mode is selected, user must also provide the lookup key format for the flow steering table. Following this step, user can start adding explicit flow steering entries to direct each flow to the required receive queue. Please refer to DPNI_ADD_QOS_ENTRY command for more details. Note that unmatched flows may either be dropped or directed to the default flow ID (FLOW_ID = 0).
7.3 DPNI command referenceThis section contains the detailed programming model of DPNI commands.
7.3.1 DPNI_CREATE
Create the DPNI object, allocate required resources and perform required initialization. The object can be created either by declaring it in the DPL file, or by invoking this command. This command includes all required parameters for the instantiation of the DPNI object. Some parameters have default settings.
This command returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent calls to this specific object. For objects that are created using the DPL file, use DPNI_OPEN to get an authentication token first.
The command format is shown in the figure below.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-8
Command structure
Figure 60. DPNI_CREATE Command Description
The following table describes the command fields.Table 6. DPNI_CREATE Command Field Descriptions
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x901 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 MAX_SENDERS MAX_TCS
63 32 31 0
0x10 – OPTIONS (details in the table below)
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 START_HDR MAX_DIST_KEY_SIZE
– MAX_QOS_KEY_SIZE
MAX_QOS_ENTRIES
MAX_VLAN_FILTERS
MAX_MULTICAST_FILTERS
MAX_UNICAST_FILTERS
63 0
0x20 –
63 56 55 48 47 0
0x28 MAX_CONGESTION_CTRL
MAX_POLICERS –
63 0
0x30 EXT_CFG_IOVA
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 MAX_TCS Maximum number of traffic classes (1-8), affecting both the receive side and the transmit side.A value of 0 is treated as 1.
8-15 MAX_SENDERS Maximum number of different senders (transmitting entities); used as the number of dedicated transmit flows.A value of 0 is treated as 1.
16-63 MAC_ADDR0..5 Primary MAC address bytes (byte 0 is the most significant byte).
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-9
0x10 OPTIONS – select one or more of the options below
0 DPNI_OPT_ALLOW_DIST_KEY_PER_TC Allow different distribution key profiles for different traffic classes.If not set, a single key profile is assumed.
1 DPNI_OPT_TX_CONF_DISABLED Disable transmit confirmation on all transmit queues
2 DPNI_OPT_PRIVATE_TX_CONF_ERR_DISABLED Disable private (per-sender) transmit confirmation/error queue
3 – Reserved
4 DPNI_OPT_DIST_HASH Support distribution based on hash. Allows statistical distribution over receive queues.
5 DPNI_OPT_DIST_FS Support distribution based on explicit flow steering. Allows explicit and controlled distribution (not statistical) over the receive queues.
6 DPNI_OPT_POLICING Support policing of ingress frames
7 DPNI_OPT_UNICAST_FILTER Support unicast filtering on ingress
8 DPNI_OPT_MULTICAST_FILTER Support multicast filtering on ingress
9 DPNI_OPT_VLAN_FILTER Support VLAN filtering on ingress
10 – Reserved
11 DPNI_OPT_IPR Support IP reassembly on ingress
12 DPNI_OPT_IPF Support IP fragmentation on egress
13-15 – Reserved
16 DPNI_OPT_VLAN_MANIPULATION Support VLAN removal on ingress and/or VLAN insertion on egress
17-32 – Reserved
0x18 0-7 MAX_UNICAST_FILTERS Maximum number of unicast filters (addresses).A value of 0 is treated as 16 (DPNI_MAX_UNICAST_FILTERS).Valid only if DPNI_OPT_UNICAST_FILTER is set.
8-15 MAX_MULTIICAST_FILTERS Maximum number of multicast filters (addresses).A value of 0 is treated as 64 (DPNI_MAX_MULTICAST_FILTERS).Valid only if DPNI_OPT_MULTICAST_FILTER is set.
16-23 MAX_VLAN_FILTERS Maximum number of VLAN filters (VLAN IDs).A value of 0 is treated as 16 (DPNI_MAX_VLAN_FILTERS).Valid only if DPNI_OPT_VLAN_FILTER is set.
24-31 MAX_QOS_ENTRIES Maximum number of entries in the QoS table.Valid only if the option bit is set.A value of 0 is treated as 64 (DPNI_MAX_QOS_ENTRIES).Valid only if MAX_TCS is bigger than 1.
32-30 MAX_QOS_KEY_SIZE Maximum size for QoS keys.A value of 0 is treated as 24 (sufficient for IPv4 5-tuple).Valid only if MAX_TCS is bigger than 1.
48-55 MAX_DIST_KEY_SIZE Maximum size for distribution keys.A value of 0 is treated as 24 (sufficient for IPv4 5-tuple).Valid only if DPNI_OPT_DIST_HASH or DPNI_OPT_DIST_FS are set.
56-63 START_HDR Indicates the starting header for purpose of parsing incoming frames;a value of 0x00 selects standard Ethernet frame.
0x20 0-78-1516-2324-3132-3940-4748-5556-63
MAX_DIST_TC0..7 Maximum distribution size per traffic class (for traffic classes 0 to 7)
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-10
All unspecified fields are reserved and must be cleared (set to zero)
Extension structure
Figure 61. DPNI_CREATE Extension Description
The following table describes the command fields.Table 7. DPNI_CREATE Extension Field Descriptions
0x28 48-55 MAX_POLICERS Maximum number of policers; should be between ‘0’ and ‘max_tcs’
56-63 MAX_CONGESTION_CTRL Maximum number of congestion control groups (CGs); covers early drop and congestion notification requirements for traffic classes; should be between '0' and MAX_TCS
0x30 0-63 EXT_CFG_IOVA I/O virtual address of 256 bytes DMA-able memory containing the extension structure as described below.
Offset from Management Command Portal base Read-Write Access
63 48 47 32 31 16 15 0
0x00 TC1_MAX_FS_ENTRIES TC1_MAX_DIST TC0_MAX_FS_ENTRIES TC0_MAX_DIST
63 48 47 32 31 16 15 0
0x08 TC3_MAX_FS_ENTRIES TC3_MAX_DIST TC2_MAX_FS_ENTRIES TC2_MAX_DIST
63 48 47 32 31 16 15 0
0x10 TC5_MAX_FS_ENTRIES TC5_MAX_DIST TC4_MAX_FS_ENTRIES TC4_MAX_DIST
63 48 47 32 31 16 15 0
0x18 TC7_MAX_FS_ENTRIES TC7_MAX_DIST TC6_MAX_FS_ENTRIES TC6_MAX_DIST
63 48 47 32 31 16 15 0
0x20 – MAX_REASS_FRM_SIZE MAX_OPEN_FRAMES_IPV6 MAX_OPEN_FRAMES_IPV4
63 32 31 16 15 0
0x28 – MIN_FRAG_SIZE_IPV6 MIN_FRAG_SIZE_IPV4
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 - 0x18
0-15;32-47
TC[0..7]_MAX_DIST Maximum distribution size for Rx traffic class;supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, 112,128,192,224,256,384,448,512,768,896,1024;value '0' will be treated as '1'.other unsupported values will be round down to the nearest supported value.
16-31;48-63
TC[0..7]_MAX_FS_ENTRIES Maximum FS entries for Rx traffic class;'0' means no support for this TC;
0x20 0-15 MAX_OPEN_FRAMES_IPV4 Maximum concurrent IPv4 packets in reassembly process.Valid only if DPNI_OPT_IPR is set.
16-31 MAX_OPEN_FRAMES_IPV6 Maximum concurrent IPv6 packets in reassembly process.Valid only if DPNI_OPT_IPR is set.
32-47 MAX_REASS_FRAME_SIZE Maximum size of the reassembled frame.Valid only if DPNI_OPT_IPR is set.
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-11
All unspecified fields are reserved and must be cleared (set to zero)
7.3.2 DPNI_DESTROY
Destroy the DPNI object and release all its resources. This command can be invoked by the software context that created the object.
After this function is called, no further operations are allowed on the object.
Command structure
Figure 62. DPNI_DESTROY Command Description
The following table describes the command fields.Table 8. DPNI_DESTROY Command Field Description
All unspecified fields are reserved and must be cleared (set to zero)
0x28 16-31 MIN_FRAG_SIZE_IPV4 Minimum fragment size of IPv4 fragments.Valid only if DPNI_OPT_IPF is set.
32-47 MIN_FRAG_SIZE_IPV6 Minimum fragment size of IPv6 fragmentsValid only if DPNI_OPT_IPF is set.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-12
7.3.3 DPNI_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPNI_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
Figure 63. DPNI_OPEN Command Description
The following table describes the command fields.Table 9. DPNI_OPEN Command Field Descriptions
All unspecified fields are reserved and must be cleared (set to zero)
7.3.4 DPNI_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x801 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 0
0x08 – DPNI_ID
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPNI_ID DPNI unique ID
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-13
Command structure
Figure 64. DPNI_CLOSE Command Description
The following table describes the command fields.Table 10. DPNI_CLOSE Command Field Descriptions
7.3.5 DPNI_ENABLE
Enable the DPNI, allow sending and receiving frames.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-14
Command structure
Figure 65. DPNI_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.6 DPNI_DISABLE
Disable the DPNI, stop sending and receiving frames.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-15
Command structure
Figure 66. DPNI_DISABLE Command Description
The following table describes the command fields.Table 11. DPNI_DISABLE Command Fields Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.7 DPNI_IS_ENABLED
Check if the DPNI is enabled.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-16
Command structure
Figure 67. DPNI_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-17
Response structure
Figure 68. DPNI_IS_ENABLED Response Description
All unspecified fields are cleared.
7.3.8 DPNI_RESET
Reset the DPNI, returns the object to initial state.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if object is enabled
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-18
Command structure
Figure 69. DPNI_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.9 DPNI_SET_IRQ
Set IRQ information for the DPNI to trigger an interrupt.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-19
Command structure
Figure 70. DPNI_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.10 DPNI_GET_IRQ
Get IRQ information from the DPNI.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-20
Command structure
Figure 71. DPNI_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-21
Response structure
Figure 72. DPNI_GET_IRQ Response Description
All unspecified fields are cleared.
7.3.11 DPNI_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-22
Command structure
Figure 73. DPNI_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.12 DPNI_GET_IRQ_ENABLE
Get overall interrupt state.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-23
Command structure
Figure 74. DPNI_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-24
Response structure
Figure 75. DPNI_GET_IRQ_ENABLE Response Description
All unspecified fields are cleared.
7.3.13 DPNI_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-25
Command structure
Figure 76. DPNI_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.14 DPNI_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-26
Command structure
Figure 77. DPNI_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-27
Response structure
Figure 78. DPNI_GET_IRQ_MASK Response Description
All unspecified fields are cleared.
7.3.15 DPNI_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-28
Command structure
Figure 79. DPNI_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPNI_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-29
Response structure
Figure 80. DPNI_GET_IRQ_STATUS Response Description
All unspecified fields are cleared.
7.3.16 DPNI_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 0: DPNI_IRQ_EVENT_LINK_CHANGED – indicates a change in the link state
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-30
Command structure
Figure 81. DPNI_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.17 DPNI_GET_ATTRIBUTES
Retrieve DPNI attributes as configured when the object was created.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-31
Command structure
Figure 82. DPNI_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-32
Response structure
Figure 83. DPNI_GET_ATTRIBUTES Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 56 55 48 47 40 39 32 31 0
0x08 – START_HDR MAX_SENDERS MAX_TCS ID
63 32 31 0
0x10 OPTIONS
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 – MAX_DIST_KEY_SIZE
MAX_QOS_KEY_SIZE
MAX_QOS_ENTRIES
MAX_VLAN_FILTERS
MAX_MULTICAST_FILTERS
MAX_UNICAST_FILTERS
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 MAX_DIST_TC7 MAX_DIST_TC6 MAX_DIST_TC5 MAX_DIST_TC4 MAX_DIST_TC3 MAX_DIST_TC2 MAX_DIST_TC1 MAX_DIST_TC0
63 56 55 48 47 32 31 16 15 0
0x28 MAX_CONGESTION_CTRL
MAX_POLICERS MIN_FRAG_SIZE_IPV6 MIN_FRAG_SIZE_IPV4 MAX_REASS_FRM_SIZE
63 32 31 16 15 0
0x30 VERSION_MINOR VERSION_MAJOR MAX_OPEN_FRAMES_IPV6 MAX_OPEN_FRAMES_IPV4
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-33
All unspecified fields are cleared.
7.3.18 DPNI_SET_ERRORS_BEHAVIOR
Set errors behavior for the DPNI – decide which action to take when specific errors occur. This command may be repeated with different errors selection at each time.
0x08 0-31 ID The DPNI object’s unique ID
32-39 MAX_TCS Refer to DPNI_CREATE command for description of these fields
40-47 MAX_SENDERS
48-55 START_HDR
0x10 0-32 OPTIONS
0x18 0-7 MAX_UNICAST_FILTERS
8-15 MAX_MULTICAST_FILTERS
16-23 MAX_VLAN_FILTERS
24-31 MAX_QOS_ENTRIES
32-39 MAX_QOS_KEY_SIZE
40-47 MAX_DIST_KEY_SIZE
0x20 0-78-1516-2324-3132-3940-4748-5556-63
MAX_DIST_PER_TC 0..7
0x28 0-15 MAX_RAESS_FRAME_SIZE
16-31 MIN_FRAG_SIZE_IPV4
32-47 MIN_FRAG_SIZE_IPV6
48-55 MAX_POLICERS
56-63 MAX_CONGESTION_CTRL
0x30 0-15 MAX_OPEN_FRAMES_IPV4
16-31 MAX_OPEN_FRAMES_IPV6
32-47 VERSION_MAJOR DPNI major version number
48-63 VERSION_MINOR DPNI minor version number
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-34
Command structure
Figure 84. DPNI_SET_ERRORS_BEHAVIOR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x20B – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 37 36 35 32 31 0
0x08 –
SE
T_F
RA
ME
_AN
NO
TAT
ION
ER
RO
R_A
CT
ION
ERRORS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ERRORS The errors mask to configure. Select any combination of supported errors below:
Bit 0: DPNI_ERROR_L4CE – parser L4 checksum errorBit 2: DPNI_ERROR_L3CE – parser L3 checksum errorBit 5: DPNI_ERROR_PHE – Parsing header errorBit 12: DPNI_ERROR_FPE – Frame physical errorBit 13: DPNI_ERROR_FLE – Frame length errorBit 17: DPNI_ERROR_EOFHE – Extract out of frame header error
32-35 ERROR_ACTION Desired action for the errors selected in ERRORS mask. Select one of the supported values below:
0 = DPNI_ERROR_ACTION_DISCARD – Discard the frame1 = DPNI_ERROR_ACTION_CONTINUE – Continue with the normal flow2 = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE – Send the frame to the error queue
36 SET_FRAME_ANNOTATION Set to '1' to mark the errors in frame annotation status (FAS); relevant only for non-discard actions.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-35
7.3.19 DPNI_GET_RX_BUFFER_LAYOUT
Retrieve buffer layout attributes for the receive side.
Command structure
Figure 85. DPNI_GET_RX_BUFFER_LAYOUT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x201 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-36
Response structure
Figure 86. DPNI_GET_RX_BUFFER_LAYOUT Response Description
All unspecified fields are cleared.
7.3.20 DPNI_SET_RX_BUFFER_LAYOUT
Set buffer layout attributes for the receive side.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x201 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 16 15 0
0x08 – DATA_ALIGN PRIVATE_DATA_SIZE
63 48 47 32 31 16 15 3 2 1 0
0x10 – DATA_TAIL_ROOM DATA_HEAD_ROOM – PA
SS
_FR
AM
E_S
TAT
US
PA
SS
_PA
RS
ER
_RE
SU
LT
PA
SS
_TIM
ES
TAM
P
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIVATE_DATA_SIZE Size kept for private data (in bytes)
16-31 DATA_ALIGN Data alignment
0x10 0 PASS_TIMESTAMP ‘1’ indicates that time-stamp is included in the buffer layout
1 PASS_PARSER_RESULT ‘1’ indicates that parsing results are included in the buffer layout
2 PASS_FRAME_STATUS ‘1’ indicates that frame status is included in the buffer layout
16-31 DATA_HEAD_ROOM Data head room
32-47 DATA_TAIL_ROOM Data tail room
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-37
Command structure
Figure 87. DPNI_SET_RX_BUFFER_LAYOUT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x202 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 16 15 0
0x08 OPTIONS DATA_ALIGN PRIVATE_DATA_SIZE
63 48 47 32 31 16 15 3 2 1 0
0x10 – DATA_TAIL_ROOM DATA_HEAD_ROOM – PA
SS
_FR
AM
E_S
TAT
US
PA
SS
_PA
RS
ER
_RE
SU
LT
PA
SS
_TIM
ES
TAM
P
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIVATE_DATA_SIZE Size kept for private data (in bytes)
16-31 DATA_ALIGN Data alignment
32-63 OPTIONS Mask of bits indicating suggested modifications to the buffer layout:
Bit 0: DPNI_BUF_LAYOUT_OPT_TIMESTAMP – set to modify time-stamp settingBit 1: DPNI_BUF_LAYOUT_OPT_PARSER_RESULT – set to modify the parser-result setting.Bit 2: DPNI_BUF_LAYOUT_OPT_FRAME_STATUS – set to modify the frame-status setting.Bit 3: DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE– set to modify the private-data-size setting.Bit 4: DPNI_BUF_LAYOUT_OPT_DATA_ALIGN – set to modify the data-alignment setting.
0x10 0 PASS_TIMESTAMP ‘1’ indicates that time-stamp is included in the buffer layout
1 PASS_PARSER_RESULT ‘1’ indicates that parsing results are included in the buffer layout
2 PASS_FRAME_STATUS ‘1’ indicates that frame status is included in the buffer layout
16-31 DATA_HEAD_ROOM Data head room
32-47 DATA_TAIL_ROOM Data tail room
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-38
7.3.21 DPNI_GET_TX_BUFFER_LAYOUT
Retrieve buffer layout attributes for the transmit side.
Command structure
Figure 88. DPNI_GET_TX_BUFFER_LAYOUT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x203 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-39
Response structure
Figure 89. DPNI_GET_TX_BUFFER_LAYOUT Response Description
All unspecified fields are cleared.
7.3.22 DPNI_SET_TX_BUFFER_LAYOUT
Set buffer layout attributes for the transmit side.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x203 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 16 15 0
0x08 – DATA_ALIGN PRIVATE_DATA_SIZE
63 48 47 32 31 16 15 3 2 1 0
0x10 – DATA_TAIL_ROOM DATA_HEAD_ROOM – PA
SS
_FR
AM
E_S
TAT
US
PA
SS
_PA
RS
ER
_RE
SU
LT
PA
SS
_TIM
ES
TAM
P
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIVATE_DATA_SIZE Size kept for private data (in bytes)
16-31 DATA_ALIGN Data alignment
0x10 0 PASS_TIMESTAMP ‘1’ indicates that time-stamp is included in the buffer layout
1 PASS_PARSER_RESULT ‘1’ indicates that parsing results are included in the buffer layout
2 PASS_FRAME_STATUS ‘1’ indicates that frame status is included in the buffer layout
16-31 DATA_HEAD_ROOM Data head room
32-47 DATA_TAIL_ROOM Data tail room
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-40
Command structure
Figure 90. DPNI_SET_TX_BUFFER_LAYOUT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x204 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 32 31 16 15 0
0x08 OPTIONS DATA_ALIGN PRIVATE_DATA_SIZE
63 48 47 32 31 16 15 3 2 1 0
0x10 – DATA_TAIL_ROOM DATA_HEAD_ROOM – PA
SS
_FR
AM
E_S
TAT
US
PA
SS
_PA
RS
ER
_RE
SU
LT
PA
SS
_TIM
ES
TAM
P
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIVATE_DATA_SIZE Size kept for private data (in bytes)
16-31 DATA_ALIGN Data alignment
32-63 OPTIONS Mask of bits indicating suggested modifications to the buffer layout:
Bit 0: DPNI_BUF_LAYOUT_OPT_TIMESTAMP – set to modify time-stamp settingBit 2: DPNI_BUF_LAYOUT_OPT_FRAME_STATUS – set to modify the frame-status setting.Bit 3: DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE– set to modify the private-data-size setting.Bit 4: DPNI_BUF_LAYOUT_OPT_DATA_ALIGN – set to modify the data-alignment setting.
0x10 0 PASS_TIMESTAMP ‘1’ indicates that time-stamp is included in the buffer layout
1 PASS_PARSER_RESULT ‘1’ indicates that parsing results are included in the buffer layout
2 PASS_FRAME_STATUS ‘1’ indicates that frame status is included in the buffer layout
16-31 DATA_HEAD_ROOM Data head room
32-47 DATA_TAIL_ROOM Data tail room
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-41
7.3.23 DPNI_GET_TX_CONF_BUFFER_LAYOUT
Set buffer layout attributes for transmit confirmation (note that it is an input queue).
Command structure
Figure 91. DPNI_GET_TX_CONF_BUFFER_LAYOUT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x206 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-42
Response structure
Figure 92. DPNI_GET_TX_CONF_BUFFER_LAYOUT Response Description
All unspecified fields are cleared.
7.3.24 DPNI_SET_TX_CONF_BUFFER_LAYOUT
Set buffer layout attributes for transmit confirmation.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x206 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 32 31 16 15 0
0x08 – DATA_ALIGN PRIVATE_DATA_SIZE
63 48 47 32 31 16 15 3 2 1 0
0x10 – DATA_TAIL_ROOM DATA_HEAD_ROOM – PA
SS
_FR
AM
E_S
TAT
US
PA
SS
_PA
RS
ER
_RE
SU
LT
PA
SS
_TIM
ES
TAM
P
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIVATE_DATA_SIZE Size kept for private data (in bytes)
16-31 DATA_ALIGN Data alignment
0x10 0 PASS_TIMESTAMP ‘1’ indicates that time-stamp is included in the buffer layout
1 PASS_PARSER_RESULT ‘1’ indicates that parsing results are included in the buffer layout
2 PASS_FRAME_STATUS ‘1’ indicates that frame status is included in the buffer layout
16-31 DATA_HEAD_ROOM Data head room
32-47 DATA_TAIL_ROOM Data tail room
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-43
Command structure
Figure 93. DPNI_SET_TX_CONF_BUFFER_LAYOUT Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x205 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 32 31 16 15 0
0x08 OPTIONS DATA_ALIGN PRIVATE_DATA_SIZE
63 48 47 32 31 16 15 3 2 1 0
0x10 – DATA_TAIL_ROOM DATA_HEAD_ROOM – PA
SS
_FR
AM
E_S
TAT
US
PA
SS
_PA
RS
ER
_RE
SU
LT
PA
SS
_TIM
ES
TAM
P
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIVATE_DATA_SIZE Size kept for private data (in bytes)
16-31 DATA_ALIGN Data alignment
32-63 OPTIONS Mask of bits indicating suggested modifications to the buffer layout:
Bit 0: DPNI_BUF_LAYOUT_OPT_TIMESTAMP – set to modify time-stamp settingBit 1: DPNI_BUF_LAYOUT_OPT_PARSER_RESULT – set to modify the parser-result setting.Bit 2: DPNI_BUF_LAYOUT_OPT_FRAME_STATUS – set to modify the frame-status setting.Bit 3: DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE– set to modify the private-data-size setting.Bit 4: DPNI_BUF_LAYOUT_OPT_DATA_ALIGN – set to modify the data-alignment setting.
0x10 0 PASS_TIMESTAMP ‘1’ indicates that time-stamp is included in the buffer layout
1 PASS_PARSER_RESULT ‘1’ indicates that parsing results are included in the buffer layout
2 PASS_FRAME_STATUS ‘1’ indicates that frame status is included in the buffer layout
16-31 DATA_HEAD_ROOM Data head room
32-47 DATA_TAIL_ROOM Data tail room
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-44
7.3.25 DPNI_SET_L3_CHKSUM_VALIDATION
Enable or disable L3 checksum validation.
Command structure
Figure 94. DPNI_SET_L3_CHKSUM_VALIDATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.26 DPNI_GET_L3_CHKSUM_VALIDATION
Get L3 checksum validation mode.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x207 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Set to '1' to enable L3 checksum validation; '0' to disable
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-45
Command structure
Figure 95. DPNI_GET_L3_CHKSUM_VALIDATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x208 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-46
Response structure
Figure 96. DPNI_GET_L3_CHKSUM_VALIDATION Response Description
All unspecified fields are cleared.
7.3.27 DPNI_SET_L4_CHKSUM_VALIDATION
Enable or disable L4 checksum validation.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x208 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if L3 checksum validation is enabled
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-47
Command structure
Figure 97. DPNI_SET_L4_CHKSUM_VALIDATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x209 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Set to '1' to enable L4 checksum validation; '0' to disable
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-48
7.3.28 DPNI_GET_L4_CHKSUM_VALIDATION
Get L4 checksum validation mode.
Command structure
Figure 98. DPNI_GET_L4_CHKSUM_VALIDATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x20A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-49
Response structure
Figure 99. DPNI_GET_L4_CHKSUM_VALIDATION Response Description
All unspecified fields are cleared.
7.3.29 DPNI_GET_QDID
Get the Queuing Destination ID (QDID) that should be used for frame enqueue operations.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x20A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if L4 checksum validation is enabled
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-50
Command structure
Figure 100. DPNI_GET_QDID Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x210 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-51
Response structure
Figure 101. DPNI_GET_QDID Response Description
All unspecified fields are cleared.
7.3.30 DPNI_GET_SP_INFO
Get the AIOP storage profile ID associated with the DPNI – relevant only for DPNI that belongs to AIOP software context (resides in AIOP container).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x210 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 QDID
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 QDID Virtual QDID value that should be used as an argument in all enqueue operations
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-52
Command structure
Figure 102. DPNI_GET_SP_INFO Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x211 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-53
Response structure
Figure 103. DPNI_GET_SP_INFO Response Description
All unspecified fields are cleared.
7.3.31 DPNI_GET_TX_DATA_OFFSET
Get the data offset for transmit buffers (from start of buffer).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x211 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 16 15 0
0x08 – SPIDS_1 SPIDS_0
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 SPIDS[0..1] AIOP storage-profile ID
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-54
Command structure
Figure 104. DPNI_GET_TX_DATA_OFFSET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x212 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-55
Response structure
Figure 105. DPNI_GET_TX_DATA_OFFSET Response Description
All unspecified fields are cleared.
7.3.32 DPNI_GET_COUNTER
Read a specific DPNI counter.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x212 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 DATA_OFFSET
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 DATA_OFFSET Transmit-side data offset (from start of buffer)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-56
Command structure
Figure 106. DPNI_GET_COUNTER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x213 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – COUNTER
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 COUNTER Selects the counter type to query.
0x0: DPNI_CNT_ING_FRAME, counts ingress frames0x1: DPNI_CNT_ING_BYTE, counts ingress bytes0x2: DPNI_CNT_ING_FRAME_DROP, counts ingress frames dropped due to explicit 'drop' setting0x3: DPNI_CNT_ING_FRAME_DISCARD, counts ingress frames discarded due to errors0x4: DPNI_CNT_ING_MCAST_FRAME, counts ingress multicast frames0x5: DPNI_CNT_ING_MCAST_BYTE, counts ingress multicast bytes0x6: DPNI_CNT_ING_BCAST_FRAME, counts ingress broadcast frames0x7: DPNI_CNT_ING_BCAST_BYTES, counts ingress broadcast bytes0x8: DPNI_CNT_EGR_FRAME, counts egress frames0x9: DPNI_CNT_EGR_BYTE, counts egress bytes0xA: DPNI_CNT_EGR_FRAME_DISCARD, counts egress frames discarded due to errors
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-57
Response structure
Figure 107. DPNI_GET_COUNTER Response Description
All unspecified fields are cleared.
7.3.33 DPNI_SET_COUNTER
Set (or clear) a specific DPNI counter.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x213 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 VALUE
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 VALUE Value of the selected counter
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-58
Command structure
Figure 108. DPNI_SET_COUNTER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.34 DPNI_SET_LINK_CFG
Set the link configuration
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x214 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – COUNTER
63 0
0x10 VALUE
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 COUNTER Selects the counter type to query.
0x0: DPNI_CNT_ING_FRAME, counts ingress frames0x1: DPNI_CNT_ING_BYTE, counts ingress bytes0x2: DPNI_CNT_ING_FRAME_DROP, counts ingress frames dropped due to explicit 'drop' setting0x3: DPNI_CNT_ING_FRAME_DISCARD, counts ingress frames discarded due to errors0x4: DPNI_CNT_ING_MCAST_FRAME, counts ingress multicast frames0x5: DPNI_CNT_ING_MCAST_BYTE, counts ingress multicast bytes0x6: DPNI_CNT_ING_BCAST_FRAME, counts ingress broadcast frames0x7: DPNI_CNT_ING_BCAST_BYTES, counts ingress broadcast bytes0x8: DPNI_CNT_EGR_FRAME, counts egress frames0x9: DPNI_CNT_EGR_BYTE, counts egress bytes0xA: DPNI_CNT_EGR_FRAME_DISCARD, counts egress frames discarded due to errors
0x10 0-63 VALUE New counter value; set to '0' to reset the counter
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-59
Command structure
Figure 109. DPNI_GET_LINK_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.35 DPNI_GET_LINK_STATE
Return the link state (either up or down).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x21A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 – RATE
63 0
0x18 OPTIONS
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-31 RATE Rate in Mbps
0x18 OPTIONS Mask of available options; use ‘DPNI_LINK_OPT_<x>’ values
1 DPNI_LINK_OPT_AUTONEG Enable auto-negotiation
2 DPNI_LINK_OPT_HALF_DUPLEX Enable half-duplex mode
3 DPNI_LINK_OPT_PAUSE Enable pause frames
4 DPNI_LINK_OPT_ASYM_PAUSE Enable a-symmetric pause frames
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-60
Command structure
Figure 110. DPNI_GET_LINK_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x215 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-61
Response structure
Figure 111. DPNI_GET_LINK_STATE Response Description
All unspecified fields are cleared.
7.3.36 DPNI_SET_TX_SHAPING
Set the transmit shaping
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x215 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 33 32 31 0
0x08 – UP –
63 32 31 0
0x10 – RATE
63 0
0x18 OPTIONS
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32 UP Link state; '1' if link is up, '0' otherwise
0x10 0-31 RATE Rate in Mbps
0x18 OPTIONS Mask of available options; use ‘DPNI_LINK_OPT_<x>’ values
1 DPNI_LINK_OPT_AUTONEG Enable auto-negotiation
2 DPNI_LINK_OPT_HALF_DUPLEX Enable half-duplex mode
3 DPNI_LINK_OPT_PAUSE Enable pause frames
4 DPNI_LINK_OPT_ASYM_PAUSE Enable a-symmetric pause frames
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-62
Command structure
Figure 112. DPNI_SET_TX_SHAPING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.37 DPNI_SET_MAX_FRAME_LENGTH
Set the maximum allowed length for received frames.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x21B – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – MAX_BURST_SIZE
63 32 31 0
0x10 RATE_LIMIT –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 MAX_BURST_SIZE Burst size in bytes (up to 64KB)
0x10 32-63 RATE_LIMIT Rate in Mbps
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-63
Command structure
Figure 113. DPNI_SET_MAX_FRAME_LENGTH Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.38 DPNI_GET_MAX_FRAME_LENGTH
Set the maximum allowed length for received frames.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x216 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – MAX_FRAME_LENGTH
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 MAX_FRAME_LENGTH Maximum received frame length (in bytes); a frame is discarded if its length exceeds this value.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-64
Command structure
Figure 114. DPNI_GET_MAX_FRAME_LENGTH Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x217 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-65
Response structure
Figure 115. DPNI_GET_MAX_FRAME_LENGTH Response Description
All unspecified fields are cleared.
7.3.39 DPNI_SET_MTU
Set the MTU (Maximum Transmission Unit) length for the interface. MTU determines the maximum fragment size for performing IP fragmentation on egress packets, therefore it is valid only when IP fragmentation is enabled.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x217 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – MAX_FRAME_LENGTH
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 MAX_FRAME_LENGTH Maximum received frame length (in bytes); a frame is discarded if its length exceeds this value.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-66
Command structure
Figure 116. DPNI_SET_MTU Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.40 DPNI_GET_MTU
Get the MTU length of the interface.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x218 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 MTU
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 MTU MTU length (in bytes)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-67
Command structure
Figure 117. DPNI_GET_MTU Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x219 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-68
Response structure
Figure 118. DPNI_GET_MTU Response Description
All unspecified fields are cleared.
7.3.41 DPNI_SET_MULTICAST_PROMISC
Enable/disable multicast promiscuous mode. In this mode, all multicast MAC addresses are accepted by the interface, and no multicast filtering is done.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x219 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – MTU
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 MTU MTU length (in bytes)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-69
Command structure
Figure 119. DPNI_SET_MULTICAST_PROMISC Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.42 DPNI_GET_MULTICAST_PROMISC
Get status of multicast promiscuous mode.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x220 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN ‘0’: disable multicast promiscuous mode‘1’: enable multicast promiscuous mode (default)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-70
Command structure
Figure 120. DPNI_GET_MULTICAST_PROMISC Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x221 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-71
Response structure
Figure 121. DPNI_GET_MULTICAST_PROMISC Response Description
All unspecified fields are cleared.
7.3.43 DPNI_SET_UNICAST_PROMISC
Enable/disable unicast promiscuous mode. In this mode, all unicast MAC addresses are accepted by the interface, and no unicast filtering is done.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x221 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN ‘0’: multicast promiscuous mode is disabled‘1’: multicast promiscuous mode is enabled
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-72
Command structure
Figure 122. DPNI_SET_UNICAST_PROMISC Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.44 DPNI_GET_UNICAST_PROMISC
Get status of unicast promiscuous mode.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x222 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN ‘0’: disable unicast promiscuous mode (default)‘1’: enable unicast promiscuous mode
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-73
Command structure
Figure 123. DPNI_GET_UNICAST_PROMISC Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x223 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-74
Response structure
Figure 124. DPNI_GET_UNICAST_PROMISC Response Description
All unspecified fields are cleared.
7.3.45 DPNI_SET_PRIMARY_MAC_ADDR
Set the primary MAC address of the interface.
The primary MAC address is initially set when the DPNI is created (see DPNI_CREATE command), and may be modified by this command. Each interface must have at least one primary MAC address defined, therefore this address can be modified but not removed. Additional MAC addresses can be assigned to the interface through MAC filtering commands.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x223 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN ‘0’: multicast promiscuous mode is disabled‘1’: multicast promiscuous mode is enabled
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-75
Command structure
Figure 125. DPNI_SET_PRIMARY_MAC_ADDR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.46 DPNI_GET_PRIMARY_MAC_ADDR
Get the primary MAC address.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x224 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-63 MAC_ADDR[0-5] MAC address (6 bytes) to set as primary address.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-76
Command structure
Figure 126. DPNI_GET_PRIMARY_MAC_ADDR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x225 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-77
Response structure
Figure 127. DPNI_GET_PRIMARY_MAC_ADDR Response Description
All unspecified fields are cleared.
7.3.47 DPNI_ADD_MAC_ADDR
Add MAC address filter. A successful invocation of this command configures the interface to accept frames with the specified destination MAC address.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x225 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 –
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-63 MAC_ADDR[0-5] MAC address (6 bytes) that serves as primary address.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-78
Command structure
Figure 128. DPNI_ADD_MAC_ADDR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.48 DPNI_REMOVE_MAC_ADDR
Remove MAC address filter. After a successful invocation of this command, frames with the specified MAC address are rejected by the interface (unless promiscuous mode is enabled).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x226 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-63 MAC_ADDR[0-5] MAC address to add
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-79
Command structure
Figure 129. DPNI_REMOVE_MAC_ADDR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.49 DPNI_CLEAR_MAC_FILTERS
Clear all unicast and/or multicast MAC filters. Note that the primary MAC address is never cleared – it stays valid at all times.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x227 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-63 ADDR[0-5] MAC address to remove
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-80
Command structure
Figure 130. DPNI_CLEAR_MAC_FILTERS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.50 DPNI_SET_VLAN_FILTERS
Enable/disable VLAN filtering mode.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x228 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
MU
LTIC
AS
T
UN
ICA
ST
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 UNICAST Set to '1' to clear unicast addresses
1 MULTICAST Set to '1' to clear multicast addresses
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-81
Command structure
Figure 131. DPNI_SET_VLAN_FILTERS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.51 DPNI_ADD_VLAN_ID
Add VLAN ID filter. A successful invocation of this command configures the interface to accept frames with the specified VLAN ID (assuming they are not dropped by the MAC filters).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x230 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN ‘0’: disable VLAN filtering‘1’: enable VLAN filtering
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-82
Command structure
Figure 132. DPNI_ADD_VLAN_ID Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.52 DPNI_REMOVE_VLAN_ID
Remove VLAN filter. After a successful invocation of this command, frames with the specified VLAN ID are rejected by the interface.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x231 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – VLAN_ID
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 VLAN_ID VLAN ID to add
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-83
Command structure
Figure 133. DPNI_REMOVE_VLAN_ID Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.53 DPNI_CLEAR_VLAN_FILTERS
Clear all VLAN filters of the interface.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x232 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 0
0x08 – VLAN_ID
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 VLAN_ID VLAN ID to remove
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-84
Command structure
Figure 134. DPNI_CLEAR_VLAN_FILTERS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.54 DPNI_SET_TX_SELECTION
Set transmission selection configuration
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x233 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-85
Command structure
Figure 135. DPNI_SET_TX_SELECTION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.55 DPNI_SET_RX_TC_DIST
Set the receive-side traffic class configuration.
This command may be used to configure any traffic class out of the maximum number of traffic classes selected during the creation of the DPNI. It determines the distribution mode and size for the traffic class; it also specifies the distribution key, by specifying up to eight configurable extractions from the frame’s headers and/or payload. The maximum size for the distribution key is limited by the MAX_DIST_KEY_SIZE value set at DPNI creation.
Distribution functionality is valid only if the DPNI_OPT_DIST_FS and/or DPNI_OPT_DIST_HASH options were set at DPNI creation; otherwise, each traffic class has exactly (and only) one flow. Refer to
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x250 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 32 31 16 15 0
0x08 TC_SCHED_1_MODE TC_SCHED_1_DELTA_BANDWIDTH
TC_SCHED_0_MODE TC_SCHED_0_DELTA_BANDWIDTH
63 48 47 32 31 16 15 0
0x10 TC_SCHED_3_MODE TC_SCHED_3_DELTA_BANDWIDTH
TC_SCHED_2_MODE TC_SCHED_2_DELTA_BANDWIDTH
63 48 47 32 31 16 15 0
0x18 TC_SCHED_5_MODE TC_SCHED_5_DELTA_BANDWIDTH
TC_SCHED_4_MODE TC_SCHED_4_DELTA_BANDWIDTH
63 48 47 32 31 16 15 0
0x20 TC_SCHED_7_MODE TC_SCHED_7_DELTA_BANDWIDTH
TC_SCHED_6_MODE TC_SCHED_6_DELTA_BANDWIDTH
63 0
0x28 –
63 0
0x30 –
63 0
0x38
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 - 0x20
0-15/ 32-47
TC_SCHED[0..7]_DELTA_BANDWIDTH Bandwidth representing transmission selection configuration
16-31/48-63
TC_SCHED_[0..7]_MODE Scheduling mode
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-86
the DPNI_CREATE for description of these options and also for DPNI_DIST_SIZE_TC0..7, which defines the maximum distribution size per traffic class.
Command structure
Figure 136. DPNI_SET_RX_TC_DIST Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x235 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 32 31 28 27 24 23 16 15 0
0x08 DEFAULT_FLOW_ID –
MIS
S_A
CT
ION
DIS
T_M
OD
E
TC_ID DIST_SIZE
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 KEY_CFG_IOVA
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-87
All unspecified fields are reserved and must be cleared (set to zero)
0x08 0-15 DIST_SIZE Set the distribution size; supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,112,128,192,224,256,384,448,512,768,896,1024.Note that high values may be unsupported due to limited queue resources in the system.
16-23 TC_ID Traffic class to configure; valid values are in the range of (0-7), but also limited by the maximum number of traffic classes configured during the creation of the DPNI.
24-27 DIST_MODE Distribution mode:
0: DPNI_DIST_MODE_NONE – no distribution1: DPNI_DIST_MODE_HASH – use hash distribution; only relevant if the 'DPNI_OPT_DIST_HASH' option was set at DPNI creation.2: DPNI_DIST_MODE_FS – use explicit flow steering; only relevant if the 'DPNI_OPT_DIST_FS' option was set at DPNI creation
28-31 MISS_ACTION For DIST_MODE = DPNI_DIST_MODE_FS: determine the fall-back action for no-match scenario.
0: DPNI_FS_MISS_DROP – in case of no-match, drop the frame1: DPNI_FS_MISS_EXPLICIT_FLOWID – in case of no-match, use the flow ID specified in DEFAULT_FLOW_ID2: DPNI_FS_MISS_HASH – in case of no-match, distribute using hash value
48-63 DEFAULT_FLOW_ID For DIST_MODE = DPNI_DIST_MODE_FS and MISS_ACTION = DPNI_FS_MISS_EXPLICIT_FLOWID: specifies the default flow ID in case of no-match scenario.
0x38 0-63 KEY_CFG_IOVA I/O virtual address of zeroed 256 bytes of DMA-able memory. This extended buffer must be programmed as specified in the “Extension structure” section below, to hold the distribution key configuration.Ignored if DIST_MODE = DPNI_DIST_MODE_NONE.
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-88
Extension structure
Figure 137. DPNI_SET_RX_TC_DIST Extension Description
Offset from Management Command Portal base Read-Write Access
63 8 7 0
0x00 – NUM_EXTRACTS
63 32 31 24 23 16 15 12 11 8 7 0
0x08 FIELD OFFSET SIZE –
EF
H_T
YP
E
PROT
63 36 35 32 31 24 23 16 15 8 7 0
0x10 –
EX
TR
AC
T_T
YP
E
NUM_OF_BYTE_MASKS
NUM_OF_REPEATS
CONSTANT HDR_INDEX
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 MASK3_OFFSET MASK3_MASK MASK2_OFFSET MASK2_MASK MASK1_OFFSET MASK1_MASK MASK0_OFFSET MASK0_MASK
0x20 - 0xC7
Repeating (9 more sections) of the extraction fields in offsets (0x08 - 0x1F) above.NUM_EXTRACTS determines the number of valid extraction sections up to the 10 possible.
Offset Bits Name Description
0x00 0-7 NUM_EXTRACTS Number of valid extractions out of the 10 possible; determines how many of the EXTRACT0..9 below are valid. Value of 0 is invalid.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-89
0x08 0-7 EXTRACT0 PROT For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: specify any of the supported headers:
8-11 EFH_TYPE For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: specify the type of extraction from header (and determines validity of the next 3 parameters):0: DPKG_FROM_HDR – SIZE and OFFSET are valid; SIZE bytes are extracted from OFFSET relative to the start of the specified header (PROT).1: DPKG_FROM_FIELD – FIELD, SIZE and OFFSET are valid; SIZE bytes are extracted from OFFSET relative to the start of the specified FIELD.2: DPKG_FULL_FIELD – only FIELD is valid; specified FIELD is fully extracted.
16-23 SIZE Size (in bytes) of the extraction
42-31 OFFSET Byte offset of starting point of the extraction
32-63 FIELD For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: standard field selection for the extraction
0x10 0-7 HDR_INDEX For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: indicates the PROT header index for protocols that may appear more than once within a frame (examples: VLAN, MPLS, IP).0x00 indicates the most outer (first) header.0xFF indicates the most inner (last) header.
8-15 CONSTANT For EXTRACT_TYPE = DPKG_EXTRACT_CONSTANT: the constant value to extract (one byte)
16-23 NUM_OF_REPEATS For EXTRACT_TYPE = DPKG_EXTRACT_CONSTANT: number of times to repeat the extraction of the constant value (values are placed in the key in adjacent manner)
24-31 NUM_OF_BYTE_MASKS Determines the number of valid entries of MASKn_MASK and MASKn_OFFSET.Up to four byte masks are available to apply on the extracted content (each mask is 1 byte in size).Note, that byte masks are valid for any selection of EXTRACT_TYPE.
32-35 EXTRACT_TYPE Determines the type of extraction:
0: DPKG_EXTRACT_FROM_HDR – extract from the frame header; the following fields are considered valid in this case:PROT, EFH_TYPE, SIZE, OFFSET, FIELD, HDR_INDEX
1: DPKG_EXTRACT_FROM_DATA – extract from data not in the header; the following fields are considered valid in this case:SIZE, OFFSET
2: DPKG_EXTRACT_CONSTANT – extract user-selected constant values; the following fields are considered valid in this case:CONSTANT, NUM_OF_REPEATS
0x18 0-7 MASK0_MASK Byte mask to apply on the extracted content at offset MASK0_OFFSET
8-15 MASK0_OFFSET Offset (relative to the first byte of extracted content) for applying MASK0_MASK
16-23 MASK1_MASK Byte mask to apply on the extracted content at offset MASK1_OFFSET
24-31 MASK1_OFFSET Offset (relative to the first byte of extracted content) for applying MASK1_MASK
32-39 MASK2_MASK Byte mask to apply on the extracted content at offset MASK2_OFFSET
40-47 MASK2_OFFSET Offset (relative to the first byte of extracted content) for applying MASK2_MASK
48-55 MASK3_MASK Byte mask to apply on the extracted content at offset MASK3_OFFSET
56-63 MASK3_OFFSET Offset (relative to the first byte of extracted content) for applying MASK3_MASK
0x20 - 0x37
EXTRACT1 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 2
0x38 - 0x4F
EXTRACT2 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 3
0x50 - 0x67
EXTRACT3 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 4
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-90
All unspecified fields are reserved and must be cleared (set to zero)
7.3.56 DPNI_SET_RX_TC_POLICING
Set Rx traffic class policing configuration
0x68 - 0x7F
EXTRACT4 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 5
0x80 - 0x97
EXTRACT5 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 6
0x98 - 0xAF
EXTRACT6 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 7
0xB0 - 0xC7
EXTRACT7 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 8
0xC8 - 0xDF
EXTRACT8 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 9
0xE0 - 0xF7
EXTRACT9 Similar to EXTRACT0; valid if NUM_EXTRACTS = 10
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-91
Command structure
Figure 138. DPNI_SET_RX_TC_POLICING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x23E – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 24 23 16 15 12 11 8 7 4 3 0
0x08 OPTIONS – TC_ID –
UNITS
DE
FAU
LT_C
OLO
R
MODE
63 32 31 0
0x10 CBS CIR
63 32 31 0
0x18 EBS EIR
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 0-3 MODE Policer mode
0x10 4-7 DEFAULT_COLOR For pass-through mode the policer re-colors with this color any incoming packets. For Color aware non-pass-through mode: policer re-colors with this color all packets with FD[DROPP]>2.
8-11 UNITS Bytes or Packets
16-23 TC_ID Traffic class ID
32-63 OPTIONS Mask of available options; use ‘DPNI_POLICER_OPT_<x>’ values
0x18 0-31 CIR Committed information rate (CIR) in Kbps or packets/second
32-63 CBS Committed burst size (CBS) in bytes or packets
0x20 0-31 EIR Peak information rate (PIR, rfc2698) in Kbps or packets/second. Excess information rate (EIR, rfc4115) in Kbps or packets/second
32-63 EBS Peak burst size (PBS, rfc2698) in bytes or packetsExcess burst size (EBS, rfc4115) in bytes or packets
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-92
7.3.57 DPNI_GET_RX_TC_POLICING
Get Rx traffic class policing configuration
Command structure
Figure 139. DPNI_GET_RX_TC_POLICING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x251 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 0
0x08 – TC_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID Traffic class ID
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-93
Response structure
Figure 140. DPNI_GET_RX_TC_POLICING Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x251 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 12 11 8 7 4 3 0
0x08 OPTIONS –
UNITS
DE
FAU
LT_C
OLO
R
MODE
63 32 31 0
0x10 CBS CIR
63 32 31 0
0x18 EBS EIR
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-3 MODE Policer mode
4-7 DEFAULT_COLOR For pass-through mode the policer re-colors with this color any incoming packets. For Color aware non-pass-through mode: policer re-colors with this color all packets with FD[DROPP]>2.
8-11 UNITS Bytes or packets
32-63 OPTIONS Mask of available options; use 'DPNI_POLICER_OPT_<X>' values
0x10 0-31 CIR Committed information rate (CIR) in Kbps or packets/second
32-63 CBS Committed burst size (CBS) in bytes or packets
0x18 0-31 EIR Peak information rate (PIR, rfc2698) in Kbps or packets/second Excess information rate (EIR, rfc4115) in Kbps or packets/second
32-63 EBS Peak burst size (PBS, rfc2698) in bytes or packetsExcess burst size (EBS, rfc4115) in bytes or packets
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-94
7.3.58 DPNI_SET_RX_TC_EARLY_DROP
Set Rx traffic class policing configuration
Command structure
Figure 141. DPNI_SET_RX_TC_EARLY_DROP Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x23E – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 0
0x08 – TC_ID –
63 0
0x10 EARLY_DROP_IOVA
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID Traffic class ID
0x10 0-63 EARLY_DROP_IOVA I/O virtual address of 64 bytes;Must be cacheline-aligned and DMA-able memory
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-95
Extension structure
Figure 142. DPNI_SET_RX_TC_EARLY_DROP Command Description
Offset from Management Command Portal base Read-Write Access
63 32 31 4 3 - 2 1 -0
0x00 TAIL_DROP_THRESHOLD –
UN
ITS
MO
DE
63 8 7 0
0x08 – GREEN_DROP_PROBABILITY
63 0
0x10 GREEN_MAX_THRESHOLD
63 0
0x18 GREEN_MIN_THRESHOLD
63 8 7 0
0x20 – YELLOW_DROP_PROBABILITY
63 0
0x28 YELLOW_MAX_THRESHOLD
63 0
0x30 YELLOW_MIN_THRESHOLD
63 8 7 0
0x38 – RED_DROP_PROBABILITY
63 0
0x40 RED_MAX_THRESHOLD
63 0
0x48 RED_MIN_THRESHOLD
Offset Bits Name Description
0x00 0-1 MODE Drop mode
2-3 UNITS Units type
0x08 0-7 GREEN_DROP_PROBABILITY probability of green WRED that a packet will be discarded (1-100, associated with the max_threshold).
0x10 0-63 GREEN_MAX_THRESHOLD maximum threshold of green WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 GREEN_MIN_THRESHOLD minimum threshold of green WRED that packets may be discarded at
0x08 0-7 YELLOW_DROP_PROBABILITY probability of yellow WRED that a packet will be discarded (1-100, associated with the max_threshold).
0x10 0-63 YELLOW_MAX_THRESHOLD maximum threshold of yellow WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 YELLOW_MIN_THRESHOLD minimum threshold of yellow WRED that packets may be discarded at
0x08 0-7 RED_DROP_PROBABILITY probability of red WRED that a packet will be discarded (1-100, associated with the max_threshold).
0x10 0-63 RED_MAX_THRESHOLD maximum threshold of red WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 RED_MIN_THRESHOLD minimum threshold of red WRED that packets may be discarded at
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-96
All unspecified fields are reserved and must be cleared (set to zero)
7.3.59 DPNI_GET_RX_TC_EARLY_DROP
Set Rx traffic class policing configuration
Command structure
Figure 143. DPNI_GET_RX_TC_EARLY_DROP Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x252 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 0
0x08 – TC_ID –
63 0
0x10 EARLY_DROP_IOVA
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID Traffic class ID
0x10 0-63 EARLY_DROP_IOVA I/O virtual address of 64 bytes;Must be cache-line aligned and DMA-able memory
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-97
Extension structure
Figure 144. DPNI_GET_RX_TC_EARLY_DROP Extension Description
Offset from Management Command Portal base Read-Write Access
63 32 31 4 3 - 2 1 -0
0x00 TAIL_DROP_THRESHOLD –
UN
ITS
MO
DE
63 8 7 0
0x08 – GREEN_DROP_PROBABILITY
63 0
0x10 GREEN_MAX_THRESHOLD
63 0
0x18 GREEN_MIN_THRESHOLD
63 8 7 0
0x20 – YELLOW_DROP_PROBABILITY
63 0
0x28 YELLOW_MAX_THRESHOLD
63 0
0x30 YELLOW_MIN_THRESHOLD
63 8 7 0
0x38 – RED_DROP_PROBABILITY
63 0
0x40 RED_MAX_THRESHOLD
63 0
0x48 RED_MIN_THRESHOLD
Offset Bits Name Description
0x00 0-1 MODE Drop mode
2-3 UNITS Units type
0x08 0-7 GREEN_DROP_PROBABILITY probability of green WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 GREEN_MAX_THRESHOLD maximum threshold of green WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 GREEN_MIN_THRESHOLD minimum threshold of green WRED that packets may be discarded at
0x08 0-7 YELLOW_DROP_PROBABILITY probability of yellow WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 YELLOW_MAX_THRESHOLD maximum threshold of yellow WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 YELLOW_MIN_THRESHOLD minimum threshold of yellow WRED that packets may be discarded at
0x08 0-7 RED_DROP_PROBABILITY probability of red WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 RED_MAX_THRESHOLD maximum threshold of red WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 RED_MIN_THRESHOLD minimum threshold of red WRED that packets may be discarded at
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-98
All unspecified fields are reserved and must be cleared (set to zero)
7.3.60 DPNI_SET_TX_TC_EARLY_DROP
Set Rx traffic class policing configuration
Command structure
Figure 145. DPNI_SET_TX_TC_EARLY_DROP Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x25B – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 0
0x08 – TC_ID –
63 0
0x10 EARLY_DROP_IOVA
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID Traffic class ID
0x10 0-63 EARLY_DROP_IOVA I/O virtual address of 64 bytes;Must be cache-line aligned and DMA-able memory
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-99
Extension structure
Figure 146. DPNI_SET_TX_TC_EARLY_DROP Extension Description
Offset from Management Command Portal base Read-Write Access
63 32 31 4 3 - 2 1 -0
0x00 TAIL_DROP_THRESHOLD –
UN
ITS
MO
DE
63 8 7 0
0x08 – GREEN_DROP_PROBABILITY
63 0
0x10 GREEN_MAX_THRESHOLD
63 0
0x18 GREEN_MIN_THRESHOLD
63 8 7 0
0x20 – YELLOW_DROP_PROBABILITY
63 0
0x28 YELLOW_MAX_THRESHOLD
63 0
0x30 YELLOW_MIN_THRESHOLD
63 8 7 0
0x38 – RED_DROP_PROBABILITY
63 0
0x40 RED_MAX_THRESHOLD
63 0
0x48 RED_MIN_THRESHOLD
Offset Bits Name Description
0x00 0-1 MODE Drop mode
2-3 UNITS Units type
0x08 0-7 GREEN_DROP_PROBABILITY probability of green WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 GREEN_MAX_THRESHOLD maximum threshold of green WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 GREEN_MIN_THRESHOLD minimum threshold of green WRED that packets may be discarded at
0x08 0-7 YELLOW_DROP_PROBABILITY probability of yellow WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 YELLOW_MAX_THRESHOLD maximum threshold of yellow WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 YELLOW_MIN_THRESHOLD minimum threshold of yellow WRED that packets may be discarded at
0x08 0-7 RED_DROP_PROBABILITY probability of red WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 RED_MAX_THRESHOLD maximum threshold of red WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 RED_MIN_THRESHOLD minimum threshold of red WRED that packets may be discarded at
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-100
All unspecified fields are reserved and must be cleared (set to zero)
7.3.61 DPNI_GET_TX_TC_EARLY_DROP
Set Rx traffic class policing configuration
Command structure
Figure 147. DPNI_GET_TX_TC_EARLY_DROP Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x25C – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 0
0x08 – TC_ID –
63 0
0x10 EARLY_DROP_IOVA
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID Traffic class ID
0x10 0-63 EARLY_DROP_IOVA I/O virtual address of 64 bytes;Must be cache-line aligned and DMA-able memory
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-101
Extension structure
Figure 148. DPNI_GET_TX_TC_EARLY_DROP Extension Description
Offset from Management Command Portal base Read-Write Access
63 32 31 4 3 - 2 1 -0
0x00 TAIL_DROP_THRESHOLD –
UN
ITS
MO
DE
63 8 7 0
0x08 – GREEN_DROP_PROBABILITY
63 0
0x10 GREEN_MAX_THRESHOLD
63 0
0x18 GREEN_MIN_THRESHOLD
63 8 7 0
0x20 – YELLOW_DROP_PROBABILITY
63 0
0x28 YELLOW_MAX_THRESHOLD
63 0
0x30 YELLOW_MIN_THRESHOLD
63 8 7 0
0x38 – RED_DROP_PROBABILITY
63 0
0x40 RED_MAX_THRESHOLD
63 0
0x48 RED_MIN_THRESHOLD
Offset Bits Name Description
0x00 0-1 MODE Drop mode
2-3 UNITS Units type
0x08 0-7 GREEN_DROP_PROBABILITY probability of green WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 GREEN_MAX_THRESHOLD maximum threshold of green WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 GREEN_MIN_THRESHOLD minimum threshold of green WRED that packets may be discarded at
0x08 0-7 YELLOW_DROP_PROBABILITY probability of yellow WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 YELLOW_MAX_THRESHOLD maximum threshold of yellow WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 YELLOW_MIN_THRESHOLD minimum threshold of yellow WRED that packets may be discarded at
0x08 0-7 RED_DROP_PROBABILITY probability of red WRED that a packet will be discarded (1-100, associated with the MAX_THRESHOLD).
0x10 0-63 RED_MAX_THRESHOLD maximum threshold of red WRED that packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 RED_MIN_THRESHOLD minimum threshold of red WRED that packets may be discarded at
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-102
All unspecified fields are reserved and must be cleared (set to zero)
7.3.62 DPNI_SET_RX_TC_CONGESTION_NOTIFICATION
Set Rx traffic class congestion notification configuration
Command structure
Figure 149. DPNI_SET_RX_TC_CONGESTION_NOTIFICATION Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x253 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 7 4 1-0
0x08 – PRIORITY TC_ID DEST_TYPE
–
UN
ITS
63 0
0x10 THRESHOLD_EXIT THRESHOLD_ENTRY
63 32 31 0
0x18 DEST_ID OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-1 UNITS Congestion units:0: DPNI_CONGESTION_UNIT_BYTES – congestion measured by byte count1: DPNI_CONGESTION_UNIT_FRAMES– congestion measured by frame count
4-7 DEST_TYPE Selects the destination for the congestion state change notification (CSCN) messages:
0: DPNI_DEST_NONE – no congestion state change notification messages.1: DPNI_DEST_DPIO – congestion notifications are sent to a DPIO notifications channel (DPIO object ID must be specified in DEST_ID).2: DPNI_DEST_DPCON – congestion notifications are sent to a DPCON channel (DPCON object ID must be specified in DEST_ID).
8-15 TC_ID Traffic class ID, selects the traffic class to configure
16-23 PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPNI_DEST_NONE' option
0x10 0-31 THRESHOLD_ENTRY Congestion state is entered above this threshold (according to selected units); set to '0' to disable
32-63 THRESHOLD_EXIT Congestion state is exited below this threshold (according to selected units)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-103
All unspecified fields are reserved and must be cleared (set to zero)
7.3.63 DPNI_GET_RX_TC_CONGESTION_NOTIFICATION
Get Rx traffic class congestion notification configuration
0x18 0-31 OPTIONS Options for congestion notifications:
Bit 0: DPNI_CONG_OPT_WRITE_MEM_ON_ENTER – CSCN message is written to MESSAGE_IOVA once entering a congestion state (see THRESHOLD_ENTRY).
Bit 1: DPNI_CONG_OPT_WRITE_MEM_ON_EXIT – CSCN message is written to MESSAGE_IOVA once exiting a congestion state (see THRESHOLD_EXIT).
Bit 2: DPNI_CONG_OPT_COHERENT_WRITE – CSCN write attempts to allocate into a cache (coherent write); valid only if 'DPNI_CONG_OPT_WRITE_MEM_ON_ENTER/EXIT' are selected.
Bit 4: DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER – when DEST_TYPE is not ‘DPNI_DEST_NONE', CSCN message is sent to the DPIO’s or DPCON's channel once entering a congestion state (see THRESHOLD_ENTRY).
Bit 5: DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT – when DEST_TYPE is not ‘DPNI_DEST_NONE', CSCN message is sent to the DPIO’s or DPCON's channel once exiting a congestion state (see THRESHOLD_EXIT).
Bit 6: DPNI_CONG_OPT_INTR_COALESCING_DISABLED – when DEST_TYPE is not ‘DPNI_DEST_NONE', the DQRI interrupt is asserted immediately (if enabled) when the CSCN is written to the software portal’s DQRR.
32-63 DEST_ID Either DPIO ID or DPCON ID, depending on DEST_TYPE selection; not relevant for 'DPNI_DEST_NONE' option
0x20 0-63 MESSAGE_CTX User’s context to be provided as part of the CSCN message
0x28 0-63 MESSAGE_IOVA I/O virtual address (must be in DMA-able memory and 16B aligned) for writing CSCN messages to memory; valid only when 'DPNI_CONG_OPT_WRITE_MEM_ENTER/EXIT' are selected in ‘OPTIONS’
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-104
Command structure
Figure 150. DPNI_GET_RX_TC_CONGESTION_NOTIFICATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x254 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 8 7 0
0x08 – TC_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 8-15 TC_ID Traffic class ID
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-105
Response structure
Figure 151. DPNI_GET_RX_TC_CONGESTION_NOTIFICATION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.64 DPNI_SET_TX_TC_CONGESTION_NOTIFICATION
Set Tx traffic class congestion notification configuration
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x254 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 7 4 1-0
0x08 – PRIORITY – DEST_TYPE
–
UN
ITS
63 0
0x10 THRESHOLD_EXIT THRESHOLD_ENTRY
63 32 31 0
0x18 DEST_ID OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-1 UNITS Refer to DPNI_SET_RX_TC_CONGESTION_NOTIFICATION for description of these fields.
4-7 DEST_TYPE
16-23 PRIORITY
0x10 0-31 THRESHOLD_ENTRY
32-63 THRESHOLD_EXIT
0x18 0-31 OPTIONS
32-63 DEST_ID
0x20 0-63 MESSAGE_CTX
0x28 0-63 MESSAGE_IOVA
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-106
Command structure
Figure 152. DPNI_SET_TX_TC_CONGESTION_NOTIFICATION Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x255 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 7 4 1-0
0x08 – PRIORITY TC_ID DEST_TYPE
–
UN
ITS
63 0
0x10 THRESHOLD_EXIT THRESHOLD_ENTRY
63 32 31 0
0x18 DEST_ID OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-1 UNITS Congestion units:0: DPNI_CONGESTION_UNIT_BYTES – congestion measured by byte count1: DPNI_CONGESTION_UNIT_FRAMES– congestion measured by frame count
4-7 DEST_TYPE Selects the destination for the congestion state change notification (CSCN) messages:
0: DPNI_DEST_NONE – no congestion state change notification messages.1: DPNI_DEST_DPIO – congestion notifications are sent to a DPIO notifications channel (DPIO object ID must be specified in DEST_ID).2: DPNI_DEST_DPCON – congestion notifications are sent to a DPCON channel (DPCON object ID must be specified in DEST_ID).
8-15 TC_ID Traffic class ID, selects the traffic class to configure
16-23 PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPNI_DEST_NONE' option
0x10 0-31 THRESHOLD_ENTRY Congestion state is entered above this threshold (according to selected units); set to '0' to disable
32-63 THRESHOLD_EXIT Congestion state is exited below this threshold (according to selected units)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-107
All unspecified fields are reserved and must be cleared (set to zero)
7.3.65 DPNI_GET_TX_TC_CONGESTION_NOTIFICATION
Get Tx traffic class congestion notification configuration
0x18 0-31 OPTIONS Options for congestion notifications:
Bit 0: DPNI_CONG_OPT_WRITE_MEM_ON_ENTER – CSCN message is written to MESSAGE_IOVA once entering a congestion state (see THRESHOLD_ENTRY).
Bit 1: DPNI_CONG_OPT_WRITE_MEM_ON_EXIT – CSCN message is written to MESSAGE_IOVA once exiting a congestion state (see THRESHOLD_EXIT).
Bit 2: DPNI_CONG_OPT_COHERENT_WRITE – CSCN write attempts to allocate into a cache (coherent write); valid only if 'DPNI_CONG_OPT_WRITE_MEM_ON_ENTER/EXIT' are selected.
Bit 4: DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER – when DEST_TYPE is not ‘DPNI_DEST_NONE', CSCN message is sent to the DPIO’s or DPCON's channel once entering a congestion state (see THRESHOLD_ENTRY).
Bit 5: DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT – when DEST_TYPE is not ‘DPNI_DEST_NONE', CSCN message is sent to the DPIO’s or DPCON's channel once exiting a congestion state (see THRESHOLD_EXIT).
Bit 6: DPNI_CONG_OPT_INTR_COALESCING_DISABLED – when DEST_TYPE is not ‘DPNI_DEST_NONE', the DQRI interrupt is asserted immediately (if enabled) when the CSCN is written to the software portal’s DQRR.
32-63 DEST_ID Either DPIO ID or DPCON ID, depending on DEST_TYPE selection; not relevant for 'DPNI_DEST_NONE' option
0x20 0-63 MESSAGE_CTX User’s context to be provided as part of the CSCN message
0x28 0-63 MESSAGE_IOVA I/O virtual address (must be in DMA-able memory and 16B aligned) for writing CSCN messages to memory; valid only when 'DPNI_CONG_OPT_WRITE_MEM_ENTER/EXIT' are selected in ‘OPTIONS’
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-108
Command structure
Figure 153. DPNI_GET_TX_TC_CONGESTION_NOTIFICATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x256 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 16 15 8 7 0
0x08 – TC_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 8-15 TC_ID Traffic class ID
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-109
Response structure
Figure 154. DPNI_GET_TX_TC_CONGESTION_NOTIFICATION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.66 DPNI_SET_TX_CONF
Set Tx confirmation and error queue configuration
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x256 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 7 4 1-0
0x08 – PRIORITY – DEST_TYPE
–
UN
ITS
63 0
0x10 THRESHOLD_EXIT THRESHOLD_ENTRY
63 32 31 0
0x18 DEST_ID OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-1 UNITS Refer to DPNI_SET_TX_TC_CONGESTION_NOTIFICATION for description of these fields.
4-7 DEST_TYPE
16-23 PRIORITY
0x10 0-31 THRESHOLD_ENTRY
32-63 THRESHOLD_EXIT
0x18 0-31 OPTIONS
32-63 DEST_ID
0x20 0-63 MESSAGE_CTX
0x28 0-63 MESSAGE_IOVA
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-110
Command structure
Figure 155. DPNI_SET_TX_CONF Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x257 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 46 43-
45
42 40-
41
39 32 31 0
0x08 FLOW_ID –
OP
E
–
ER
RO
RS
_ON
LY
DE
ST
_TY
PE
PRIORITY –
63 0
0x10 USER_CTX
63 32 31 0
0x18 DEST_ID QUEUE_OPTIONS
63 32 31 0
0x20 – TAIL_DROP_THRESHOLD
63 12 11 8 7 4 3 0
0x28 FLC_OPTIONS – FLOW_CONTEXT_SIZ
E
FRAME_DATA_
SIZE
FLC_TYPE
63 0
0x30 FLOW_CONTEXT
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPNI_DEST_NONE' option
40-41 DEST_TYPE Selects the destination for the Tx confirmation queue:
0: DPNI_DEST_NONE – unassigned destination; the queue is set in parked mode and does not generate FQDAN notifications; user is expected to dequeue from the queue based on polling or other user-defined method.1: DPNI_DEST_DPIO – the queue is set in scheduled mode and generates FQDAN notifications to the specified DPIO; user is expected to dequeue from the queue only after notification is received.2: DPNI_DEST_DPCON – the queue is set in scheduled mode; the queue does not generate FQDAN notifications, but is rather connected to the specified DPCON object; user is expected to dequeue from the DPCON channel.
Valid only if DPNI_QUEUE_OPT_DEST is set in QUEUE_OPTIONS.
42 ERRORS_ONLY 0: Confirm all transmitted frames (both successful and failed transmissions)1: Confirm only errors (failed transmissions)
46 ORDER_PRESERVATION_EN (OPE) Enable order preservation; valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained in 'QUEUE_OPTIONS'
48-63 FLOW_ID The sender's flow ID to configure, as returned by DPNI_SET_TX_FLOW command; use 'DPNI_COMMON_TX_CONF' for configuring the common Tx confirmation queue.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-111
All unspecified fields are reserved and must be cleared (set to zero)
7.3.67 DPNI_GET_TX_CONF
Get Tx confirmation and error queue attributes
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' is contained in 'QUEUE_OPTIONS'
0x18 0-31 QUEUE_OPTIONS Option bits selecting the requested modifications to the transmit flow:
Bit 0: DPNI_QUEUE_OPT_USER_CTX – Set to modify the user's context associated with the queue to the value in USER_CTX.Bit 1:.DPNI_QUEUE_OPT_DEST – Set to modify the queue’s destination according to DEST_TYPE.Bit 3: DPNI_QUEUE_OPT_ORDER_PRESERVATION – Set to modify the queue’s order preservation mode, according to ORDER_PRESERVATION_EN field.Bit 4: DPNI_QUEUE_OPT_TAILDROP_THRESHOLD – Set to modify the queue’s tail-drop threshold, according to TAIL_DROP_THRESHOLD field.
32-63 DEST_ID Either DPIO ID or DPCON ID, depending on DEST_TYPE configuration
0x20 0-31 TAIL_DROP_THRESHOLD Set the queue's tail drop threshold in bytes;'0' disables the threshold; maximum value is 0xE000000;valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is selected in 'QUEUE_OPTIONS'
0x28 0-3 FLC_TYPE Flow context type:‘DPNI_FLC_USER_DEFINED’ – flow context is a user-defined value‘DPNI_FLC_STASH’ – flow context is an I/O virtual address of memory to be stashed.
4-7 FRAME_DATA_SIZE Size of frame data to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
8-11 FLOW_CONTEXT_SIZE Size of flow context to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
32-63 FLC_OPTIONS Option bits for the flow context;
Bit : DPNI_FLC_STASH_FRAME_ANNOTATION – stash the frame annotation area (up to 192 bytes)
0x30 0-63 FLOW_CONTEXT If ‘FLC_TYPE’ = 'DPNI_FLC_USER_DEFINED', this value is provided in the dequeued frame descriptor (FD[FLC]).If ‘FLC_TYPE’ = 'DPNI_FLC_STASH', this value is the I/O virtual address of the user’s flow context that should be stashed; Must be cache-line aligned and DMA-able memory. The size of stashed memory is taken from FLOW_CONTEXT_SIZE.
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-112
Command structure
Figure 156. DPNI_GET_TX_CONF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x258 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 0
0x08 FLOW_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 48-63 FLOW_ID The sender's flow ID to query, as returned by DPNI_SET_TX_FLOW command; use 'DPNI_COMMON_TX_CONF' for retrieve the common Tx confirmation queue configuration.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-113
Response structure
Figure 157. DPNI_GET_TX_CONF Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x258 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 47 46 43-
45
42 40-
41
39 32 31 0
0x08 –
OP
E
–
ER
RO
RS
_ON
LY
DE
ST
_TY
PE
PRIORITY –
63 0
0x10 USER_CTX
63 32 31 0
0x18 DEST_ID QUEUE_OPTIONS
63 32 31 0
0x20 – TAIL_DROP_THRESHOLD
63 12 11 8 7 4 3 0
0x28 FLC_OPTIONS – FLOW_CONTEXT_SIZ
E
FRAME_DATA_
SIZE
FLC_TYPE
63 0
0x30 FLOW_CONTEXT
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 PRIORITY Refer to DPNI_SET_TX_CONF for description of these fields.
40-41 DEST_TYPE
42 ERRORS_ONLY
46 ORDER_PRESERVATION_EN (OPE)
0x10 0-63 USER_CTX
0x18 0-31 QUEUE_OPTIONS
32-63 DEST_ID
0x20 0-31 TAIL_DROP_THRESHOLD
0x28 0-3 FLC_TYPE
4-7 FRAME_DATA_SIZE
8-11 FLOW_CONTEXT_SIZE
32-63 FLC_OPTIONS
0x30 0-63 FLOW_CONTEXT
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-114
All unspecified fields are reserved and must be cleared (set to zero)
7.3.68 DPNI_SET_TX_CONF_CONGESTION_NOTIFICATION
Set Tx conf congestion notification configuration
Command structure
Figure 158. DPNI_SET_TX_CONF_CONGESTION_NOTIFICATION Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x259 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 24 23 16 15 8 7 4 2-3 0-1
0x08 FLOW_ID – PRIORITY – DEST_
TYPE
–
UN
ITS
63 32 31 0
0x10 THRESHOLD_EXIT THRESHOLD_ENTRY
63 32 31 0
0x18 DEST_ID OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-1 UNITS Congestion units:0: DPNI_CONGESTION_UNIT_BYTES – congestion measured by byte count1: DPNI_CONGESTION_UNIT_FRAMES– congestion measured by frame count
4-7 DEST_TYPE Selects the destination for the congestion state change notification (CSCN) messages:
0: DPNI_DEST_NONE – no congestion state change notification messages.1: DPNI_DEST_DPIO – congestion notifications are sent to a DPIO notifications channel (DPIO object ID must be specified in DEST_ID).2: DPNI_DEST_DPCON – congestion notifications are sent to a DPCON channel (DPCON object ID must be specified in DEST_ID).
16-23 PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPNI_DEST_NONE' option
48-63 FLOW_ID The sender's flow ID to configure, as returned by DPNI_SET_TX_FLOW command; use 'DPNI_COMMON_TX_CONF' for configuring the common Tx confirmation queue.
0x10 0-31 THRESHOLD_ENTRY Congestion state is entered above this threshold (according to selected units); set to '0' to disable
32-63 THRESHOLD_EXIT Congestion state is exited below this threshold (according to selected units)
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-115
All unspecified fields are reserved and must be cleared (set to zero)
7.3.69 DPNI_GET_TX_CONF_CONGESTION_NOTIFICATION
Get Tx conf congestion notification configuration
0x18 0-31 OPTIONS Options for congestion notifications:
Bit 0: DPNI_CONG_OPT_WRITE_MEM_ON_ENTER – CSCN message is written to MESSAGE_IOVA once entering a congestion state (see THRESHOLD_ENTRY).
Bit 1: DPNI_CONG_OPT_WRITE_MEM_ON_EXIT – CSCN message is written to MESSAGE_IOVA once exiting a congestion state (see THRESHOLD_EXIT).
Bit 2: DPNI_CONG_OPT_COHERENT_WRITE – CSCN write attempts to allocate into a cache (coherent write); valid only if 'DPNI_CONG_OPT_WRITE_MEM_ON_ENTER/EXIT' are selected.
Bit 4: DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER – when DEST_TYPE is not ‘DPNI_DEST_NONE', CSCN message is sent to the DPIO’s or DPCON's channel once entering a congestion state (see THRESHOLD_ENTRY).
Bit 5: DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT – when DEST_TYPE is not ‘DPNI_DEST_NONE', CSCN message is sent to the DPIO’s or DPCON's channel once exiting a congestion state (see THRESHOLD_EXIT).
Bit 6: DPNI_CONG_OPT_INTR_COALESCING_DISABLED – when DEST_TYPE is not ‘DPNI_DEST_NONE', the DQRI interrupt is asserted immediately (if enabled) when the CSCN is written to the software portal’s DQRR.
32-63 DEST_ID Either DPIO ID or DPCON ID, depending on DEST_TYPE selection; not relevant for 'DPNI_DEST_NONE' option
0x20 0-63 MESSAGE_CTX User’s context to be provided as part of the CSCN message
0x28 0-63 MESSAGE_IOVA I/O virtual address (must be in DMA-able memory and 16B aligned) for writing CSCN messages to memory; valid only when 'DPNI_CONG_OPT_WRITE_MEM_ENTER/EXIT' are selected in ‘OPTIONS’
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-116
Command structure
Figure 159. DPNI_GET_TX_CONF_CONGESTION_NOTIFICATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x25A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 0
0x08 FLOW_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 48-63 FLOW_ID The sender's flow ID to query, as returned by DPNI_SET_TX_FLOW command; use 'DPNI_COMMON_TX_CONF' for retrieving common Tx confirmation configuration.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-117
Response structure
Figure 160. DPNI_GET_TX_CONF_CONGESTION_NOTIFICATION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x25A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 8 7 4 2-3 0-1
0x08 – PRIORITY – DEST_
TYPE
–
UN
ITS
63 32 31 0
0x10 THRESHOLD_EXIT THRESHOLD_ENTRY
63 32 31 0
0x18 DEST_ID OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-1 UNITS Refer to DPNI_SET_TX_CONF_CONGESTION_NOTIFICATION for description of these fields.
4-7 DEST_TYPE
16-23 PRIORITY
0x10 0-31 THRESHOLD_ENTRY
32-63 THRESHOLD_EXIT
0x18 0-31 OPTIONS
32-63 DEST_ID
0x20 0-63 MESSAGE_CTX
0x28 0-63 MESSAGE_IOVA
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-118
7.3.70 DPNI_SET_TX_FLOW
Set the configuration of a specified transmit flow. A transmit flow is associated with a ‘sender’, that is with an entity that enqueues frames to the DPNI. The DPNI supports multiple senders, up to the number specified in MAX_SENDERS field in DPNI_CREATE command.
The sender’s ID (FLOW_ID) is not known in advance to the sender, and therefore each sender must invoke this command at least once before enqueuing frames to the DPNI, in order to generate its FLOW_ID. The FLOW_ID should be used as the QDBIN value in the enqueue operation. This command may be invoked again and again to modify the transmit flow attributes, in this case each sender should specify its own FLOW_ID.
Each sender has a private transmit confirmation and error queue, unless the DPNI_OPT_TX_CONF_DISABLED or DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED options were set during creation of the DPNI (refer to DPNI_CREATE command description). This command may be used to configure various options for the sender’s private transmit confirmation and error queue. Most of the settings in this command support the configuration of this private queue. The user may associate the queue with DPIO or DPCON objects for notifications on data availability and/or advanced scheduling options. In addition, it is possible (and recommended) to set a user-defined context value (USER_CTX) for this queue. The configured USER_CTX is part of a dequeued Frame Descriptor.
Other settings in this command are related to L3 and L4 checksum generation during frame transmission.
It is possible to modify only a subset of the settings in each invocation of the command – use the OPTIONS and QUEUE_OPTIONS fields to specify which settings are to be modified.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-119
Command structure
Figure 161. DPNI_SET_TX_FLOW Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x236 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 46-
47
45 44 43 42 0
0x08 FLOW_ID –
US
E_C
OM
MO
N_T
X_C
ON
F_Q
UE
UE
L4_CH
KS
UM
_GE
N
L3_CH
KS
UM
_GE
T
–
63 0
0x10 –
63 32 31 0
0x18 – OPTIONS
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-120
All unspecified fields are reserved and must be cleared (set to zero)
0x08 43 L3_CHKSUM_GEN '0' – disable L3 checksum generation.'1' – enable L3 checksum generation.Valid only if DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN is set in OPTIONS
44 L4_CHKSUM_GEN '0' – disable L4 checksum generation.'1' – enable L4 checksum generation.Valid only if DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN is set in OPTIONS
45 USE_COMMON_TX_CONF_QUEUE 0: Use a private Tx confirmation and error queue.1: Use the common (default) Tx confirmation and error queue.Valid only if 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'OPTIONS'
48-63 FLOW_ID FLOW_ID represents the sender's ID; this ID should be used as QDBIN argument in every enqueue operations.Each sender should invoke this command before starting to transmit frames through the DPNI; in first invocation of the command by a sender, this field must be set to 0xFF (DPNI_NEW_FLOW_ID) to generate a new FLOW_ID (see also below, description of the response structure).The generated FLOW_ID must be set in subsequent invocations of this command by the same sender.
0x18 0-31 OPTIONS Option bits selecting the requested modifications to the transmit flow:
Bit 0: DPNI_TX_FLOW_OPT_TX_CONF_ERROR – set to modify the USE_DEFAULT_QUEUE setting.Bit 4: DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN – set to modify the L3 checksum generation settingBit 5: DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN – set to modify the L4 checksum generation setting
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-121
Response structure
Figure 162. DPNI_SET_TX_FLOW Response Description
All unspecified fields are cleared.
7.3.71 DPNI_GET_TX_FLOW
Get the configuration of a specified transmit flow. A transmit flow is associated with a ‘sender’, that is with an entity that enqueues frames to the DPNI. See DPNI_SET_TX_FLOW for more details.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x236 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 0
0x08 FLOW_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 48-63 FLOW_ID FLOW_ID represents the sender's ID; this ID should be used as QDBIN argument in every enqueue operations.On first invocation of the command by a sender, the FLOW_ID field in the command is set to 0xFF (DPNI_NEW_FLOW_ID) to generate a new FLOW_ID (see also above, description of the command structure); the generated FLOW_ID is returned here, and must be set in subsequent invocations of this command by the same sender.Subsequent invocations of the command with an existing FLOW_ID (different from 0xFF) are not expected to change the FLOW_ID value, so this field may be ignored.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-122
Command structure
Figure 163. DPNI_GET_TX_FLOW Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x237 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 0
0x08 FLOW_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 48-63 FLOW_ID FLOW_ID represents the sender's ID; it is generated by each sender by invoking the DPNI_SET_TX_FLOW command before starting any transmission of frames through the DPNI.The generated FLOW_ID must be set in subsequent invocations of commands related to the same transmit flow, including this command.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-123
Response structure
Figure 164. DPNI_GET_TX_FLOW Command Description
All unspecified fields are cleared.
7.3.72 DPNI_SET_RX_FLOW
Set the configuration of a specified receive flow. Receive flows are grouped per traffic class, therefore the identification of a receive flow involves both the traffic class ID (TC_ID) and the relative flow ID (FLOW_ID) within that traffic class.
The user may associate a receive flow with DPIO or DPCON objects for notifications on data availability and/or advanced scheduling options. In addition, it is possible (and recommended) to set a user-defined
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x237 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 46 45 44 43 42 0
0x08 –
US
E_C
OM
MO
N_T
X_C
ON
F_Q
UE
UE
L4_CH
KS
UM
_GE
N
L3_CH
KS
UM
_GE
T
–
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 43 L3_CHKSUM_GEN Refer to DPNI_SET_TX_FLOW for description of these fields.
44 L4_CHKSUM_GEN
45 USE_COMMON_TX_CONF_QUEUE
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-124
context value (USER_CTX) for each receive flow. The configured USER_CTX is part of a dequeued Frame Descriptor.
It is possible to modify only a subset of the settings in each invocation of the command – use the QUEUE_OPTIONS fields to specify which settings are to be modified.
Command structure
Figure 165. DPNI_SET_RX_FLOW Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x238 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 43
47
42 41 40 39 32 31 0
0x08 FLOW_ID –
OP
E
DEST_TYPE
PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 18 17 16 15 0
0x18 QUEUE_OPTIONS – TC_ID –
63 32 31 12 11 8 7 4 3 0
0x20 FLC_OPTIONS – FLOW_CONTEXT_SIZ
E
FRAME_DATA_
SIZE
FLC_TYPE
63 0
0x28 FLOW_CONTEXT
63 32 31 0
0x30 – TAIL_DROP_THRESHOLD
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-125
0x08 0-31 DEST_ID For DEST_TYPE = DPNI_DEST_DPIO, set to the DPIO ID;For DEST_TYPE = DPNI_DEST_DPCON, set to the DPCON ID.Valid only if DPNI_QUEUE_OPT_DEST is set in QUEUE_OPTIONS.
32-39 PRIORITY Priority selection within the DPIO or DPCON channel, according to the selection in DEST_TYPE; valid values are 0-7, but depending on the number of priorities in the corresponding channel.This field is irrelevant for DEST_TYPE = DPNI_DEST_NONE.Valid only if DPNI_QUEUE_OPT_DEST is set in QUEUE_OPTIONS.
40-41 DEST_TYPE Selects the destination for the receive queue:
0: DPNI_DEST_NONE – unassigned destination; the queue is set in parked mode and does not generate FQDAN notifications; user is expected to dequeue from the queue based on polling or other user-defined method.1: DPNI_DEST_DPIO – the queue is set in scheduled mode and generates FQDAN notifications to the specified DPIO; user is expected to dequeue from the queue only after notification is received.2: DPNI_DEST_DPCON – the queue is set in scheduled mode; the queue does not generate FQDAN notifications, but is rather connected to the specified DPCON object; user is expected to dequeue from the DPCON channel.
Valid only if DPNI_QUEUE_OPT_DEST is set in QUEUE_OPTIONS.
42 ORDER_PRESEVATION_EN (OPE) enable/disable order preservation; valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is containedin 'options'
48-63 FLOW_ID Identifies the receive flow ID within the specified traffic class (TC_ID).Use 0xFF (DPNI_ALL_TC_FLOWS) to apply the selected configuration on all flows within the traffic class.This field is ignored if TC_ID = 0xFF (DPNI_ALL_TCS).
0x10 0-63 USER_CTX User context value provided within the frame descriptor of each dequeued frame.Valid only if DPNI_QUEUE_OPT_USER_CTX is set in QUEUE_OPTIONS.
0x18 16-23 TC_ID Traffic class to configure; valid values are in the range of (0-7), but also limited by the maximum number of traffic classes configured during the creation of the DPNI.Use 0xFF (DPNI_ALL_TCS) to apply the selected configuration on all traffic classes of the DPNI.
32-63 QUEUE_OPTIONS Option bits selecting the requested modifications to the transmit flow:
Bit 0: DPNI_QUEUE_OPT_USER_CTX – Set to modify the user's context associated with the queue to the value in USER_CTX.Bit 1:.DPNI_QUEUE_OPT_DEST – Set to modify the queue’s destination according to DEST_TYPE.Bit 2: DPNI_QUEUE_OPT_FLC – Set to modify the flow context associated with the queue according to FLC_TYPE.Bit 3: DPNI_QUEUE_OPT_ORDER_PRESERVATION – Set to modify the queue’s order preservation mode, according to ORDER_PRESERVATION_EN field.Bit 4: DPNI_QUEUE_OPT_TAILDROP_THRESHOLD – Set to modify the queue’s tail-drop threshold, according to TAIL_DROP_THRESHOLD field.
0x20 0-3 FLC_TYPE Flow context type:‘DPNI_FLC_USER_DEFINED’ – flow context is a user-defined value‘DPNI_FLC_STASH’ – flow context is an I/O virtual address of memory to be stashed.
4-7 FRAME_DATA_SIZE Size of frame data to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
8-11 FLOW_CONTEXT_SIZE Size of flow context to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
32-63 FLC_OPTIONS Option bits for the flow context;
Bit 0: DPNI_FLC_STASH_FRAME_ANNOTATION – stash the frame annotation area (up to 192 bytes)
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-126
All unspecified fields are reserved and must be cleared (set to zero)
7.3.73 DPNI_GET_RX_FLOW
Get the configuration of a specified receive flow. See DPNI_SET_RX_FLOW for more details.
Command structure
Figure 166. DPNI_GET_RX_FLOW Command Description
All unspecified fields are reserved and must be cleared (set to zero)
0x28 0-63 FLOW_CONTEXT If ‘FLC_TYPE’ = 'DPNI_FLC_USER_DEFINED', this value is provided in the dequeued frame descriptor (FD[FLC]).If ‘FLC_TYPE’ = 'DPNI_FLC_STASH', this value is the I/O virtual address of the user’s flow context that should be stashed; Must be cache-line aligned and DMA-able memory. The size of stashed memory is taken from FLOW_CONTEXT_SIZE.
0x30 0-31 TAIL_DROP_THRESHOLD The queue's tail drop threshold in bytes;‘0' value disables the threshold; maximum value is 0xE000000;valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained in 'options'
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x239 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 24 23 16 15 0
0x08 FLOW_ID – TC_ID –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID Traffic class to configure; valid values are in the range of (0-7), but also limited by the maximum number of traffic classes configured during the creation of the DPNI.
48-63 FLOW_ID Identifies the receive flow ID within the specified traffic class (TC_ID).
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-127
Response structure
Figure 167. DPNI_GET_RX_FLOW Response Description
All unspecified fields are cleared.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x239 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 43 42 41 40 39 32 31 0
0x08 -
OP
E
DEST_TYPE DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 0
0x18 FQID TAIL_DROP_THRESHOLD
63 32 31 12 11 8 7 4 3 0
0x20 FLC_OPTIONS – FLOW_CONTEXT_SIZ
E
FRAME_DATA_
SIZE
FLC_TYPE
63 0
0x28 FLOW_CONTEXT
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Refer to DPNI_SET_RX_FLOW for description of these fields.
32-39 DEST_PRIORITY
40-41 DEST_TYPE
42 ORDER_PRESERVATION_EN (OPE)
0x10 0-63 USER_CTX
0x18 0-31 TAIL_DROP_THRESHOLD
32-63 FQID Virtual Frame Queue ID to be used when dequeuing from the receive queue of the specified flow ID.
0x20 0-3 FLC_TYPE Refer to DPNI_SET_RX_FLOW for description of these fields.
4-7 FRAME_DATA_SIZE
8-11 FLOW_CONTEXT_SIZE
32-63 FLC_OPTIONS
0x28 0-63 FLOW_CONTEXT
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-128
7.3.74 DPNI_SET_RX_ERR_QUEUE
Set the configuration of the common receive error queue.
The user may associate the common receive error queue with DPIO or DPCON objects for notifications on data availability and/or advanced scheduling options. In addition, it is possible (and recommended) to set a user-defined context value (USER_CTX) for this queue. The configured USER_CTX is part of a dequeued Frame Descriptor.
It is possible to modify only a subset of the settings in each invocation of the command – use the QUEUE_OPTIONS fields to specify which settings are to be modified.
Command structure
Figure 168. DPNI_SET_RX_ERR_QUEUE Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x23A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 43 42 41 40 39 32 31 0
0x08 -
OP
E
DEST_TYPE
DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 0
0x18 TAIL_DROP_THRESHOLD QUEUE_OPTIONS
63 32 31 12 11 8 7 4 3 0
0x20 FLC_OPTIONS – FLOW_CONTEXT_SIZ
E
FRAME_DATA_
SIZE
FLC_TYPE
63 0
0x28 FLOW_CONTEXT
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-129
All unspecified fields are reserved and must be cleared (set to zero)
7.3.75 DPNI_GET_RX_ERR_QUEUE
Get the configuration of a specified receive flow. See DPNI_SET_RX_ERR_QUEUE for more details.
0x08 0-31 DEST_ID For DEST_TYPE = DPNI_DEST_DPIO, set to the DPIO ID;For DEST_TYPE = DPNI_DEST_DPCON, set to the DPCON ID.
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel, according to the selection in DEST_TYPE; valid values are 0-7, but depending on the number of priorities in the corresponding channel.This field is irrelevant for DEST_TYPE = DPNI_DEST_NONE.
40-41 DEST_TYPE Selects the destination for the receive queue:
0: DPNI_DEST_NONE – unassigned destination; the queue is set in parked mode and does not generate FQDAN notifications; user is expected to dequeue from the queue based on polling or other user-defined method.1: DPNI_DEST_DPIO – the queue is set in scheduled mode and generates FQDAN notifications to the specified DPIO; user is expected to dequeue from the queue only after notification is received.2: DPNI_DEST_DPCON – the queue is set in scheduled mode; the queue does not generate FQDAN notifications, but is rather connected to the specified DPCON object; user is expected to dequeue from the DPCON channel.
42 ORDER_PRESERVATION_EN (OPE) enable/disable order preservation; valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained in 'options'
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' is contained in 'options'
0x18 0-31 QUEUE_OPTIONS Option bits selecting the requested modifications to the transmit flow:
Bit 0: DPNI_QUEUE_OPT_USER_CTX – Set to modify the user's context associated with the queue to the value in USER_CTX.Bit 1:.DPNI_QUEUE_OPT_DEST – Set to modify the queue’s destination according to DEST_TYPE.Bit 2: DPNI_QUEUE_OPT_FLC – Set to modify the flow context associated with the queue according to FLC_TYPE.Bit 3: DPNI_QUEUE_OPT_ORDER_PRESERVATION – Set to modify the queue’s order preservation mode, according to ORDER_PRESERVATION_EN field.Bit 4: DPNI_QUEUE_OPT_TAILDROP_THRESHOLD – Set to modify the queue’s tail-drop threshold, according to TAIL_DROP_THRESHOLD field.
32-63 TAIL_DROP_THRESHOLD Set the queue's tail drop threshold in bytes;'0' disables the threshold; maximum value is 0xE000000;valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is selected in 'QUEUE_OPTIONS'
0x20 0-3 FLC_TYPE Flow context type:‘DPNI_FLC_USER_DEFINED’ – flow context is a user-defined value‘DPNI_FLC_STASH’ – flow context is an I/O virtual address of memory to be stashed.
4-7 FRAME_DATA_SIZE Size of frame data to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
8-11 FLOW_CONTEXT_SIZE Size of flow context to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
32-63 FLC_OPTIONS Mask of available options; use ‘DPNI_FLC_STASH_<x>’ values
0x28 0-63 FLOW_CONTEXT If ‘FLC_TYPE’ = 'DPNI_FLC_USER_DEFINED', this value is provided in the dequeued frame descriptor (FD[FLC]).If ‘FLC_TYPE’ = 'DPNI_FLC_STASH', this value is the I/O virtual address of the user’s flow context that should be stashed; Must be cache-line aligned and DMA-able memory. The size of stashed memory is taken from FLOW_CONTEXT_SIZE.
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-130
Command structure
Figure 169. DPNI_GET_RX_ERR_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x23B – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-131
Response structure
Figure 170. DPNI_GET_RX_ERR_QUEUE Response Description
All unspecified fields are cleared.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x23B – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 43 42 41 40 39 32 31 0
0x08 -
OP
E
DEST_TYPE DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 0
0x18 FQID TAIL_DROP_THRESHOLD
63 32 31 12 11 8 7 4 3 0
0x20 FLC_OPTIONS – FLOW_CONTEXT_SIZ
E
FRAME_DATA_
SIZE
FLC_TYPE
63 0
0x28 FLOW_CONTEXT
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Refer to DPNI_SET_RX_ERR_QUEUE for description of these fields.
32-39 DEST_PRIORITY
40-41 DEST_TYPE
42 ORDER_PRESEVATION_EN (OPE)
0x10 0-63 USER_CTX
0x18 0-31 TAIL_DROP_THRESHOLD
32-63 FQID Virtual Frame Queue ID to be used when dequeuing from the common receive error queue.
0x20 0-3 FLC_TYPE Flow context type:‘DPNI_FLC_USER_DEFINED’ – flow context is a user-defined value‘DPNI_FLC_STASH’ – flow context is an I/O virtual address of memory to be stashed.
4-7 FRAME_DATA_SIZE Size of frame data to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
8-11 FLOW_CONTEXT_SIZE Size of flow context to be stashed; valid only if ‘FLC_TYPE’ = ‘DPNI_FLC_STASH’
32-63 FLC_OPTIONS Mask of available options; use ‘DPNI_FLC_STASH_<x>’ values
0x28 0-63 FLOW_CONTEXT If ‘FLC_TYPE’ = 'DPNI_FLC_USER_DEFINED', this value is provided in the dequeued frame descriptor (FD[FLC]).If ‘FLC_TYPE’ = 'DPNI_FLC_STASH', this value is the I/O virtual address of the user’s flow context that should be stashed; Must be cache-line aligned and DMA-able memory. The size of stashed memory is taken from FLOW_CONTEXT_SIZE.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-132
7.3.76 DPNI_SET_TX_CONF_REVOKE
Tx confirmation revocation. This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not selected at DPNI creation. Calling this function with 'revoke' set to '1' disables all transmit confirmation (including the private confirmation queues), regardless of previous settings; Note that in this case, Tx error frames are still enqueued to the general transmit errors queue. Calling this function with 'revoke' set to '0' restores the previous settings for both general and private transmit confirmation.
Command structure
Figure 171. DPNI_SET_TX_CONF_REVOKE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x20C – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 -
RE
VO
KE
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 REVOKE 1: Disable all transmit confirmation (including private confirmation queues), regardless of previous settings; Note that in this case, Tx error frames are still enqueued to the common transmit errors queue.0: Restores previous settings for both common and private transmit confirmation queues
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-133
7.3.77 DPNI_SET_QOS_TABLE
Configure the QoS criteria and attributes. The result of the lookup in QoS table determines the traffic class for the received frame. The user may select a flexible lookup key for the QoS table. This command must be invoked to select the QoS key format, before adding any QoS entries using the DPNI_ADD_QOS_ENTRY command.
This function and all QoS-related functions require that the DPNI was created with multiple traffic classes.
Command structure
Figure 172. DPNI_SET_QOS_TABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x240 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 41 40 39 32 31 0
0x08
DIS
CA
RD
_ON
_MIS
S
DEFAULT_TC –
63 0
0x10 -
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 KEY_CFG_IOVA
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 DEFAULT_TC Default traffic class to use in case of a lookup miss in the QoS table.Valid only if DISCARD_ON_MISS is not set.
40 DISCARD_ON_MISS Determine the action in case of a lookup miss in the QoS table.'0' – use DEFAULT_TC in case of no match‘1’ – discard frames in case of no match.
0x38 0-63 KEY_CFG_IOVA I/O virtual address of zeroed 256 bytes of DMA-able memory. This extended buffer must be programmed as specified in the “Extension structure” section below, to hold the QoS key configuration.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-134
Extension structure
Figure 173. DPNI_SET_QOS_TABLE Extension Description
Offset from Management Command Portal base Read-Write Access
63 8 7 0
0x00 – NUM_EXTRACTS
63 32 31 24 23 16 15 12 11 8 7 0
0x08 FIELD OFFSET SIZE –
EF
H_T
YP
E
PROT
63 36 35 32 31 24 23 16 15 8 7 0
0x10 –
EX
TR
AC
T_T
YP
E
NUM_OF_BYTE_MASKS
NUM_OF_REPEATS
CONSTANT HDR_INDEX
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 MASK3_OFFSET MASK3_MASK MASK2_OFFSET MASK2_MASK MASK1_OFFSET MASK1_MASK MASK0_OFFSET MASK0_MASK
0x20 - 0xC7
Repeating (9 more sections) of the extraction fields in offsets (0x08 - 0x1F) above.NUM_EXTRACTS determines the number of valid extraction sections up to the 10 possible.
Offset Bits Name Description
0x00 0-7 NUM_EXTRACTS Number of valid extractions out of the 10 possible; determines how many of the EXTRACT0..9 below are valid. Value of 0 is invalid.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-135
0x08 0-7 EXTRACT0 PROT For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: specify any of the supported headers:
8-11 EFH_TYPE For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: specify the type of extraction from header (and determines validity of the next 3 parameters):0: DPKG_FROM_HDR – SIZE and OFFSET are valid; SIZE bytes are extracted from OFFSET relative to the start of the specified header (PROT).1: DPKG_FROM_FIELD – FIELD, SIZE and OFFSET are valid; SIZE bytes are extracted from OFFSET relative to the start of the specified FIELD.2: DPKG_FULL_FIELD – only FIELD is valid; specified FIELD is fully extracted.
16-23 SIZE Size (in bytes) of the extraction
42-31 OFFSET Byte offset of starting point of the extraction
32-63 FIELD For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: standard field selection for the extraction
0x10 0-7 HDR_INDEX For EXTRACT_TYPE = DPKG_EXTRACT_FROM_HDR: indicates the PROT header index for protocols that may appear more than once within a frame (examples: VLAN, MPLS, IP).0x00 indicates the most outer (first) header.0xFF indicates the most inner (last) header.
8-15 CONSTANT For EXTRACT_TYPE = DPKG_EXTRACT_CONSTANT: the constant value to extract (one byte)
16-23 NUM_OF_REPEATS For EXTRACT_TYPE = DPKG_EXTRACT_CONSTANT: number of times to repeat the extraction of the constant value (values are placed in the key in adjacent manner)
24-31 NUM_OF_BYTE_MASKS Determines the number of valid entries of MASKn_MASK and MASKn_OFFSET.Up to four byte masks are available to apply on the extracted content (each mask is 1 byte in size).Note, that byte masks are valid for any selection of EXTRACT_TYPE.
32-35 EXTRACT_TYPE Determines the type of extraction:
0: DPKG_EXTRACT_FROM_HDR – extract from the frame header; the following fields are considered valid in this case:PROT, EFH_TYPE, SIZE, OFFSET, FIELD, HDR_INDEX
1: DPKG_EXTRACT_FROM_DATA – extract from data not in the header; the following fields are considered valid in this case:SIZE, OFFSET
2: DPKG_EXTRACT_CONSTANT – extract user-selected constant values; the following fields are considered valid in this case:CONSTANT, NUM_OF_REPEATS
0x18 0-7 MASK0_MASK Byte mask to apply on the extracted content at offset MASK0_OFFSET
8-15 MASK0_OFFSET Offset (relative to the first byte of extracted content) for applying MASK0_MASK
16-23 MASK1_MASK Byte mask to apply on the extracted content at offset MASK1_OFFSET
24-31 MASK1_OFFSET Offset (relative to the first byte of extracted content) for applying MASK1_MASK
32-39 MASK2_MASK Byte mask to apply on the extracted content at offset MASK2_OFFSET
40-47 MASK2_OFFSET Offset (relative to the first byte of extracted content) for applying MASK2_MASK
48-55 MASK3_MASK Byte mask to apply on the extracted content at offset MASK3_OFFSET
56-63 MASK3_OFFSET Offset (relative to the first byte of extracted content) for applying MASK3_MASK
0x20 - 0x37
EXTRACT1 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 2
0x38 - 0x4F
EXTRACT2 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 3
0x50 - 0x67
EXTRACT3 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 4
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-136
All unspecified fields are reserved and must be cleared (set to zero)
7.3.78 DPNI_ADD_QOS_ENTRY
Add QoS mapping entry to select a traffic class for frames matching the specified rule.
Before using this command, the DPNI_SET_QOS_TABLE command must be invoked in order to define the QoS key format and other attributes.
The user is responsible for providing the pointers (DMA-able memory) to the key and optionally a mask to apply on extracted bytes.
0x68 - 0x7F
EXTRACT4 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 5
0x80 - 0x97
EXTRACT5 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 6
0x98 - 0xAF
EXTRACT6 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 7
0xB0 - 0xC7
EXTRACT7 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 8
0xC8 - 0xDF
EXTRACT8 Similar to EXTRACT0; valid if NUM_EXTRACTS >= 9
0xE0 - 0xF7
EXTRACT9 Similar to EXTRACT0; valid if NUM_EXTRACTS = 10
Offset Bits Name Description
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-137
Command structure
Figure 174. DPNI_ADD_QOS_ENTRY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.79 DPNI_REMOVE_QOS_ENTRY
Remove QoS mapping entry that was previously added using DPNI_ADD_QOS_ENTRY command.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x241 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 24 23 16 15 0
0x08 – KEY_SIZE TC_ID
63 0
0x10 KEY_IOVA
63 0
0x18 MASK_IOVA
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-23 TC_ID The traffic class to select in case a frame matches the specified lookup key and mask. Valid values are in the range of (0-7), but also limited by the number of traffic classes configured during the creation of the DPNI.
24-31 KEY_SIZE Size of the key and mask (in bytes); Must not exceed 56 bytes.
0x10 0-63 KEY_IOVA I/O virtual address of the key (must be in DMA-able memory). The key contents must match the extraction order and format as specified in the SET_QOS_TABLE command.
0x18 0-63 MASK_IOVA I/O virtual address of the mask for applying on extracted bytes (must be in DMA-able memory); the mask format must match the key format.Clear this field to indicate that no mask should be applied.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-138
Command structure
Figure 175. DPNI_REMOVE_QOS_ENTRY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.80 DPNI_CLEAR_QOS_TABLE
Clear all QoS mapping entries. This command causes all received frames to be classified to the default traffic class (TC_ID = 0).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x242 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 28 27 24 23 0
0x08 – KEY_SIZE
63 0
0x10 KEY_IOVA
63 0
0x18 MASK_IOVA
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 24-31 KEY_SIZE Size of the key and mask (in bytes); Must not exceed 56 bytes.
0x10 0-63 KEY_IOVA I/O virtual address of the key (must be in DMA-able memory). The key contents must match the extraction order and format as specified in the SET_QOS_TABLE command.
0x18 0-63 MASK_IOVA I/O virtual address of the mask for applying on extracted bytes (must be in DMA-able memory); the mask format must match the key format.Clear this field to indicate that no mask should be applied.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-139
Command structure
Figure 176. DPNI_CLEAR_QOS_TABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.81 DPNI_ADD_FS_ENTRY
Add explicit flow steering entry to explicitly select a receive flow ID within a traffic class. Flow steering lookup tables are managed per traffic class, therefore the user must first ensure that the frame type of interest is also classified to the correct traffic class. Please refer to DPNI_ADD_QOS_ENTRY command for more details.
Before using this command, the DPNI_SET_RX_TC_DIST command must be invoked to select flow steering distribution mode (DIST_MODE = DPNI_DIST_MODE_FS), and to define the QoS key format and other attributes.
The user is responsible for providing the pointers (DMA-able memory) to the key and optionally a mask to apply on extracted bytes.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x243 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 0
0x08 –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-140
Command structure
Figure 177. DPNI_ADD_FS_ENTRY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.82 DPNI_REMOVE_FS_ENTRY
Remove an existing flow steering entry that belongs to a specified traffic class.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x244 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 48 47 32 31 24 23 16 15 0
0x08 FLOW_ID – KEY_SIZE TC_ID
63 0
0x10 KEY_IOVA
63 0
0x18 MASK_IOVA
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 16-23 TC_ID Traffic class selection. Valid values are in the range of (0-7), but also limited by the number of traffic classes configured during the creation of the DPNI.
24-31 KEY_SIZE Size of the key and mask (in bytes); Must not exceed 56 bytes.
48-63 FLOW_ID The receive flow ID to select in case a frame matches the specified lookup key and mask. The flow ID is zero based and limited by the distribution size configured for the specified traffic class (refer to DIST_SIZE in the DPNI_SET_RX_TC_DIST command).
0x10 0-63 KEY_IOVA I/O virtual address of the key (must be in DMA-able memory). The key contents must match the extraction order and format as specified in the DPNI_SET_RX_TC_DIST command.
0x18 0-63 MASK_IOVA I/O virtual address of the mask for applying on extracted bytes (must be in DMA-able memory); the mask format must match the key format.Clear this field to indicate that no mask should be applied.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-141
Command structure
Figure 178. DPNI_REMOVE_FS_ENTRY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.83 DPNI_CLEAR_FS_ENTRIES
Clear all flow steering entries of a specified traffic class. This command causes all received frames associated with that traffic class to be classified to the default flow ID (FLOW_ID = 0).
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x245 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 32 31 24 23 16 15 0
0x08 – KEY_SIZE TC_ID
63 0
0x10 KEY_IOVA
63 0
0x18 MASK_IOVA
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 16-23 TC_ID Traffic class selection. Valid values are in the range of (0-7), but also limited by the number of traffic classes configured during the creation of the DPNI.
24-31 KEY_SIZE Size of the key and mask (in bytes); Must not exceed 56 bytes.
0x10 0-63 KEY_IOVA I/O virtual address of the key (must be in DMA-able memory). The key contents must match the extraction order and format as specified in the DPNI_SET_RX_TC_DIST command.
0x18 0-63 MASK_IOVA I/O virtual address of the mask for applying on extracted bytes (must be in DMA-able memory); the mask format must match the key format.Clear this field to indicate that no mask should be applied.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-142
Command structure
Figure 179. DPNI_CLEAR_FS_ENTRIES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.84 DPNI_SET_VLAN_INSERTION
Enable or disable VLAN insertion for egress frames.
VLAN insertion functionality requires that the DPNI_OPT_VLAN_MANIPULATION configuration option is set at DPNI creation.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x246 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 24 23 16 15 0
0x08 – TC_ID
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 16-23 TC_ID Traffic class selection. Valid values are in the range of (0-7), but also limited by the number of traffic classes configured during the creation of the DPNI.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-143
Command structure
Figure 180. DPNI_SET_VLAN_INSERTION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.85 DPNI_SET_VLAN_REMOVAL
Enable or disable VLAN removal for ingress frames.
VLAN removal functionality requires that the DPNI_OPT_VLAN_MANIPULATION configuration option is set at DPNI creation.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x247 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 0 EN 0 – disable VLAN insertion for transmitted frames.1 – enable VLAN insertion for transmitted frames.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-144
Command structure
Figure 181. DPNI_SET_VLAN_REMOVAL Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.86 DPNI_SET_IPR
Enable or disable IP reassembly of ingress IP fragments.
The IP reassembly functionality requires that the DPNI_OPT_IPR option is set at DPNI creation.
Refer also to the settings of MAX_OPEN_FRAMES_IPV4, MAX_OPEN_FRAMES_IPV6 and MAX_REASS_FRAME_SIZE in DPNI_CREATE command.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x248 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 0 EN 0 – disable VLAN removal for received frames.1 – enable VLAN removal for received frames.
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-145
Command structure
Figure 182. DPNI_SET_IPR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
7.3.87 DPNI_SET_IPF
Enable or disable IP fragmentation of egress frames.
The IP fragmentation functionality rrequires that the DPNI_OPT_IPF option is set at DPNI creation. Fragmentation is performed according to the selected MTU value as set by DPNI_SET_MTU command.
Refer also to the settings of MIN_FRAG_SIZE_IPV4 and MIN_FRAG_SIZE_IPV6 in DPNI_CREATE command.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x249 – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 0 EN
DPNI: Data Path Network Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 7-146
Command structure
Figure 183. DPNI_SET_IPF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x24A – TOKEN – –
INT
R_D
IS
STATUS P – SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0X08 0 EN 0 - disable IP fragmentation of transmitted frames1 - enable IP fragmentation of transmitted frames, according to selected MTU value.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-1
Chapter 8 DPBP: Data Path Buffer PoolThe DPBP configures a buffer pool that can be associated with DPAA2 network and accelerator interfaces; DPBP owners are responsible for seeding it with buffers. The DPBP is a DPAA2 infrastructure object used to configure a buffer pool that is compatible with QBMan hardware. The main role of the buffer manager in DPAA2 is to reduce the software overhead associated with managing free buffer pools for multiple DPAA2 objects. The buffer manager manages pools of data storage buffers, and allows the acquisition and release of these buffers on behalf of multiple processor cores, network interfaces, and accelerators in a multi-core SoC.
The DPBP is a DPAA2 infrastructure object used for buffer pool configuration, which is compatible with the QBMan hardware and represents it; however it doesn't monitor the buffer pool content that is managed by the GPP software. The main role of the buffer manager in DPAA2 is to reduce the overhead on software for managing free buffer pools for multiple DPAA2 objects. The Buffer Manager is managing pools of data storage buffers and allows the acquisition and release of these buffers on behalf of multiple processor cores, network interfaces, and accelerators in a multi-core SoC.
The DPBP object is required for receiving frames from a network interface; refer to the DPNI section for more information on the relationship between DPNI and DPBP.
Please refer to the API book for complete reference of available functions.
8.1 DPBP featuresThe following list summarizes the DPBP main features and capabilities:
• Maintains a list of software-provided free buffers that are used with DPAA2 objects
• Supports buffer pool depletion notifications
• Does not perform read or write access to the buffer
• Supports enable, disable, and reset operations
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-2
8.2 DPBP command referenceThis section contains the detailed programming model of DPBP commands.
8.2.1 DPBP_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPBP_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
The command format is shown in the figure below.
Figure 184. DPBP_OPEN Command Description
The following table describes the command fields.
1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x804 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPBP_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 12. DPBP_OPEN Command Field Descriptions1
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPBP_ID DPBP unique ID
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-3
8.2.2 DPBP_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 185. DPBP_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-4
8.2.3 DPBP_CREATE
This command creates and initializes an instance of DPBP according to the specified command parameters. This command is not required for DPBP instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 186. DPBP_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x904 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 13. DPBP_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-5
8.2.4 DPBP_DESTROY
Command structure
Figure 187. DPBP_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-6
8.2.5 DPBP_ENABLE
Command structure
Figure 188. DPBP_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-7
8.2.6 DPBP_DISABLE
Command structure
Figure 189. DPBP_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-8
8.2.7 DPBP_IS_ENABLED
Command structure
Figure 190. DPBP_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-9
Response structure
Figure 191. DPBP_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-10
8.2.8 DPBP_RESET
Command structure
Figure 192. DPBP_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-11
8.2.9 DPBP_SET_IRQ
Set IRQ information for the DPBP to trigger an interrupt.
Command structure
Figure 193. DPBP_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-12
8.2.10 DPBP_GET_IRQ
Get IRQ information from the DPBP.
Command structure
Figure 194. DPBP_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-13
Response structure
Figure 195. DPBP_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-14
8.2.11 DPBP_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 196. DPBP_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-15
8.2.12 DPBP_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 197. DPBP_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-16
Response structure
Figure 198. DPBP_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-17
8.2.13 DPBP_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 199. DPBP_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-18
8.2.14 DPBP_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 200. DPBP_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-19
Response structure
Figure 201. DPBP_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-20
8.2.15 DPBP_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 202. DPBP_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPBP_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-21
Response structure
Figure 203. DPBP_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-22
8.2.16 DPBP_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 204. DPBP_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-23
8.2.17 DPBP_GET_ATTRIBUTES
Command structure
Figure 205. DPBP_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-24
Response structure
Figure 206. DPBP_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 ID BPID —
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 BPID Hardware buffer pool ID; should be used as an argument inacquire/release operations on buffers
32-63 ID DPBP object ID
0x10 0-15 VERSION_MAJOR DPBP major version
16-31 VERSION_MINOR DPBP minor version
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-25
8.2.18 DPBP_SET_NOTIFICATIONS
Command structure
Figure 207. DPBP_SET_NOTIFICATIONS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1B0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DEPLETION_EXIT DEPLETION_ENTRYY
63 32 31 0
0x10 SURPLUS_EXIT SURPLUS_ENTRY
63 16 15 0
0x18 — OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0.31 DEPLETION_ENTRY below this threshold the pool is "depleted"; set it to '0' to disable it
32-63 DEPLETION_EXIT greater than or equal to this threshold the pool exit its “depleted" state
0x10 0-31 SURPLUS_ENTRY above this threshold the pool is in "surplus" state; set it to '0' to disable it
32-63 SURPLUS_EXIT less than or equal to this threshold the pool exit its "surplus" state
0x18 0-15 OPTIONS Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
0x20 0-63 MESSAGE_CTX The context that will be part of the BPSCN message and will be written to 'message_iova'
0x28 0-63 MESSAGE_IOVA MUST be given if either 'depletion_entry' or 'surplus_entry' is not '0' (enable); I/O virtual address (must be in DMA-able memory), must be 16B aligned.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-26
8.2.19 DPBP_GET_NOTIFICATIONS
Command structure
Figure 208. DPBP_GET_NOTIFICATIONS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1B1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-27
Response structure
Figure 209. DPBP_GET_NOTIFICATIONS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1B1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DEPLETION_EXIT DEPLETION_ENTRYY
63 32 31 0
0x10 SURPLUS_EXIT SURPLUS_ENTRY
63 16 15 0
0x18 — OPTIONS
63 0
0x20 MESSAGE_CTX
63 0
0x28 MESSAGE_IOVA
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0.31 DEPLETION_ENTRY below this threshold the pool is "depleted"; set to '0' to disable
32-63 DEPLETION_EXIT greater than or equal to this threshold the pool exit its “depleted" state
0x10 0-31 SURPLUS_ENTRY above this threshold the pool is in "surplus" state; set it to '0' to disable it
32-63 SURPLUS_EXIT less than or equal to this threshold the pool exit its "surplus" state
0x18 0-15 OPTIONS Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
0x20 0-63 MESSAGE_CTX The context that will be part of the BPSCN message and will be written to 'MESSAGE_IOVA'
0x28 0-63 MESSAGE_IOVA MUST be given if either 'DEPLETION_ENTRY' or 'SURPLUS_ENTRY' is not '0' (enable); I/O virtual address (must be in DMA-able memory), must be 16B aligned.
DPBP: Data Path Buffer Pool
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 8-28
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-1
Chapter 9 DPIO: Data Path I/OThe DPIO object allows configuration of the QBMan software portal, with optional notification capabilities. Software portals are used by GPP software to communicate with the QBMan. The DPIO object’s main purpose is to enable the GPP to perform I/O – enqueue and dequeue operations, as well as buffer release and acquire operations – using QBMan. Usually, a DPIO object can be affined to a GPP core-thread, to prevent any need for multi-core synchronization on the software portal.
The DPIO object is mandatory for sending frames to, and receiving frames from, a network interface; refer to the DPNI section for more information on the relationship between DPNI and DPIO.
9.1 DPIO featuresThe following list summarizes the DPIO main features and capabilities:
• Supports configuration of the QBMan software portal for GPP I/O operations
• Supports data availability notifications in the frame queues associated with the DPIO object
• Supports data availability notifications in the DPCON objects associated with the DPIO object
• Supports up to eight priorities for scheduling data availability notifications; having a DPIO object with multiple priorities, for example, allows for different notification priorities to be set for different DPNI receive queues; assuming that they are associated with the same DPIO object
• Supports enable, disable, and reset operations
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-2
9.2 DPIO command referenceThis section contains the detailed programming model of DPIO commands.
9.2.1 DPIO_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPIO_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
Figure 210. DPIO_OPEN Command Description
The following table describes the command fields.
1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x803 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPIO_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 14. DPIO_OPEN Command Field Descriptions1
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPIO_ID DPIO unique ID
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-3
9.2.2 DPIO_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 211. DPIO_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-4
9.2.3 DPIO_CREATE
This command creates and initializes an instance of DPIO according to the specified command parameters. This command is not required for DPIO instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 212. DPIO_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x903 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 40 39 32 31 18 17 16 15 0
0x08 — NUM_PRIORITIES
— CHANNEL_MO
DE
—
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 15. DPIO_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-17 CHANNEL_MODE Notification channel mode. Select one of the supported values below:0x0 = DPIO_NO_CHANNEL - No support for notification channel0x1 = DPIO_LOCAL_CHANNEL - Notifications on data availability can be received by a dedicated channel in the DPIO; user should point the queue's destination in the relevant interface to this DPIO
32-39 NUM_PRIORITIES Number of priorities for the notification channel (1-8);relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-5
9.2.4 DPIO_DESTROY
Command structure
Figure 213. DPIO_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-6
9.2.5 DPIO_ENABLECommand structure
Figure 214. DPIO_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-7
9.2.6 DPIO_DISABLE
Command structure
Figure 215. DPIO_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-8
9.2.7 DPIO_IS_ENABLED
Command structure
Figure 216. DPIO_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-9
Response structure
Figure 217. DPIO_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-10
9.2.8 DPIO_RESET
Command structure
Figure 218. DPIO_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-11
9.2.9 DPIO_SET_IRQ
Set IRQ information for the DPIO to trigger an interrupt.
Command structure
Figure 219. DPIO_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 8 7 0
0x08 IRQ_VAL IRQ_INDEX
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 IRQ_INDEX Identifies the interrupt index to configure
32-63 IRQ_VAL Value to write into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-12
9.2.10 DPIO_GET_IRQ
Get IRQ information from the DPIO.
Command structure
Figure 220. DPIO_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-13
Response structure
Figure 221. DPIO_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-14
9.2.11 DPIO_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 222. DPIO_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-15
9.2.12 DPIO_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 223. DPIO_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-16
Response structure
Figure 224. DPIO_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-17
9.2.13 DPIO_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 225. DPIO_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-18
9.2.14 DPIO_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 226. DPIO_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-19
Response structure
Figure 227. DPIO_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-20
9.2.15 DPIO_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 228. DPIO_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPIO_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-21
Response structure
Figure 229. DPIO_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-22
9.2.16 DPIO_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 230. DPIO_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
0x10 - 0x38
reserved
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-23
9.2.17 DPIO_GET_ATTRIBUTES
Command structure
Figure 231. DPIO_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-24
Response structure
Figure 232. DPIO_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 60 59 56 55 48 47 32 31 0
0x08 — CHANNEL_MO
DE
NUM_PRIORITIES
QBMAN_PORTAL_ID ID
63 0
0x10 QBMAN_PORTAL_CE_PADDR
63 0
0x18 QBMAN_PORTAL_CI_PADDR
63 32 31 16 15 0
0x20 QBMAN_VERSION VERSION_MINOR VERSION_MAJOR
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID DPIO object ID
32-47 QBMAN_PORTAL_ID Software portal ID
48-55 NUM_PRIORITIES Number of priorities for the notification channel (1-8); relevant only if 'CHANNEL_MODE = DPIO_LOCAL_CHANNEL'
56-59 CHANNEL_MODE Notification channel mode:0x0 = DPIO_NO_CHANNEL - No support for notification channel0x1 = DPIO_LOCAL_CHANNEL - Notifications on data availability can be received by a dedicated channel in the DPIO; user should point the queue's destination in the relevant interface to this DPIO
0x10 0-63 QBMAN_PORTAL_CE_PADDR Physical address of the software portal cache-enabled area
0x18 0-63 QBAMN_PORTAL_CI_PADDR Physical address of the software portal cache-inhibited area
0x20 0-15 VERSION_MAJOR DPIO major version
16-31 VERSION_MINOR DPIO minor version
32-63 QBMAN_VERSION QBMAN hardware IP version
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-25
9.2.18 DPIO_SET_STASHING_DESTINATION
Command structure
Figure 233. DPIO_SET_STASHING_DESTINATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x120 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 8 7 0
0x08 — SDEST
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 SDEST stashing destination value
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-26
9.2.19 DPIO_GET_STASHING_DESTINATION
Command structure
Figure 234. DPIO_GET_STASHING_DESTINATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x121 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-27
Response structure
Figure 235. DPIO_GET_STASHING_DESTINATION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x121 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 8 7 0
0x08 — SDEST
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 SDEST stashing destination value
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-28
9.2.20 DPIO_ADD_STATIC_DEQUEUE_CHANNEL
Command structure
Figure 236. DPIO_ADD_STATIC_DEQUEUE_CHANNEL Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x122 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — DPCON_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPCON_ID DPCON object ID
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-29
Response structure
Figure 237. DPIO_ADD_STATIC_DEQUEUE_CHANNEL Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x122 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 8 7 0
0x08 — CHANNEL_INDEX
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 CHANNEL_INDEX Returned channel index to be used in qbman API
DPIO: Data Path I/O
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 9-30
9.2.21 DPIO_REMOVE_STATIC_DEQUEUE_CHANNEL
Command structure
Figure 238. DPIO_REMOVE_STATIC_DEQUEUE_CHANNEL Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x123 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — DPCON_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPCON_ID DPCON object ID
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-1
Chapter 10 DPCON: Data Path ConcentratorThe DPCON object provides advanced scheduling of ingress packets, including scheduling between different network interfaces. It enables advanced scheduling options for ingress traffic coming from one or more network interfaces, and provides better flexibility for the GPP software to handle received packets. The use of DPCON objects is optional – it is not required for basic receive operations; refer to the DPNI section for more information on the relationship between DPNI and DPCON.
10.1 DPCON featuresThe following list summarizes the DPCON main features and capabilities:
• Supports configuration of QBMan channels for advanced scheduling of ingress packets from one or more network interfaces
• Supports up to eight scheduling priorities; having a DPCON object with multiple priorities, for example, allows for different priorities to be set for the receive queues of two different DPNI objects
• Supports data availability notifications through a selected DPIO object
• Supports enable, disable, and reset operations
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-2
10.2 DPCON command referenceThis section contains the detailed programming model of DPCON commands.
10.2.1 DPCON_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPCON_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
The command format is shown in the figure below.
Figure 239. DPCON_OPEN Command Description
The following table describes the command fields.1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x808 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPCON_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 16. DPCON_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPCI_ID
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-3
10.2.2 DPCON_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 240. DPCON_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 - 0x38
Reserved
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-4
10.2.3 DPCON_CREATE
This command creates and initializes an instance of DPCON according to the specified command parameters. This command is not required for DPCON instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 241. DPCON_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x908 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 8 7 0
0x08 — NUM_PRIORITIES
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 17. DPCON_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 NUM_PRIORITIES Number of priorities for the DPCON channel (1-8)
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-5
10.2.4 DPCON_DESTROY
Command structure
Figure 242. DPCON_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-6
10.2.5 DPCON_ENABLE
Command structure
Figure 243. DPCON_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-7
10.2.6 DPCON_DISABLE
Command structure
Figure 244. DPCON_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-8
10.2.7 DPCON_IS_ENABLED
Command structure
Figure 245. DPCON_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-9
Response structure
Figure 246. DPCON_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-10
10.2.8 DPCON_RESET
Command structure
Figure 247. DPCON_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-11
10.2.9 DPCON_SET_IRQ
Set IRQ information for the DPCON to trigger an interrupt.
Command structure
Figure 248. DPCON_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-12
10.2.10 DPCON_GET_IRQ
Get IRQ information from the DPCON.
Command structure
Figure 249. DPCON_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-13
Response structure
Figure 250. DPCON_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-14
10.2.11 DPCON_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 251. DPCON_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-15
10.2.12 DPCON_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 252. DPCON_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-16
Response structure
Figure 253. DPCON_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-17
10.2.13 DPCON_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 254. DPCON_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-18
10.2.14 DPCON_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 255. DPCON_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-19
Response structure
Figure 256. DPCON_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-20
10.2.15 DPCON_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 257. DPCON_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPCON_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-21
Response structure
Figure 258. DPCON_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-22
10.2.16 DPCON_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 259. DPCON_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-23
10.2.17 DPCON_GET_ATTRIBUTES
Command structure
Figure 260. DPCON_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-24
Response structure
Figure 261. DPCON_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 32 31 0
0x08 — NUM_PRIORITIES
QBMAN_CH_ID ID
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 0
0x18 —
63 0
0x20 —
63
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID DPCON object ID
32-47 QBMAN_CH_ID Channel ID to be used by dequeue operation
48-55 NUM_PRIORITIES Number of priorities for the DPCON channel (1-8)
0x10 0-15 VERSION_MAJOR DPCON major version
16-31 VERSION_MINOR DPCON minor version
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-25
10.2.18 DPCON_SET_NOTIFICATION
Command structure
Figure 262. DPCON_SET_NOTIFICATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x100 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 — PRIORITY DPIO_ID
63 0
0x10 USER_CTX
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPIO_ID DPIO object ID; must be configured with a notification channel
32-39 PRIORITY Priority selection within the DPIO channel; valid valuesare 0-7, depending on the number of priorities in that channel
0x10 0-63 USER_CTX User context value provided with each CDAN message
DPCON: Data Path Concentrator
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 10-26
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-1
Chapter 11 DPCI: Data Path Communication InterfaceThe MC exports a generic interface for inter-partition communication (IPC). The DPCI enables frame-based communication between different software contexts, utilizing the DPAA2 QBMan infrastructure. The communication protocol is completely free, unlike DPNI, which is a standard network interface. DPCI objects may be connected in pairs (one DPCI in each software context) to form a communication link. This type of communication may serve basic management/control needs between GPP software and AIOP software, or between two separate GPP software contexts.
Please refer to the API book for complete reference of available functions.
11.1 DPCI featuresThe following list summarizes the DPCI main features and capabilities:
• Supports up to two scheduling priorities for outgoing frames.
• Supports up to two scheduling priorities for incoming frames.
• Allows interaction with one or more Data Path I/O (DPIO) objects for dequeueing/enqueueing frame descriptors (FD) and for acquiring/releasing buffers.
• Supports different scheduling options for processing received packets:
— Queues can be configured either in ‘parked’ mode (default), or attached to a DPIO object, or attached to DPCON object
• Supports link state indication – a communication link is active only when both DPCI objects are initialized and enabled.
• Supports enable, disable, and reset operations
11.2 DPCI functional description
11.2.1 Connecting DPCI objects
The communication channel consists of two DPCI objects, each on a different software context. Each DPCI object owns up to two receive queues, matching the number of priorities requested when the object was created. The two objects should be connected using either DPL declaration or through DPRC CONNECT operation. The connection (link) will be in an active state (‘link up’) only after both DPCI objects are enabled. Once the link is up, each software context may query the DPCI attributes to find the queue IDs that should be used in enqueue and dequeue operations.
11.2.2 Relationship with DPIO and DPCON objects
Each of the two DPCI receive queues may be associated with either a DPIO object or a DPCON object. This serves for notification purposes and/or advanced scheduling of received frames.
DPIO objects provide configuration of a QBMan software portal, with an option for data availability notifications. GPP software is free to relate DPIO objects to threads, or to share them between cores in SMP mode but this requires synchronized access to the QBMan software portal. It is possible to associate
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-2
multiple DPIO objects with the same DPCI, in order to spread traffic from this DPCI across multiple QBMan software portals.
GPP software may decide to enable DPIO notifications, or it may dequeue frames based on its own scheduled polling logic. It is also possible for one GPP entity to receive the notification from one DPIO and alert another entity that will dequeue the packets using a different DPIO.
DPCON objects are used for concentrating traffic from several interfaces into sub-interfaces, mainly for scheduling purposes. It is possible to connect DPCON with DPIO so it generates notifications to the GPP.
Note that the QBMan software portal is used both for enqueue/dequeue operations on packets, and for acquire/release buffer operations. GPP software is responsible for the portal’s operation mode and usage i.e. sharing vs. affinity, association of queue context, etc.
DPIO objects may serve multiple interfaces. This is not limited to multiple DPCI objects; it can also be extended to network interfaces and accelerator interfaces. For example, the same DPIO may serve both a DPNI and a DPCI, assuming they are assigned to the same software context (container).
11.2.3 Buffer requirements
A DPCI does not need to be associated with a DPBP object; in addition, buffers for the communication messages (frames) may or may not be managed by buffer pools. However, these buffers must be shared by the two communicating software contexts, as the communication channel does not involve copying of the frame.
11.3 DPCI command referenceThis section contains detailed programming model of DPCI commands.
11.3.1 DPCI_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPCI_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-3
Command structure
The command format is shown in the figure below.
Figure 263. DPCI_OPEN Command Description
The following table describes the command fields.1-
11.3.2 DPCI_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x807 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPCI_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 18. DPCI_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPCI_ID DPCI unique ID
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-4
Command structure
Figure 264. DPCI_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-5
11.3.3 DPCI_CREATE
This command creates and initializes an instance of DPCI according to the specified command parameters. This command is not required for DPCI instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 265. DPCI_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x907 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 8 7 0
0x08 — NUM_OF_PRIORITIES
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 19. DPCI_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 NUM_OF_PRIORITIES Number of receive priorities (queues) for the DPCI; note, that the number of transmit priorities (queues) is determined by the number of receive priorities of the peer DPCI object
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-6
11.3.4 DPCI_DESTROY
Command structure
Figure 266. DPCI_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-7
11.3.5 DPCI_ENABLE
Command structure
Figure 267. DPCI_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-8
11.3.6 DPCI_DISABLE
Command structure
Figure 268. DPCI_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-9
11.3.7 DPCI_IS_ENABLED
Command structure
Figure 269. DPCI_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-10
Response structure
Figure 270. DPCI_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-11
11.3.8 DPCI_RESETCommand structure
Figure 271. DPCI_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-12
11.3.9 DPCI_SET_IRQ
Set IRQ information for the DPCI to trigger an interrupt.
Command structure
Figure 272. DPCI_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-13
11.3.10 DPCI_GET_IRQ
Get IRQ information from the DPCI.
Command structure
Figure 273. DPCI_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-14
Response structure
Figure 274. DPCI_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-15
11.3.11 DPCI_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 275. DPCI_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-16
11.3.12 DPCI_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 276. DPCI_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-17
Response structure
Figure 277. DPCI_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-18
11.3.13 DPCI_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 278. DPCI_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-19
11.3.14 DPCI_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 279. DPCI_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-20
Response structure
Figure 280. DPCI_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-21
11.3.15 DPCI_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 281. DPCI_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPCI_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-22
Response structure
Figure 282. DPCI_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 0: DPCI_IRQ_EVENT_LINK_CHANGED – indicates a change in the link stateBit 1: DPCI_IRQ_EVENT_CONNECTED – indicates a peer was connectedBit 2: DPCI_IRQ_EVENT_DISCONNECTED – indicates a peer was disconnected
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-23
11.3.16 DPCI_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 283. DPCI_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-24
11.3.17 DPCI_GET_ATTRIBUTES
Command structure
Figure 284. DPCI_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-25
Response structure
Figure 285. DPCI_GET_ATTRIBUTES Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 32 31 0
0x08 — NUM_OF_PRIORITIES
— ID
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 48 47 32 31 0
0x18 —
63 48 47 0
0x20 —
63 0
0x28 —
63 32 31 16 15 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID DPCI object ID
48-55 NUM_OF_PRIORITIES Number of receive priorities
0x10 0-15 VERSION_MAJOR DPCI major version
16-31 VERSION_MINOR DPCI minor version
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-26
11.3.18 DPCI_GET_PEER_ATTRIBUTES
Command structure
Figure 286. DPCI_GET_PEER_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-27
Response structure
Figure 287. DPCI_GET_PEER_ATTRIBUTES Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 — NUM_OF_PRIORITIES PEER_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 PEER_ID DPCI peer ID; if no peer is connected returns (-1)
32-39 NUM_OF_PRIORITIES The peer's number of receive priorities; determines thenumber of transmit priorities for the local DPCI object
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-28
11.3.19 DPCI_GET_LINK_STATE
Command structure
Figure 288. DPCI_GET_LINK_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-29
Response structure
Figure 289. DPCI_GET_LINK_STATE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — UP
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 UP Returned link state; returns '1' if link is up, '0' otherwise
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-30
11.3.20 DPCI_SET_RX_QUEUE
Command structure
Figure 290. DPCI_SET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — TYPE PRIORITY DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 0
0x18 — OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel; valid valuesare 0-1 or 0-7, depending on the number of priorities in thatchannel; not relevant for 'DPCI_DEST_NONE' option
40-47 PRIORITY Select the queue relative to number of priorities configured at DPCI creation; use DPCI_ALL_QUEUES to configure all Rx queuesidentically.
48-51 DEST_TYPE Destination type:0x0 = DPCI_DEST_NONE - Unassigned destination; The queue is set in parked mode and does not generate FQDAN notifications; user is expected to dequeue from the queue based on polling or other user-defined method0x1 = DPCI_DEST_DPIO- The queue is set in schedule mode and generates FQDAN notifications to the specified DPIO; user is expected to dequeue from the queue only after notification is received0x2 = DPCI_DEST_DPCON - The queue is set in schedule mode and does not generate FQDAN notifications, but is connected to the specified DPCON object; user is expected to dequeue from the DPCON channel
0x10 0-63 USER_CTX User context value provided in the frame descriptor of eachdequeued frame;valid only if 'DPCI_QUEUE_OPT_USER_CTX' is contained in 'options'
0x18 0-32 OPTIONS Flags representing the suggested modifications to the queue;Use any combination of 'DPCI_QUEUE_OPT_<X>' flags:bit 0: DPCI_QUEUE_OPT_USER_CTX - Select to modify the user's context associated with the queuebit 1: DPCI_QUEUE_OPT_DEST - Select to modify the queue's destination
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-31
11.3.21 DPCI_GET_RX_QUEUE
Command structure
Figure 291. DPCI_GET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 0
0x08 — PRIORITY —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 40-47 PRIORITY Select the queue relative to number of priorities configured at DPCI creation
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-32
Response structure
Figure 292. DPCI_GET_RX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — DEST_TYPE
— DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 0
0x18 FQID
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 PRIORITY Priority selection within the DPIO or DPCON channel; valid valuesare 0-1 or 0-7, depending on the number of priorities in thatchannel; not relevant for 'DPCI_DEST_NONE' option
48-51 DEST_TYPE Destination type
0x10 0-63 USER_CTX User context value provided in the frame descriptor of eachdequeued frame
0x18 32-63 FQID Virtual FQID value to be used for dequeue operations
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-33
11.3.22 DPCI_GET_TX_QUEUE
Command structure
Figure 293. DPCI_GET_TX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPCI: Data Path Communication Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 11-34
Response structure
Figure 294. DPCI_GET_TX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0E4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 FQID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 FQID Virtual FQID to be used for sending frames to peer DPCI;returns 'DPCI_FQID_NOT_VALID' if a no peer is connected or ifthe selected priority exceeds the number of priorities of thepeer DPCI object
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-1
Chapter 12 DPDMUX: Data Path Network DeMuxThe DPDMUX object provides the functionality of Ethernet virtual bridging, based mainly on 802.1Qbg standard. The major role of the DPDMUX is forwarding traffic from a single uplink interface to one or more internal interfaces. The uplink interface can be an internal or external interface.
DPDMUX forwarding is decided by an internal database which classifies the received frames and sends them to either the uplink interface or to the internal interfaces. The DPDMUX database can be updated dynamically at run-time. DPDMUX does not support automatic learning from network traffic, however it does learn MAC addresses and VLAN IDs from connected DPNI objects. There is no aging mechanism support for database entries.
12.1 DPDMUX featuresThe following list summarizes the DPDMUX main features and capabilities:
• Supports 802.1Qbg configurations such as VEB and VEPA
• Splits ingress traffic from one uplink interface to multiple internal interfaces (DPNIs)
• Supports VM-to-VM bridging (VEB configuration mode)
• Supports the following demux methods:
— Split traffic by destination MAC address (DMAC)
— Split traffic by C-VLAN
— Split traffic by DMAC and C-VLAN combined
• Configurable number of demux table entries
• Support Unicast, Multicast and Broadcast frames, including Unicast and Multicast promiscuous modes for the internal interfaces.
• Supports the following frame acceptance policies per interface:
— All frames are accepted (default behavior)
— Only tagged frames are accepted
— Only untagged (or priority-tagged) frames are accepted
• Statistics counters per interface
• Link state indication per interface (interrupt GPP on change)
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-2
12.2 DPDMUX functional description
12.2.1 Demux database
DPDMUX forwarding is decided by an internal database which classifies received frames and sends them to either the uplink interface or to the internal interfaces.
DPDMUX database can be updated dynamically through two main mechanisms:
• Interface learning – DPDMUX automatically queries DPNI objects after they are connected to its internal interfaces, and automatically configures the forwarding database with the matching MAC/VLAN rules according to the selected demux method. The information received from DPNI includes MAC filters (Unicast and Multicast), VLAN filters and promiscuous settings. Rules that were configured based on this mechanism are removed once the DPNI object is disconnected from the DPDMUX interface.
• Management configuration – The DPDMUX user (GPP driver) may add (or remove) forwarding rules directly through DPDMUX commands. Please refer to the DPDMUX_IF_ADD/REMOVE_L2_RULE commands for more details. Rules that were configured through management commands can only be removed by management commands, so connecting/disconnecting DPNI objects have no impact on such rules.
DPDMUX does not support automatic learning from network traffic. Frames that cannot be matched with any rule are either dropped or redirected to a selected interface.
There is no automatic aging support for database entries.
12.2.2 Broadcast and multicast support
Ethernet broadcast and multicast frames are replicated to the relevant interfaces. Replication is supported only when the demux method is based on MAC addresses (or MAC and VLAN). If the demux method is set to use both MAC and VLAN, then replication is limited to the scope of the VLAN ID that is found in the frame (frames do not cross VLAN boundaries).
Note, that if the demux method is not configured to use MAC address, frames are never replicated.
12.2.3 Promiscuous interfaces
As mentioned, the DPDMUX queries connected DPNI objects for their settings. If a DPNI is configured in promiscuous mode (Unicast or Multicast), then it will receive all frames that did not match the MAC address in any of the existing rules. Frames that match an existing rule are not forwarded to promiscuous interfaces. When the demux method is set to use both MAC and VLAN, then frames replication to promiscuous interfaces is limited to the scope of the VLAN ID that is found in the frame (frames do not cross VLAN boundaries).
Note, that if the demux method is not configured to use MAC address, frames are never replicated.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-3
12.2.4 Frames acceptance policy
The frames acceptance policy can be configured for each of the DPDMUX interfaces. Note, that the acceptance policy is applied before a frame is matched against the demux database.
Valid acceptance policies are:
• Admit all – The DPDMUX interface accepts all valid Ethernet frames (tagged, untagged and priority-tagged frames).
• Admit only tagged – The DPDMUX interface accepts only VLAN-tagged Ethernet frames.
• Admit only untagged – The DPDMUX interface accepts only untagged Ethernet frames and priority-tagged Ethernet frames (VLAN ID = 0).
For each interface, the user may select an action to apply on unaccepted frames – either drop the frame or redirect it to control interface.
Please refer to DPDMUX_IF_SET_ACCEPTED_FRAMES command.
12.3 DPDMUX command referenceThis section contains detailed programming model of DPDMUX commands.
12.3.1 DPDMUX_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPDMUX_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-4
Command structure
Figure 295. DPDMUX_OPEN Command Description
The following table describes the command fields.1-
12.3.2 DPDMUX_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x80B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPDMUX_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 20. DPDMUX_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPDMUX_ID DPDMUX unique ID
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-5
Command structure
Figure 296. DPDMUX_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
12.3.3 DPDMUX_CREATE
This command creates and initializes an instance of DPDMUX according to the specified command parameters. This command is not required for DPDMUX instances that are created using the DPL.
The command format is shown in the figure below.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-6
Command structure
Figure 297. DPDMUX_CREATE Command Description
The following table describes the command fields.
1-5
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x906 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 8 7 0
0x08 – NUM_IFS MANIP METHOD
63 32 31 16 15 0
0x10 — MAX_VLAN_IDS MAX_MC_GROUPS MAX_DMAT_ENTRIES
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 METHOD Defines the operation method for the DPDMUX address table. select one of the supported values below:0x1 = DPDMUX_METHOD_C_VLAN_MAC: DPDMUX based on C-VLAN and MAC address0x2 = DPDMUX_METHOD_MAC: DPDMUX based on MAC address0x3 = DPDMUX_METHOD_C_VLAN: DPDMUX based on C-VLAN0x4 = DPDMUX_METHOD_S_VLAN: DPDMUX based on S-VLAN
8-15 MANIP Required manipulation operation. select one of the supported values below:0x0 = DPDMUX_MANIP_NONE: No manipulation on frames0x1 = DPDMUX_MANIP_ADD_REMOVE_S_VLAN: Add S-VLAN on egress, remove it on ingress
16-31 NUM_IFS Number of interfaces (excluding the uplink interface)
0x10 0-15 MAX_DMAT_ENTRIES Maximum entries in DPDMUX address table0- indicates default: 64 entries multiplied by number of interfaces
16-31 MAX_MC_GROUPS Number of multicast groups in DPDMUX table0 - indicates default: 32 multicast groups
32-47 MAX_VLAN_IDS Maximum VLANs allowed in the system – relevant only for METHOD=DPDMUX_METHOD_C_VLAN_MAC.0 - indicates default of 16 VLANs.
0x18 0-63 OPTIONS DPDMUX options - combination of 'DPDMUX_OPT_<X>' flags.Select any combination of supported options below:bit 1: DPDMUX_OPT_BRIDGE_EN - Enable bridging between internal interfaces; allowed only if METHOD is either DPDMUX_METHOD_C_VLAN_MAC or DPDMUX_METHOD_MAC.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-7
12.3.4 DPDMUX_DESTROY
Command structure
Figure 298. DPDMUX_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-8
12.3.5 DPDMUX_ENABLE
Command structure
Figure 299. DPDMUX_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-9
12.3.6 DPDMUX_DISABLE
Command structure
Figure 300. DPDMUX_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-10
12.3.7 DPDMUX_IS_ENABLED
Command structure
Figure 301. DPDMUX_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-11
12.3.8 DPDMUX_RESET
Command structure
Figure 302. DPDMUX_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-12
12.3.9 DPDMUX_SET_IRQ
Set IRQ information for the DPDMUX to trigger an interrupt.
Command structure
Figure 303. DPDMUX_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-13
12.3.10 DPDMUX_GET_IRQ
Get IRQ information from the DPDMUX.
Command structure
Figure 304. DPDMUX_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-14
Response structure
Figure 305. DPDMUX_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-15
12.3.11 DPDMUX_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 306. DPDMUX_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-16
12.3.12 DPDMUX_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 307. DPDMUX_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-17
Response structure
Figure 308. DPDMUX_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-18
12.3.13 DPDMUX_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 309. DPDMUX_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-19
12.3.14 DPDMUX_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 310. DPDMUX_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-20
Response structure
Figure 311. DPDMUX_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-21
12.3.15 DPDMUX_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 312. DPDMUX_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPDMUX_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-22
Response structure
Figure 313. DPDMUX_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask (bits 0-15), one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 0: DPDMUX_IRQ_EVENT_LINK_CHANGED – indicates a change in the link stateBits 16-31 contain the DPDMUX interface ID associated with the event.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-23
12.3.16 DPDMUX_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 314. DPDMUX_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-24
12.3.17 DPDMUX_GET_ATTRIBUTES
Command structure
Figure 315. DPDMUX_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-25
Response structure
Figure 316. DPDMUX_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 16 15 8 7 0
0x08 — MEM_SIZE NUM_IFS MANIP METHOD
63 0
0x10 —
63 32 31 0
0x18 — ID
63 0
0x20 OPTIONS
63 32 31 16 15 0
0x28 — VERSION_MINOR VERSION_MAJOR
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 METHOD DPDMUX address table method. One of the supported values below:1 = DPDMUX_METHOD_C_VLAN_MAC - DPDMUX based on C-VLAN and MAC address2 = DPDMUX_METHOD_MAC - DPDMUX based on MAC address3 = DPDMUX_METHOD_C_VLAN - DPDMUX based on C-VLAN4 = DPDMUX_METHOD_S_VLAN - DPDMUX based on S-VLAN
8-15 MANIP DPDMUX manipulation type. One of the supported values below:0 = DPDMUX_MANIP_NONE - No manipulation on frames1 = DPDMUX_MANIP_ADD_REMOVE_S_VLAN - Add S-VLAN on egress, remove it on ingress
16-31 NUM_IFS Number of interfaces (excluding the uplink interface)
32-47 MEM_SIZE DPDMUX frame storage memory size
0x18 0-31 ID DPDMUX object ID
0x20 0-63 OPTIONS Configuration options (bitmap). Any combination of supported options below: bit 1: DPDMUX_OPT_BRIDGE_EN - Enable bridging between internal interfaces
0X28 0-15 VERSION_MAJOR DPDMUX major version
16-31 VERSION_MINOR DPDMUX minor version
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-26
12.3.18 DPDMUX_UL_SET_MAX_FRAME_LENGTH
Command structure
Figure 317. DPDMUX_UL_SET_MAX_FRAME_LENGTH Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — MAX_FRAME_LENGTH
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 MAX_FRAME_LENGTH The required maximum frame length
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-27
12.3.19 DPDMUX_IF_SET_ACCEPTED_FRAMES
Command structure
Figure 318. DPDMUX_IF_SET_ACCEPTED_FRAMES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A7 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 24 23 20 19 16 15 0
0x08 — UNACCEPT_A
CT
TYPE IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID (0 for uplink, or 1-num_ifs);
16-19 TYPE Defines ingress accepted frames. Select one of the supported values below:0x0 = DPDMUX_ADMIT_ALL - The device accepts VLAN tagged, untagged andpriority-tagged frames0x1 = DPDMUX_ADMIT_ONLY_VLAN_TAGGED - The device discards untagged frames or priority-tagged frames that are received on this interface0x2 = DPDMUX_ADMIT_ONLY_UNTAGGED - Untagged frames or priority-tagged frames received on this interface are accepted
20-23 UNACCEPT_ACT Defines action on frames not accepted. Select one of the supported values below:0x0 = DPDMUX_ACTION_DROP: Drop un-accepted frames0x1 = DPDMUX_ACTION_REDIRECT_TO_CTRL: Redirect un-accepted frames to the control interface
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-28
12.3.20 DPDMUX_IF_GET_ATTRIBUTES
Command structure
Figure 319. DPDMUX_IF_GET_ATTR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A8 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID (0 for uplink, or 1-num_ifs);
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-29
Response structure
Figure 320. DPDMUX_IF_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A8 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 60 59 56 55 26 25 24 23 0
0x08 —
AC
CE
PT
_FR
AM
E_T
YP
E
—
IS_D
EFA
ULT
EN —
63 0
0x10 RATE
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 24 ENABLED Indicates if interface is enabled
25 IS__DEFAULT Indicates if configured as default interface
56-59 ACCEPT_FRAME_TYPE Indicates type of accepted frames for the interface. Select one of the supported values below:0x0 = DPDMUX_ADMIT_ALL - The device accepts VLAN tagged, untagged andpriority-tagged frames0x1 = DPDMUX_ADMIT_ONLY_VLAN_TAGGED - The device discards untagged frames or priority-tagged frames that are received on this interface0x2 = DPDMUX_ADMIT_ONLY_UNTAGGED - Untagged frames or priority-tagged frames received on this interface are accepted
0x10 0-63 RATE Configured interface rate (in bits per second)
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-30
12.3.21 DPDMUX_IF_REMOVE_L2_RULE
Command structure
Figure 321. DPDMUX_IF_REMOVE_L2_RULE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 IF_ID
63 48 47 32 31 0
0x10 — VLAN_ID —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Destination interface ID
16-63 MAC_ADDR[0-5] MAC address
0x10 32-47 VLAN_ID VLAN ID
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-31
12.3.22 DPDMUX_IF_ADD_L2_RULE
Command structure
Figure 322. DPDMUX_IF_ADD_L2_RULE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 IF_ID
63 48 47 32 31 0
0x10 — VLAN_ID —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Destination interface ID
16-63 MAC_ADDR[0-5] MAC address
0x10 32-47 VLAN_ID VLAN ID
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-32
12.3.23 DPDMUX_IF_GET_COUNTER
Command structure
Figure 323. DPDMUX_IF_GET_COUNTER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 24 23 16 15 0
0x08 — COUNTER_TYPE
IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-23 COUNTER_TYPE Counter type
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-33
Response structure
Figure 324. DPDMUX_IF_GET_COUNTER Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 COUNTER
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 COUNTER Returned specific counter information
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-34
12.3.24 DPDMUX_UL_RESET_COUNTERS
Command structure
Figure 325. DPDMUX_IF_RESET_COUNTERS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-35
12.3.25 DPDMUX_IF_SET_LINK_CFG
Command structure
Figure 326. DPDMUX_IF_SET_LINK_CFG Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 RATE
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
0x10 0-63 RATE Rate
0x18 0-63 OPTIONS Mask of available options; use ‘DPDMUX_LINK_OPT_<x>’ values
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-36
12.3.26 DPDMUX_IF_GET_LINK_STATE
Command structure
Figure 327. DPDMUX_IF_GET_LINK_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-37
Response structure
Figure 328. DPDMUX_IF_GET_LINK_STATE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0B4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 33 32 31 0
0x08 — UP —
63 0
0x10 RATE
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32 UP 0 - down, 1 - up
0x10 0-63 RATE Rate
0x18 0-63 OPTIONS Mask of available options; use ‘DPDMUX_LINK_OPT_<x>’ values
DPDMUX: Data Path Network DeMux
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 12-38
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-1
Chapter 13 DPSW: Data Path L2 SwitchThe DPSW object provides the functionality of a general layer-2 switch. It receives packets on one port and sends them on another. It can also send packets out on multiple ports for the purposes of broadcast, multicast, or mirroring.
13.1 DPSW featuresThe following list summarizes the DPSW main features and capabilities:
• Supports 802.1Q switching:
— Forwarding based on (outer) VLAN and MAC address
— Forwarding of L2 unicast, multicast and broadcast frames
• Supports connections to DPMAC and DPNI
• Supports separate MAC table (FDB) per VLAN
• Supports sharing of FDB between multiple VLANs
• Supports flooding (configuration per VLAN)
• Supports three address learning modes, selected per FDB:
— Automatic learning by the switch hardware
— Secure learning by host GPP software
— Non-secure learning by host GPP software
• Supports port-based VLAN – definition of default VLAN per interface
• Supports untagged frames transmission (configuration per VLAN/interface)
• Supports untagged frames admittance:
— Admit tagged and untagged frames
— Admit only tagged frames
• Supports VLAN filtering – dropping frames with unregistered VLANs
• Supports trunk interface – accepting all VLANs (configurtion per interface)
• Supports two custom TPIDs per switch
• Supports interface mirroring, with option to mirror only specific VLAN
— One mirroring destination interface per VLAN
• Supports STP/RSTP/MSTP marking (Spanning Tree Protocol handled by host GPP software)
• Supports QoS capabilities:
— Traffic class selection based on DSCP or 802.1P
— Supports transmission bandwidth allocation per traffic class
— Supports transmission rate configuration per interface
— Supports WRED on ingress (configuration per traffic class)
• Supports policy-based forwarding on ingress:
— TCAM lookup with keys formed of L2-L4 fields
• Supports forwarding of selective protocols to a control interface, for example:
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-2
— Ethernet monitoring packets (IEEE 802.3 clause 57, IEEE 802.1ag, ITU-T Y.1731)
— Multicast groups management packets (IGMP/MLD)
— Spanning Tree Protocol packets (BPDU)
• Supports statistics counters per interface
• Supports link state indication per interface
• Supports interrupts to host GPP software:
— Link change events (per interface)
• Supports switch enable, disable, and reset operations
• Supports interface enable and disable operations
13.2 DPSW functional description
13.2.1 Creating L2 switch instance
The DPSW may be declared in the DPL (Data Path Layout) file or created dynamically by submitting explicit DPSW_CREATE command to the Management Complex. The DPSW has only one mandatory input for creating a working L2 switch instance, and that is the requested number of switch interfaces. Other configuration options are possible but have default settings for simplicity.
The default operation mode for a DPSW (unless requetsed otherqise in DPSW creation) is with a default VLAN (VID = 1), a single Forwardimg Data Base (FDB 0) and with automatic learning enabled in hardware. This implies that the switch is fully functional after creation, and user only needs to connect each of its interfaces to either DPMAC objects or DPNI objects. Connections can be made initially in the DPL or later through DPRC object.
13.2.2 VLAN configuration
The switch starts up with VLAN 1 being configured as default VLAN. All untagged traffic received on any switch port is classified to VLAN 1 and all frames classified in VLAN 1 are sent out untagged on all ports.
The DPSW allows to add (and remove) other VLANs at any time. Each VLAN can include any subset of the switch ports.
13.2.3 Learning modes
The default configuration of the switch enables automatic learning by the switch hardware. It is possible to set Secure or Unsecure CPU learning modes instead of automatic learning. The leraning mode is configurable per FDB.
The table below summarizes the differences between the two CPU learning modes. These modes require that one of the switch interfaces is defined as control interface.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-3
Note that turning off automatic learning does not remove the learned entries. Therefore, learning should be disabled before injecting any traffic if the intent is to establish a static topology.
13.2.4 FDB configuration
The default switch configuration does not include any static entries. It is possible to add (and remove) static rules for forwarding to different interfaces based on their MAC addresses.
The user may select to use a separate FDB per VLAN or decide to share FDBs between different VLANs.
13.3 DPSW command referenceThis section contains detailed programming model of DPSW commands.
13.3.1 DPSW_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPSW_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Learning ModeSMAC known
DMAC known
Action
Non-SecureCPU learning
V V Forward to DMAC destination
- V Forward to DMAC destination + control interface
V - Forward to list of flooding-enabled interfaces
- - Forward to list of flooding-enabled interfaces + control interface
SecureCPU learning
V V Forward to DMAC destination
- V Forward to control interface
V - Forward to list of flooding-enabled interfaces
- - Forward to control interface
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-4
Command structure
Figure 329. DPSW_OPEN Command Description
The following table describes the command fields.1-
13.3.2 DPSW_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x802 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPSW_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 21. DPSW_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPSW_ID DPSW unique ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-5
Command structure
Figure 330. DPSW_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
13.3.3 DPSW_CREATE
This command creates and initializes an instance of DPSW according to the specified command parameters. This command is not required for DPSW instances that are created using the DPL.
The command format is shown in the figure below.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-6
Command structure
Figure 331. DPSW_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x902 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 24 23 16 15 0
0x08 — MAX_METERS_PER_IF
MAX_FDBS NUM_IFS
63 48 47 32 31 16 15 0
0x10 MAX_FDB_MC_GROUPS FDB_AGING_TIME MAX_FDB_ENTRIES MAX_VLANS
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 22. DPSW_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 NUM_IFS Number of external and internal interfaces
16-23 MAX_FDBS Maximum number of FDB’s; 0 - indicates default 16
24-31 MAX_METERS_PER_IF Number of meters per interface
0x10 0-15 MAX_VLANS Maximum number of VLAN’s; 0 - indicates default 16
16-31 MAX_FDB_ENTRIES Number of FDB entries for default FDB table;0 - indicates default 1024 entries.
32-47 FDB_AGING_TIME Default FDB aging time for default FDB table;0 - indicates default 300 seconds
48-63 MAX_FDB_MC_GROUPS Number of multicast groups in each FDB table;0 - indicates default 32
0x18 0-63 OPTIONS Enable/Disable DPSW features (bitmap). Select any combination of supported errors below:bit 0: DPSW_OPT_FLOODING_DIS - Disable floodingbit 1: DPSW_OPT_BROADCAST_DIS - Disable Broadcastbit 2: DPSW_OPT_MULTICAST_DIS - Disable Multicastbit 3: DPSW_OPT_TC_DIS - Disable Traffic classesbit 4: DPSW_OPT_CONTROL - Support control interface
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-7
13.3.4 DPSW_DESTROY
Command structure
Figure 332. DPSW_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-8
13.3.5 DPSW_ENABLE
Command structure
Figure 333. DPSW_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-9
13.3.6 DPSW_DISABLE
Command structure
Figure 334. DPSW_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-10
13.3.7 DPSW_IS_ENABLED
Command structure
Figure 335. DPSW_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-11
Response structure
Figure 336. DPSW_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-12
13.3.8 DPSW_RESET
Command structure
Figure 337. DPSW_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-13
13.3.9 DPSW_SET_IRQ
Set IRQ information for the DPSW to trigger an interrupt.
Command structure
Figure 338. DPSW_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-14
13.3.10 DPSW_GET_IRQ
Get IRQ information from the DPSW.
Command structure
Figure 339. DPSW_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-15
Response structure
Figure 340. DPSW_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-16
13.3.11 DPSW_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 341. DPSW_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-17
13.3.12 DPSW_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 342. DPSW_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-18
Response structure
Figure 343. DPSW_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-19
13.3.13 DPSW_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 344. DPSW_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-20
13.3.14 DPSW_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 345. DPSW_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-21
Response structure
Figure 346. DPSW_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-22
13.3.15 DPSW_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 347. DPSW_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPSW_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-23
Response structure
Figure 348. DPSW_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask (bits 0-15), one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 0: DPDMUX_IRQ_EVENT_LINK_CHANGED – indicates a change in the link stateBits 16-31 contain the DPDMUX interface ID associated with the event.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-24
13.3.16 DPSW_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 349. DPSW_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-25
13.3.17 DPSW_GET_ATTRIBUTES
Command structure
Figure 350. DPSW_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-26
Response structure
Figure 351. DPSW_GET_ATTRIBUTES Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 24 23 16 15 0
0x08 NUM_VLANS MAX_VLANS NUM_FDBS MAX_FDBS NUM_IFS
63 48 47 32 31 16 15 0
0x10 FDB_AGING_TIME MAX_FDB_ENTRIES VERSION_MINOR VERSION_MAJOR
63 48 47 32 31 0
0x18 MAX_FDB_MC_GROUPS MEM_SIZE ID
63 0
0x20 OPTIONS
63 8 7 0
0x28 — MAX_METERS_PER_IF
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 NUM_IFS Number of interfaces
16-23 MAX_FDBS Maximum Number of FDBs
24-31 NUM_FDBS Current number of FDBs
32-47 MAX_VLANS Maximum Number of VLANs
48-63 NUM_VLANS Current number of VLANs
0x10 0-15 VERSION_MAJOR DPSW major version
16-31 VERSION_MINOR DPSW minor version
32-47 MAX_FDB_ENTRIES Number of FDB entries for default FDB table;0 - indicates default 1024 entries.
48-63 FDB_AGING_TIME Default FDB aging time for default FDB table;0 - indicates default 300 seconds
0x18 0-31 ID DPSW object ID
32-39 MEM_SIZE DPSW frame storage memory size
40-47 MAX_FDB_MC_GROUPS Number of multicast groups in each FDB table;0 - indicates default 32
0x20 0-63 OPTIONS Enable/Disable DPSW features.bit 0: DPSW_OPT_FLOODING_DIS - Disable floodingbit 1: DPSW_OPT_BROADCAST_DIS - Disable Broadcastbit 2: DPSW_OPT_MULTICAST_DIS - Disable Multicastbit 3: DPSW_OPT_TC_DIS - Disable Traffic classesbit 4: DPSW_OPT_CONTROL - Support control interface
0x28 0-7 MAX_METERS_PER_IF Number of meters per interface
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-27
All unspecified fields are reserved and must be cleared (set to zero)
13.3.18 DPSW_SET_REFLECTION_IF
Command structure
Figure 352. DPSW_SET_REFLECTION_IF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x022 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-28
13.3.19 DPSW_IF_SET_FLOODING
Command structure
Figure 353. DPSW_IF_SET_FLOODING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x047 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 17 16 15 0
0x08 — EN IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16 EN 1 - enable, 0 - disable
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-29
13.3.20 DPSW_IF_SET_BROADCAST
Command structure
Figure 354. DPSW_IF_SET_BROADCAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x048 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 19 16 15 0
0x08 — EN IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16 EN 1 - enable, 0 - disable
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-30
13.3.21 DPSW_IF_SET_MULTICAST
Command structure
Figure 355. DPSW_IF_SET_MULTICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x049 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 17 16 15 0
0x08 — EN IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16 EN 1 - enable, 0 - disable
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-31
13.3.22 DPSW_IF_SET_TCI
Command structure
Figure 356. DPSW_IF_SET_TCI Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x030 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 29 28 27 16 15 0
0x08 — PCP DEI
VLAN_ID IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-27 VLAN_ID VLAN Identifier (VID): a 12-bit field specifying the VLANto which the frame belongs. The hexadecimal valuesof 0x000 and 0xFFF are reserved;all other values may be used as VLAN identifiers, allowing upto 4,094 VLANs
28 DEI Drop Eligible Indicator (DEI): a 1-bit field. May be used separately or in conjunction with PCP to indicate frameseligible to be dropped in the presence of congestion
29-31 PCP Priority Code Point (PCP): a 3-bit field which refersto the IEEE 802.1p priority
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-32
13.3.23 DPSW_IF_GET_TCI
Command structure
Figure 357. DPSW_IF_GET_TCI Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x04A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-33
Response structure
Figure 358. DPSW_IF_GET_TCI Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x04A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 32 31 16 15 0
0x08 — PCP DEI VLAN_ID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN Identifier (VID): a 12-bit field specifying the VLANto which the frame belongs. The hexadecimal valuesof 0x000 and 0xFFF are reserved;all other values may be used as VLAN identifiers, allowing upto 4,094 VLANs
32-39 DEI Drop Eligible Indicator (DEI): a 1-bit field. May be usedseparately or in conjunction with PCP to indicate frameseligible to be dropped in the presence of congestion
40-47 PCP Priority Code Point (PCP): a 3-bit field which refersto the IEEE 802.1p priority
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-34
13.3.24 DPSW_IF_SET_STP
Command structure
Figure 359. DPSW_IF_SET_STP Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x031 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 36 35 32 31 16 15 0
0x08 — STATE VLAN_ID IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-31 VLAN_ID VLAN ID STP state
32-35 STATE STP state. Select one of the supported values below:0x0 = DPSW_STP_STATE_BLOCKING - Blocking state 0x1 = DPSW_STP_STATE_LISTENING - Listening state 0x2 = DPSW_STP_STATE_LEARNING - Learning state0x3 = DPSW_STP_STATE_FORWARDING - Forwarding state
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-35
13.3.25 DPSW_IF_SET_ACCEPTED_FRAMES
Command structure
Figure 360. DPSW_IF_SET_ACCEPTED_FRAMES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x032 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 24 23 20 19 16 15 0
0x08 —
UA
CC
EP
T_A
CT
TYPE IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-19 TYPE Defines ingress accepted frames. Select one of the supported values below:0x1 = DPSW_ADMIT_ALL - The device accepts VLAN tagged, untagged and priority tagged frames0x3 = DPSW_ADMIT_ONLY_VLAN_TAGGED - The device discards untagged frames or Priority-Tagged frames received on this interface.
20-23 UNACCEPT_ACT When a frame is not accepted, it may be discarded or redirectedto control interface depending on this mode. Select one of the supported values below:0x0 = DPSW_ACTION_DROP - Drop frame0x1 = DPSW_ACTION_REDIRECT_TO_CTRL - Redirect frame to control interface
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-36
13.3.26 DPSW_SET_IF_ACCEPT_ALL_VLAN
Command structure
Figure 361. DPSW_SET_IF_ACCEPT_ALL_VLAN Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x033 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 —
AC
CE
PT
_ALL
IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16 ACCEPT_ALL Accept or drop frames having different VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-37
13.3.27 DPSW_IF_GET_COUNTER
Command structure
Figure 362. DPSW_IF_GET_COUNTER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x034 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 21 20 16 15 0
0x08 — TYPE IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-20 TYPE Counter type. Select one of the supported values below:0x0 = DPSW_CNT_ING_FRAME- Counts ingress frames 0x1 = DPSW_CNT_ING_BYTE - Counts ingress bytes 0x2 = DPSW_CNT_ING_FLTR_FRAME - Counts filtered ingress frames 0x3 = DPSW_CNT_ING_FRAME_DISCARD - Counts discarded ingress frame 0x4 = DPSW_CNT_ING_MCAST_FRAME- Counts ingress multicast frames 0x5 = DPSW_CNT_ING_MCAST_BYTE- Counts ingress multicast bytes 0x6 = DPSW_CNT_ING_BCAST_FRAME- Counts ingress broadcast frames 0x7 = DPSW_CNT_ING_BCAST_BYTES - Counts ingress broadcast bytes 0x8 = DPSW_CNT_EGR_FRAME - Counts egress frames 0x9 = DPSW_CNT_EGR_BYTE- Counts eEgress bytes 0xa =DPSW_CNT_EGR_FRAME_DISCARD - Counts discarded egress frames
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-38
Response structure
Figure 363. DPSW_IF_GET_COUNTER Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x034 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 COUNTER
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 COUNTER counter return value
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-39
13.3.28 DPSW_IF_SET_COUNTER
Command structure
Figure 364. DPSW_IF_SET_COUNTER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x035 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 21 20 16 15 0
0x08 — TYPE IF_ID
63 0
0x10 COUNTER
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-20 TYPE Counter type. Select one of the supported values below:0x0 = DPSW_CNT_ING_FRAME- Counts ingress frames 0x1 = DPSW_CNT_ING_BYTE - Counts ingress bytes 0x2 = DPSW_CNT_ING_FLTR_FRAME - Counts filtered ingress frames 0x3 = DPSW_CNT_ING_FRAME_DISCARD - Counts discarded ingress frame 0x4 = DPSW_CNT_ING_MCAST_FRAME- Counts ingress multicast frames 0x5 = DPSW_CNT_ING_MCAST_BYTE- Counts ingress multicast bytes 0x6 = DPSW_CNT_ING_BCAST_FRAME- Counts ingress broadcast frames 0x7 = DPSW_CNT_ING_BCAST_BYTES - Counts ingress broadcast bytes 0x8 = DPSW_CNT_EGR_FRAME - Counts egress frames 0x9 = DPSW_CNT_EGR_BYTE- Counts eEgress bytes 0xa =DPSW_CNT_EGR_FRAME_DISCARD - Counts discarded egress frames
0x10 0-63 COUNTER New counter value
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-40
13.3.29 DPSW_IF_SET_TX_SELECTION
Command structure
Figure 365. DPSW_IF_SET_TX_SELECTION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x036 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 19 18 16 15 0
0x08 — PRIORITY_SELECTO
R
IF_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 TC_ID7 TC_ID6 TC_ID5 TC_ID4 TC_ID3 TC_ID2 TC_ID1 TC_ID
63 51 48 47 32 31 20 19 16 15 0
0x18 — TC_SHED1_M
ODE
TC_SCHED1_DELTA_BANDWIDTH — TC_SHED0_M
ODE
TC_SCHED0_DELTA_BANDWIDTH
63 51 48 47 32 31 20 19 16 15 0
0x20 — TC_SHED3_M
ODE
TC_SCHED3_DELTA_BANDWIDTH — TC_SHED2_M
ODE
TC_SCHED2_DELTA_BANDWIDTH
63 51 48 47 32 31 20 19 16 15 0
0x28 — TC_SHED5_M
ODE
TC_SCHED5_DELTA_BANDWIDTH — TC_SHED4_M
ODE
TC_SCHED4_DELTA_BANDWIDTH
63 51 48 47 32 31 20 19 16 15 0
0x30 — TC_SHED7_M
ODE
TC_SCHED7_DELTA_BANDWIDTH — TC_SHED6_M
ODE
TC_SCHED6_DELTA_BANDWIDTH
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-18 PRIORITY_SELECTOR Source for user priority regeneration. Select one of the supported values below:0x0 = DPSW_UP_PCP - Priority Code Point (PCP): a 3-bit field which refers to the IEEE 802.1p priority.0x1 = DPSW_UP_PCP_DEI - Priority Code Point (PCP) combined with Drop Eligible Indicator (DEI)0x2 = DPSW_UP_DSCP - Differentiated services Code Point (DSCP): 6 bit field from IP header
0x10 0-63 TC_ID[0-7] The Regenerated User priority that the incomingUser Priority is mapped to for this interface
0x18- 0x30
0-15/32-47
TC_SHED[0-7]_DELTA_BANDWIDTH weighted Bandwidth in range from 100 to 10000
16-19/ 47-51
TC_SCHED[0-7]_MODE Strict or weight-based scheduling
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-41
13.3.30 DPSW_IF_ADD_REFLECTION
Command structure
Figure 366. DPSW_IF_ADD_REFLECTION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x037 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 34 33 32 31 16 15 0
0x08 — FILTER VLAN_ID IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-31 VLAN_ID VLAN ID to reflect;valid only when filter type is DPSW_INGRESS_VLAN
32-33 FILTER Filter type for frames to reflect. Select one of the supported values below:0x0 = DPSW_REFLECTION_FILTER_INGRESS_ALL - Reflect all frames 0x1 = DPSW_REFLECTION_FILTER_INGRESS_VLAN - Reflect only frames belong to particular VLAN defined by vid parameter
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-42
13.3.31 DPSW_IF_REMOVE_REFLECTION
Command structure
Figure 367. DPSW_IF_REMOVE_REFLECTION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x038 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 34 33 32 31 16 15 0
0x08 — FILTER VLAN_ID IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-31 VLAN_ID VLAN ID to reflect;valid only when filter type is DPSW_INGRESS_VLAN
32-33 FILTER Filter type for frames to reflect. Select one of the supported values below:0x0 = DPSW_REFLECTION_FILTER_INGRESS_ALL - Reflect all frames 0x1 = DPSW_REFLECTION_FILTER_INGRESS_VLAN - Reflect only frames belong to particular VLAN defined by vid parameter
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-43
13.3.32 DPSW_IF_SET_FLOODING_METERING
Command structure
Figure 368. DPSW_IF_SET_FLOODING_METERING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x039 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 28 27 24 23 16 15 0
0x08 CIR UNITS MODE — IF_ID
63 32 31 0
0x10 CBS EIR
63 32 31 0
0x18 — EBS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
24-27 MODE Metering modes. Select one of the supported values below: 0x0 = DPSW_METERING_MODE_NONE: metering disabled0x1 = DPSW_METERING_MODE_RFC2698: RFC 26980x2 = DPSW_METERING_MODE_RFC4115: RFC 4115
28-31 UNITS Metering count. Select one of the supported values below: 0x0 = DPSW_METERING_UNIT_BYTES: count in byte units0x1 = DPSW_METERING_UNIT_FRAMES: count in frame units
32-63 CIR Committed information rate (CIR) in bits/s
0x10 0-31 EIR Excess information rate (EIR) in bits/s
32-63 CBS Committed burst size (CBS) in bytes
0x18 0-31 EBS Excess bust size (EBS) in bytes
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-44
13.3.33 DPSW_IF_SET_METERING
Command structure
Figure 369. DPSW_IF_SET_METERING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x03A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 28 27 24 23 16 15 0
0x08 CIR UNITS MODE TC_ID IF_ID
63 32 31 0
0x10 CBS EIR
63 32 31 0
0x18 — EBS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-23 TC_ID Traffic class ID
24-27 MODE Metering modes. Select one of the supported values below: 0x0 = DPSW_METERING_MODE_NONE: metering disabled0x1 = DPSW_METERING_MODE_RFC2698: RFC 26980x2 = DPSW_METERING_MODE_RFC4115: RFC 4115
28-31 UNITS Metering count. Select one of the supported values below: 0x0 = DPSW_METERING_UNIT_BYTES: count in byte units0x1 = DPSW_METERING_UNIT_FRAMES: count in frame units
32-63 CIR Committed information rate (CIR) in bits/s
0x10 0-31 EIR Excess information rate (EIR) in bits/s
32-63 CBS Committed burst size (CBS) in bytes
0x18 0-31 EBS Excess bust size (EBS) in bytes
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-45
13.3.34 DPSW_IF_SET_EARLY_DROP
Command structure
Figure 370. DPSW_IF_SET_EARLY_DROP Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x03B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 8 7 0
0x08 IF_ID TC_ID —
63 0
0x10 EARLY_DROP_IOVA
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 8-15 TC_ID Traffic class ID
16-31 IF_ID Interface ID
0x10 0-63 EARLY_DROP_IOVA I/O virtual address of 64 bytes;Must be cacheline-aligned and DMA-able memory
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-46
Extension structure
Figure 371. DPSW_IF_SET_EARLY_DROP Extension Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
0x00 TAIL_DROP_THRESHOLD — UN
ITS
DR
OP
_MO
DE
63 8 7 0
0x08 GREEN_DROP_PROBABILITY
63 0
0x10 GREEN_MAX_THRESHOLD
63 0
0x18 GREEN_MIN_THRESHOLD
63 8 7 0
0x20 YELLOW_DROP_PROBABILITY
63 0
0x28 YELLOW_MAX_THRESHOLD
63 0
0x30 YELLOW_MIN_THRESHOLD
Offset Bits Name Description
0x00 0-1 DROP_MODE Drop mode
2-3 UNITS Count units
32-63 TAIL_DROP_THRESHOLD Tail drop threshold
0x08 0-7 GREEN_DROP_PROBABILITY probability for green WRED that a packet will be discarded (1-100,associated with the maximum threshold)
0x10 0-63 GREEN_MAX_THRESHOLD maximum threshold for green WRED hat packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x18 0-63 GREEN_MIN_THRESHOLD minimum threshold for green WRED that packets may be discarded at
0x20 0-7 YELLOW_DROP_PROBABILITY probability for yellow WRED that a packet will be discarded (1-100,associated with the maximum threshold)
0x28 0-63 YELLOW_MAX_THRESHOLD maximum threshold for yellow WRED hat packets may be discarded. Above this threshold all packets are discarded; must be less than 2^39; approximated to be expressed as (x+256)*2^(y-1) due to HW implementation.
0x30 0-63 YELLOW_MIN_THRESHOLD minimum threshold for yellow WRED that packets may be discarded at
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-47
13.3.35 DPSW_ADD_CUSTOM_TPID
Command structure
Figure 372. DPSW_ADD_CUSTOM_TPID Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x024 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 TPID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 TPID An additional tag protocol identifier
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-48
13.3.36 DPSW_REMOVE_CUSTOM_TPID
Command structure
Figure 373. DPSW_REMOVE_CUSTOM_TPID Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x026 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 TPID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 TPID An additional tag protocol identifier
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-49
13.3.37 DPSW_IF_ENABLE
Command structure
Figure 374. DPSW_IF_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x03D — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-50
13.3.38 DPSW_IF_DISABLE
Command structure
Figure 375. DPSW_IF_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x03E — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-51
13.3.39 DPSW_IF_GET_ATTRIBUTES
Command structure
Figure 376. DPSW_IF_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x042 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-52
Response structure
Figure 377. DPSW_IF_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x042 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 24 23 16 15 7 6 5 4 0
0x08 — QDID — NUM_TCS —
AC
CE
PT
_ALL_V
LAN
EN
AB
LED
AD
MIT
_UN
TAG
GE
D
63 32 31 0
0x10 — OPTIONS
63 32 31 0
0x18 — RATE
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-3 ADMIT_UNTAGGED When set to 'DPSW_ADMIT_ONLY_VLAN_TAGGED', the device discardsuntagged frames or priority-tagged frames received on thisinterface;When set to 'DPSW_ADMIT_ALL', untagged frames or priority-tagged frames received on this interface are accepted
4 ENABLED Indicates if interface is enabled
5 ACCEPT_ALL_VLAN The device discards/accepts incoming framesfor VLANs that do not include this interface
16-23 NUM_TCS Number of traffic classes
32-47 QDID QDID value to use when transmitting control frames through this interface
0x10 0-32 OPTIONS Interface configuration options (bitmap)
0x18 0-32 RATE Transmit rate in bits per second
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-53
13.3.40 DPSW_IF_SET_MAX_FRAME_LENGTH
Command structure
Figure 378. DPSW_IF_SET_MAX_FRAME_LENGTH Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x044 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — FRAME_LENGTH IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
16-31 FRAME_LENGTH Maximum Frame Length
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-54
13.3.41 DPSW_IF_SET_LINK_CFG
Command structure
Figure 379. DPSW_IF_SET_LINK_CFG Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x04C — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 32 31 0
0x10 — RATE
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
0x10 0-32 RATE Rate
0x18 0-63 OPTIONS Mask of available options; use ‘DPSW_LINK_OPT_<x> values
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-55
13.3.42 DPSW_IF_GET_LINK_STATE
Command structure
Figure 380. DPSW_IF_GET_LINK_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x046 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-56
Response structure
Figure 381. DPSW_IF_GET_LINK_STATE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x046 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — UP —
63 32 31 0
0x10 — RATE
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32 UP 0 - down, 1- up
0x10 0-32 RATE Rate
0x18 0-63 OPTIONS Mask of available options; use ‘DPSW_LINK_OPT_<x>’ values
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-57
13.3.43 DPSW_IF_GET_MAX_FRAME_LENGTH
Command structure
Figure 382. DPSW_IF_GET_MAX_FRAME_LENGTH Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x045 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — IF_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IF_ID Interface ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-58
Response structure
Figure 383. DPSW_IF_GET_MAX_FRAME_LENGTH Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x045 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — FRAME_LENGTH —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 FRAME_LENGTH Maximum Frame Length
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-59
13.3.44 DPSW_VLAN_ADD
Command structure
Figure 384. DPSW_VLAN_ADD Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x060 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Data base
16-31 VLAN_ID VLAN ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-60
13.3.45 DPSW_VLAN_ADD_IF
Command structure
Figure 385. DPSW_VLAN_ADD_IF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x061 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 IF_ID (Bitmap)
63 0
0x18 IF_ID (Bitmap)
63 0
0x20 IF_ID (Bitmap)
63 0
0x28 IF_ID (Bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-61
13.3.46 DPSW_VLAN_ADD_IF_UNTAGGED
Command structure
Figure 386. DPSW_VLAN_ADD_IF_UNTAGGED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x062 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 IF_ID (Bitmap)
63 0
0x18 IF_ID (Bitmap)
63 0
0x20 IF_ID (Bitmap)
63 0
0x28 IF_ID (Bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-62
13.3.47 DPSW_VLAN_ADD_IF_FLOODING
Command structure
Figure 387. DPSW_VLAN_ADD_IF_FLOODING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x063 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-63
13.3.48 DPSW_VLAN_REMOVE_IF
Command structure
Figure 388. DPSW_VLAN_REMOVE_IF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x064 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-64
13.3.49 DPSW_VLAN_REMOVE_IF_UNTAGGED
Command structure
Figure 389. DPSW_VLAN_REMOVE_IF_UNTAGGED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x065 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-65
13.3.50 DPSW_VLAN_REMOVE_IF_FLOODING
Command structure
Figure 390. DPSW_VLAN_REMOVE_IF_FLOODING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x066 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-66
13.3.51 DPSW_VLAN_REMOVE
Command structure
Figure 391. DPSW_VLAN_REMOVE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x067 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-67
13.3.52 DPSW_VLAN_GET_ATTRIBUTES
Command structure
Figure 392. DPSW_VLAN_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x06B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-68
Response structure
Figure 393. DPSW_VLAN_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset
from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x06B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 48 47 32 31 16 15 0
0x10 NUM_FLOODING_IFS NUM_UNTAGGED_IFS NUM_IFS FDB_ID
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08
0x10 0-15 FDB_ID Associated FDB ID
16-31 NUM_IFS Number of interfaces
32-47 NUM_UNTAGGED_IFS Number of untagged interfaces
48-63 NUM_FLOODING_IFS Number of flooding interfaces
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-69
13.3.53 DPSW_VLAN_GET_IF
Command structure
Figure 394. DPSW_VLAN_GET_IF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x068 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 19 16 15 0
0x08 — VLAN_ID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-70
Response structure
Figure 395. DPSW_VLAN_GET_IF Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x068 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — NUM_IFS
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 NUM_IFS The number of interfaces that areassigned to the egress list for this VLAN
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-71
13.3.54 DPSW_VLAN_GET_IF_FLOODING
Command structure
Figure 396. DPSW_VLAN_GET_IF_FLOODING Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x069 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-72
Response structure
Figure 397. DPSW_VLAN_GET_IF_FLOODING Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x069 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — NUM_IFS
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 NUM_IFS The number of interfaces that areassigned to the egress list for this VLAN
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-73
13.3.55 DPSW_VLAN_GET_IF_UNTAGGED
Command structure
Figure 398. DPSW_VLAN_GET_IF_UNTAGGED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x06A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — VLAN_ID —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 VLAN_ID VLAN ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-74
Response structure
Figure 399. DPSW_VLAN_GET_IF_UNTAGGED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x06A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — NUM_IFS
63 0
0x10 IF_ID (bitmap)
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 NUM_IFS The number of interfaces that areassigned to the egress list for this VLAN
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-75
13.3.56 DPSW_FDB_ADD
Command structure
Figure 400. DPSW_FDB_ADD Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x082 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 0
0x08 NUM_FDB_ENTRIES FDB_AGING_TIME —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-47 FDB_AGING_TIME Aging time in seconds
48-63 NUM_FDB_ENTRIES Number of FDB entries
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-76
Response structure
Figure 401. DPSW_FDB_ADD Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x082 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-77
13.3.57 DPSW_FDB_REMOVE
Command structure
Figure 402. DPSW_FDB_REMOVE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x083 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-78
13.3.58 DPSW_FDB_ADD_UNICAST
Command structure
Figure 403. DPSW_FDB_ADD_UNICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x084 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 FDB_ID
63 20 19 16 15 0
0x10 — TYPE IF_EGRESS
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-63 MAC_ADDR[0-5] MAC address
0x10 0-15 IF_EGRESS Egress interface ID
16-19 TYPE Select static or dynamic entry. Select one of the supported values below:0x0 = DPSW_FDB_ENTRY_STATIC - Static entry 0x1 = DPSW_FDB_ENTRY_DINAMIC - Dynamic entry
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-79
13.3.59 DPSW_FDB_GET_UNICAST
Command structure
Figure 404. DPSW_FDB_GET_UNICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x081 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 21 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-63 MAC_ADDR[0-5] MAC address
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-80
Response structure
Figure 405. DPSW_FDB_GET_UNICAST Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x081 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 20 19 16 15 0
0x10 — TYPE IF_EGRESS
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-15 IF_EGRESS Egress interface ID
16-19 TYPE Select static or dynamic entry:0x0 = DPSW_FDB_ENTRY_STATIC - Static entry 0x1 = DPSW_FDB_ENTRY_DINAMIC - Dynamic entry
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-81
13.3.60 DPSW_FDB_REMOVE_UNICAST
Command structure
Figure 406. DPSW_FDB_REMOVE_UNICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x085 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 FDB_ID
63 20 19 16 15 0
0x10 — TYPE IF_EGRESS
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-63 MAC_ADDR[0-5] MAC address
0x10 0-15 IF_EGRESS Egress interface ID
16-19 TYPE Select static or dynamic entry:0x0 = DPSW_FDB_ENTRY_STATIC - Static entry 0x1 = DPSW_FDB_ENTRY_DINAMIC - Dynamic entry
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-82
13.3.61 DPSW_FDB_ADD_MULTICAST
Command structure
Figure 407. DPSW_FDB_ADD_MULTICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x086 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 36 35 32 31 16 15 0
0x08 — TYPE NUM_IFS FDB_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x10 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 —
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 IF_ID (bitmap)
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-31 NUM_IFS Number of external and internal interfaces
32-35 TYPE Select static or dynamic entry:0x0 = DPSW_FDB_ENTRY_STATIC - Static entry 0x1 = DPSW_FDB_ENTRY_DINAMIC - Dynamic entry
0x10 16-63 MAC_ADDR[0-5] MAC address
0x18- 0x37
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-83
13.3.62 DPSW_FDB_GET_MULTICAST
Command structure
Figure 408. DPSW_FDB_GET_MULTICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x080 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x08 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-63 MAC_ADDR[0-5] MAC address
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-84
Response structure
Figure 409. DPSW_FDB_GET_MULTICAST Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x080 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 20 19 16 15 0
0x10 — TYPE NUM_IFS
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 IF_ID (bitmap)
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 Reserved
0x10 0-15 NUM_IFS Number of external and internal interfaces
16-19 TYPE Select static or dynamic entry:0x0 = DPSW_FDB_ENTRY_STATIC - Static entry 0x1 = DPSW_FDB_ENTRY_DINAMIC - Dynamic entry
0x18- 0x37
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-85
13.3.63 DPSW_FDB_REMOVE_MULTICAST
Command structure
Figure 410. DPSW_FDB_REMOVE_MULTICAST Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x087 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 36 35 32 31 16 15 0
0x08 — TYPE NUM_IFS FDB_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 0
0x10 MAC_ADDR0 MAC_ADDR1 MAC_ADDR2 MAC_ADDR3 MAC_ADDR4 MAC_ADDR5 —
63 0
0x18 IF_ID (bitmap)
63 0
0x20 IF_ID (bitmap)
63 0
0x28 IF_ID (bitmap)
63 0
0x30 IF_ID (bitmap)
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-31 NUM_IFS Number of external and internal interfaces
32-35 TYPE Select static or dynamic entry:0x0 = DPSW_FDB_ENTRY_STATIC - Static entry 0x1 = DPSW_FDB_ENTRY_DINAMIC - Dynamic entry
0x10 16-63 MAC_ADDR[0-5] MAC address
0x18- 0x37
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-86
13.3.64 DPSW_FDB_SET_LEARNING_MODE
Command structure
Figure 411. DPSW_FDB_SET_LEARNING_MODE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x088 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 20 19 16 15 0
0x08 — MODE FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
16-19 MODE learning mode. Select one of the supported values below:0x0 = DPSW_FDB_LEARNING_MODE_DIS - Disable Auto-learning 0x1 = DPSW_FDB_LEARNING_MODE_HW - Enable HW auto-Learning 0x2 = DPSW_FDB_LEARNING_MODE_NON_SECURE - Enable None secure learning by CPU 0x3 = DPSW_FDB_LEARNING_MODE_SECURE - Enable secure learning by CPU
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-87
13.3.65 DPSW_FDB_GET_ATTRIBUTES
Command structure
Figure 412. DPSW_FDB_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x089 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — FDB_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 FDB_ID Forwarding Database Identifier
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-88
Response structure
Figure 413. DPSW_FDB_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x089 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 32 31 16 15 0
0x08 NUM_FDB_MC_GROUPS FDB_AGING_TIME MAX_FDB_ENTRIES —
63 20 19 16 15 0
0x10 — LEARNING_MO
DE
MAX_FDB_MC_GROUPS
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 MAX_FDB_ENTRIES Number of FDB entries
32-47 FDB_AGING_TIME Aging time in seconds
48-63 NUM_FDB_MC_GROUPS Current number of multicast groups
0x10 0-15 MAX_FDB_MC_GROUPS Maximum number of multicast groups
16-19 LEARNING_MODE learning mode. Select one of the supported values below:0x0 = DPSW_FDB_LEARNING_MODE_DIS - Disable Auto-learning 0x1 = DPSW_FDB_LEARNING_MODE_HW - Enable HW auto-Learning 0x2 = DPSW_FDB_LEARNING_MODE_NON_SECURE - Enable None secure learning by CPU 0x3 = DPSW_FDB_LEARNING_MODE_SECURE - Enable secure learning by CPU
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-89
13.3.66 DPSW_ACL_ADD
Command structure
Figure 414. DPSW_ACL_ADD Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x090 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — MAX_ENTRIES —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-32 MAX_ENTIRIES Number of FDB entries
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-90
Response structure
Figure 415. DPSW_ACL_ADD Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x090 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — ACL_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID Returned ACL ID, for the future reference
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-91
13.3.67 DPSW_ACL_REMOVE
Command structure
Figure 416. DPSW_ACL_REMOVE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x091 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — ACL_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID ACL ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-92
13.3.68 DPSW_ACL_PREPARE_ENTRY_CFG
Extension structure
Figure 417. DPSW_ACL_PREPARE_ENTRY_CFG Extension Description
Offset from Management Command Portal base Read-Write Access
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x00 L2_TPID L2_DEST_MAC0 L2_DEST_MAC1 L2_DEST_MAC2 L2_DEST_MAC3 L2_DEST_MAC4 L2_DEST_MAC5
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x08 L2_VLAN_ID L2_SOURCE_MAC0
L2_SOURCE_MAC1
L2_SOURCE_MAC2
L2_SOURCE_MAC3
L2_SOURCE_MAC4
L2_SOURCE_MAC5
63 32 31 0
0x10 L3_SOURCE_IP L3_DEST_IP
63 56 55 48 47 32 31 16 15 0
0x18 L3_DSCP L2_PCP_DEI L2_ETHR_TYPE L4_SOURCE_PORT L4_DEST_PORT
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TPID L2_DEST_MAC0 L2_DEST_MAC1 L2_DEST_MAC2 L2_DEST_MAC3 L2_DEST_MAC4 L2_DEST_MAC5
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 L2_VLAN_ID L2_SOURCE_MAC0
L2_SOURCE_MAC1
L2_SOURCE_MAC2
L2_SOURCE_MAC3
L2_SOURCE_MAC4
L2_SOURCE_MAC5
63 32 31 0
0x30 L3_SOURCE_IP L3_DEST_IP
63 56 55 48 47 32 31 16 15 0
0x38 L3_DSCP L2_PCP_DEI L2_ETHR_TYPE L4_SOURCE_PORT L4_DEST_PORT
63 16 15 8 7 0
0x40 — L3_PROTOCOL L3_ROTOCOL
Offset Bits Name Description
0x00 0-47 L2_DEST_MAC[0-5] Destination MAC address: BPDU, Multicast, Broadcast, Unicast, slow protocols, MVRP, STP
Key match Fields
48-63 L2_TPID Layer 2 (Ethernet) protocol type, used to identify the following protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae, Q-in-Q, IPv4, IPv6, PPPoE
0x08 0-47 L2_SOURCE_MAC[0-5] Source MAC address
48-63 L2_VLAN_ID layer 2 VLAN ID
0x10 0-31 L3_DEST_IP Destination IPv4 IP
32-63 L3_SOURCE_IP Source IPv4 IP
0x18 0-15 L4_DEST_PORT Destination TCP/UDP port
16-31 L4_SOURCE_PORT Source TCP/UDP port
32-47 L2_ETHR_TYPE Layer 2 Ethernet Type
48-55 L2_PCP_DEI Indicate which protocol is encapsulated in the payload
56-63 L3_DSCP Layer 3 differentiated services code point
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-93
All unspecified fields are reserved and must be cleared (set to zero)
0x20 0-47 L2_DEST_MAC[0-5] Destination MAC address: BPDU, Multicast, Broadcast, Unicast, slow protocols, MVRP, STP
key mask : b’1 - valid, b’0 don’t care
48-63 L2_TPID Layer 2 (Ethernet) protocol type, used to identify the following protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae, Q-in-Q, IPv4, IPv6, PPPoE
0x28 0-47 L2_SOURCE_MAC[0-5] Source MAC address
48-63 L2_VLAN_ID layer 2 VLAN ID
0x30 0-31 L3_DEST_IP Destination IPv4 IP
32-63 L3_SOURCE_IP Source IPv4 IP
0x38 0-15 L4_DEST_PORT Destination TCP/UDP port
16-31 L4_SOURCE_PORT Source TCP/UDP port
32-47 L2_ETHR_TYPE Layer 2 Ethernet Type
48-55 L2_PCP_DEI Indicate which protocol is encapsulated in the payload
56-63 L3_DSCP Layer 3 differentiated services code point
0x40 0-7 L3_PROTOCOL Tells the Network layer at the destination host, to which Protocol this packet belongs to. The following protocol are supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6(encapsulation), GRE, PTP
Match Fields
8-15 L3_PROTOCOL Tells the Network layer at the destination host, to which Protocol this packet belongs to. The following protocol are supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6(encapsulation), GRE, PTP
Mask : b’1 - valid, b’0 don’t care
Offset Bits Name Description
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-94
13.3.69 DPSW_ACL_ADD_ENTRY
Command structure
Figure 418. DPSW_ACL_ADD_ENTRY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x092 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 PRECEDENCE RESULT_IF_ID ACL_ID
63 4 3 0
0x10 —
RE
SU
LT_A
CT
ION
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 KEY_IOVA
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID ACL ID
16-31 RESULT_IF_ID Interface IDs to redirect frame. Valid only if redirect selected for action
32-63 PRECEDENCE Precedence inside ACL 0 is lowest; This priority can not changeduring the lifetime of a Policy. It is user responsibility tospace the priorities according to consequent rule additions.
0x10 0-3 RESULT_ACTION Action should be taken when ACL entry hit
0x38 0-63 KEY_IOVA I/O virtual address of DMA-able memory filled with key after call to dpsw_acl_prepare_entry_cfg()
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-95
13.3.70 DPSW_ACL_REMOVE_ENTRY
Command structure
Figure 419. DPSW_ACL_REMOVE_ENTRY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x093 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 PRECEDENCE RESULT_IF_ID ACL_ID
63 4 3 0
0x10 —
RE
SU
LT_A
CT
ION
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 KEY_IOVA
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID ACL ID
16-31 RESULT_IF_ID Interface IDs to redirect frame. Valid only if redirect selected for action
32-63 PRECEDENCE Precedence inside ACL 0 is lowest; This priority can not changeduring the lifetime of a Policy. It is user responsibility tospace the priorities according to consequent rule additions.
0x10 0-3 RESULT_ACTION Action should be taken when ACL entry hit
0x38 0-63 KEY_IOVA I/O virtual address of DMA-able memory filled with key after call to dpsw_acl_prepare_entry_cfg()
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-96
Extension structure
Figure 420. DPSW_ACL_REMOVE_ENTRY Extension Description
Offset from Management Command Portal base Read-Write Access
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x00 L2_TPID L2_DEST_MAC0 L2_DEST_MAC1 L2_DEST_MAC2 L2_DEST_MAC3 L2_DEST_MAC4 L2_DEST_MAC5
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x08 L2_VLAN_ID L2_SOURCE_MAC0
L2_SOURCE_MAC1
L2_SOURCE_MAC2
L2_SOURCE_MAC3
L2_SOURCE_MAC4
L2_SOURCE_MAC5
63 32 31 0
0x10 L3_SOURCE_IP L3_DEST_IP
63 56 55 48 47 32 31 16 15 0
0x18 L3_DSCP L2_PCP_DEI L2_ETHR_TYPE L4_SOURCE_PORT L4_DEST_PORT
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x20 TPID L2_DEST_MAC0 L2_DEST_MAC1 L2_DEST_MAC2 L2_DEST_MAC3 L2_DEST_MAC4 L2_DEST_MAC5
63 48 47 40 39 32 31 24 23 16 15 8 7 0
0x28 L2_VLAN_ID L2_SOURCE_MAC0
L2_SOURCE_MAC1
L2_SOURCE_MAC2
L2_SOURCE_MAC3
L2_SOURCE_MAC4
L2_SOURCE_MAC5
63 32 31 0
0x30 L3_SOURCE_IP L3_DEST_IP
63 56 55 48 47 32 31 16 15 0
0x38 L3_DSCP L2_PCP_DEI L2_ETHR_TYPE L4_SOURCE_PORT L4_DEST_PORT
63 32 31 16 15 8 7 0
0x40 PRECEDENCE IF_ID L3_PROTOCOL L3_ROTOCOL
63 4 3 0
0x48 — ACTION
Offset Bits Name Description
0x00 0-47 L2_DEST_MAC[0-5] Destination MAC address: BPDU, Multicast, Broadcast, Unicast, slow protocols, MVRP, STP
Key match Fields
48-63 L2_TPID Layer 2 (Ethernet) protocol type, used to identify the following protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae, Q-in-Q, IPv4, IPv6, PPPoE
0x08 0-47 L2_SOURCE_MAC[0-5] Source MAC address
48-63 L2_VLAN_ID layer 2 VLAN ID
0x10 0-31 L3_DEST_IP Destination IPv4 IP
32-63 L3_SOURCE_IP Source IPv4 IP
0x18 0-15 L4_DEST_PORT Destination TCP/UDP port
16-31 L4_SOURCE_PORT Source TCP/UDP port
32-47 L2_ETHR_TYPE Layer 2 Ethernet Type
48-55 L2_PCP_DEI Indicate which protocol is encapsulated in the payload
56-63 L3_DSCP Layer 3 differentiated services code point
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-97
All unspecified fields are reserved and must be cleared (set to zero)
0x20 0-47 L2_DEST_MAC[0-5] Destination MAC address: BPDU, Multicast, Broadcast, Unicast, slow protocols, MVRP, STP
key mask : b’1 - valid, b’0 don’t care
48-63 L2_TPID Layer 2 (Ethernet) protocol type, used to identify the following protocols: MPLS, PTP, PFC, ARP, Jumbo frames, LLDP, IEEE802.1ae, Q-in-Q, IPv4, IPv6, PPPoE
0x28 0-47 L2_SOURCE_MAC[0-5] Source MAC address
48-63 L2_VLAN_ID layer 2 VLAN ID
0x30 0-31 L3_DEST_IP Destination IPv4 IP
32-63 L3_SOURCE_IP Source IPv4 IP
0x38 0-15 L4_DEST_PORT Destination TCP/UDP port
16-31 L4_SOURCE_PORT Source TCP/UDP port
32-47 L2_ETHR_TYPE Layer 2 Ethernet Type
48-55 L2_PCP_DEI Indicate which protocol is encapsulated in the payload
56-63 L3_DSCP Layer 3 differentiated services code point
0x40 0-7 L3_PROTOCOL Tells the Network layer at the destination host, to which Protocol this packet belongs to. The following protocol are supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6(encapsulation), GRE, PTP
Match Fields
8-15 L3_PROTOCOL Tells the Network layer at the destination host, to which Protocol this packet belongs to. The following protocol are supported: ICMP, IGMP, IPv4 (encapsulation), TCP, IPv6(encapsulation), GRE, PTP
Mask : b’1 - valid, b’0 don’t care
16-31 IF_ID Interface IDs to redirect frame. Valid only if redirect selected for action
result - Required action when entry hit occurs
32-63 PRECEDENCE Precedence inside ACL 0 is lowest; This priority can not change during the lifetime of a Policy. It is user responsibility to space the priorities according to consequent rule additions.
0x48 0-4 ACTION Action should be taken whenACL entry hit result - Required action when entry hit occurs
Offset Bits Name Description
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-98
13.3.71 DPSW_ACL_ADD_IF
Command structure
Figure 421. DPSW_ACL_ADD_IF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x094 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — NUM_IFS ACL_ID
63 0
0x10 IF_ID (Bitmap)
63 0
0x18 IF_ID (Bitmap)
63 0
0x20 IF_ID (Bitmap)
63 0
0x28 IF_ID (Bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID ACL ID
16-31 NUM_IFS Number of interfaces
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-99
13.3.72 DPSW_ACL_REMOVE_IF
Command structure
Figure 422. DPSW_ACL_REMOVE_IF Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x095 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — NUM_IFS ACL_ID
63 0
0x10 IF_ID (Bitmap)
63 0
0x18 IF_ID (Bitmap)
63 0
0x20 IF_ID (Bitmap)
63 0
0x28 IF_ID (Bitmap)
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID ACL ID
16-31 NUM_IFS Number of interfaces
0x10- 0x2F
0-63 IF_ID (bitmap) The set of interfaces that are assigned to the egress list for this VLAN
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-100
13.3.73 DPSW_ACL_GET_ATTRIBUTES
Command structure
Figure 423. DPSW_ACL_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x096 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 0
0x08 — ACL_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 ACL_ID ACL ID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-101
Response structure
Figure 424. DPSW_ACL_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x096 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 32 31 16 15 0
0x10 NUM_IFS NUM_ENTRIES MAX_ENTRIES
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-15 MAX_ENTRIES Max number of ACL entries
16-31 NUM_ENTRIES Number of used ACL entries
32-63 NUM_IFS Number of interfaces associated with ACL
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-102
13.3.74 DPSW_CTRL_IF_GET_ATTRIBUTES
Command structure
Figure 425. DPSW_CTRL_IF_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-103
Response structure
Figure 426. DPSW_CTRL_IF_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 32 31 0
0x10 RX_ERR_FQID RX_FQID
63 32 31 0
0x18 — TX_ERR_CONF_FQID
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-31 RX_FQID Receive FQID
32-63 RX_ERR_FQID Receive error FQID
0x18 0-31 TX_ERR_CONF_FQID Transmit error and confirmation FQID
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-104
13.3.75 DPSW_CTRL_IF_SET_POOLS
Command structure
Figure 427. DPSW_CTRL_IF_SET_POOLS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 14 13 12 11 10 9 8 7 0
0x08 POOL0_DPBP_ID —
PO
OL7_B
AC
KU
P_P
OO
L
PO
OL6_B
AC
KU
P_P
OO
L
PO
OL5_B
AC
KU
P_P
OO
L
PO
OL4_B
AC
KU
P_P
OO
L
PO
OL3_B
AC
KU
P_P
OO
L
PO
OL2_B
AC
KU
P_P
OO
L
PO
OL1_B
AC
KU
P_P
OO
L
PO
OL0_B
AC
KU
P_P
OO
L
NUM_DPBP
63 32 31 0
0x10 POOL2_DPBP_ID POOL1_DPBP_ID
63 32 31 0
0x18 POOL4_DPBP_ID POOL3_DPBP_ID
63 32 31 0
0x20 POOL6_DPBP_ID POOL5_DPBP_ID
63 48 47 32 31 0
0x28 POOL1_BUFFER_SIZE POOL0_BUFFER_SIZE POOL7_DPBP_ID
63 48 47 32 31 16 15 0
0x30 POOL5_BUFFER_SIZE POOL4_BUFFER_SIZE POOL3_BUFFER_SIZE POOL2_BUFFER_SIZE
63 32 31 16 15 0
0x38 — POOL7_BUFFER_SIZE POOL6_BUFFER_SIZE
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 NUM_DPBP Number of DPBPs
8-15 POOLS[0-7]_BACKUP_POOL Backup pool
0x08 - 0x28
0-31 / 32-63
POOLS[0-7]_DPBP_ID DPBP object ID
0x28 - 0x30
0-15 / 16-31/ 32-47/ 48-63
POLS[0-7]_BUFFER_SIZE Buffer size
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-105
13.3.76 DPSW_CTRL_IF_ENABLE
Command structure
Figure 428. DPSW_CTRL_IF_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A2 — TOKEN — — STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSW: Data Path L2 Switch
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 13-106
13.3.77 DPSW_CTRL_IF_DISABLE
Command structure
Figure 429. DPSW_CTRL_IF_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0A3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-1
Chapter 14 DPMAC: Data Path MACFor every DPAA2 MAC, there is an MC object named DPMAC, for MDIO and link state updates.
The DPMAC virtualizes the MDIO interface, so each PHY driver may see a private interface (removing the need for synchronization in GPP on the multiplexed MDIO hardware).
DPMAC objects are expected to be accessed only by kernel/host when the PHYs are configured or when a PHY interrupt occurs. PHY driver and PHY interrupt handling are kept in the responsibility of the GPP (preferably BSP software in the kernel only).
MC does not handle PHY interrupts, therefore the PHY driver in GPP must notify state changes and adjust the link setup through the DPMAC API.
14.1 DPMAC features
The following list summarizes the DPMAC main features and capabilities:
• Initialization of MAC controllers according to selected Reset Configuration Word and SerDes protocols.
• Link configuration requests are taken from network objects connected to the DPMAC (for example, DPNI, DPSW, or DPDMUX).
• Link state setting (by PHY driver) – the DPMAC propagates link state from the PHY the connected network object.
• IRQ support for link configuration request (to PHY driver) and for link state change.
• MDIO read/write commands
• Query MAC counters
• Supports various types of Ethernet links:
— Regular PHY links – Link is negotiated or set manually through PHY configuration.
— Fixed links – MC assumes that the link is always on (PHY configuration is assumed to be fixed).
— Backplane links – 1Gbase-KX and 10Gbase-KR; MC handles the SerDes calibration required for these modes.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-2
14.2 DPMAC command referenceThis section contains detailed programming model of DPMAC commands.
14.2.1 DPMAC_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPMAC_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
Figure 430. DPMAC_OPEN Command Description
The following table describes the command fields.1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x80C — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPMAC_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 23. DPMAC_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPMAC_ID DPMAC unique ID
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-3
14.2.2 DPMAC_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 431. DPMAC_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-4
14.2.3 DPMAC_CREATE
This command creates and initializes an instance of DPMAC according to the specified command parameters. This command is not required for DPMAC instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 432. DPMAC_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x90C — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — MAC_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 24. DPMAC_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MAC_ID Represents the Hardware MAC ID; in case of multiple WRIOP,the MAC IDs are continuous.For example: * 2 WRIOPs, 16 MACs in each:* MAC IDs for the 1st WRIOP: 1-16,* MAC IDs for the 2nd WRIOP: 17-32.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-5
14.2.4 DPMAC_DESTROY
Command structure
Figure 433. DPMAC_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-6
14.2.5 DPMAC_SET_IRQ
Set IRQ information for the DPMAC to trigger an interrupt.
Command structure
Figure 434. DPMAC_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-7
14.2.6 DPMAC_GET_IRQ
Get IRQ information from the DPMAC.
Command structure
Figure 435. DPMAC_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-8
Response structure
Figure 436. DPMAC_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_PADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-9
14.2.7 DPMAC_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 437. DPMAC_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-10
14.2.8 DPMAC_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 438. DPMAC_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-11
Response structure
Figure 439. DPMAC_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-12
14.2.9 DPMAC_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 440. DPMAC_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-13
14.2.10 DPMAC_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 441. DPMAC_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-14
Response structure
Figure 442. DPMAC_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-15
14.2.11 DPMAC_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 443. DPMAC_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPMAC_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-16
Response structure
Figure 444. DPMAC_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events in IRQ 0:Bit 0: DPMAC_IRQ_EVENT_LINK_CFG_REQ – indicates a change in requested link configuration; PHY driver (if exists) is expected to renogotiate the configuration.Bit 1: DPMAC_IRQ_EVENT_LINK_CHANGED – indicates a change in the link state
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-17
14.2.12 DPMAC_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 445. DPMAC_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-18
14.2.13 DPMAC_GET_ATTRIBUTES
Command structure
Figure 446. DPMAC_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-19
Response structure
Figure 447. DPMAC_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ID PHY_ID
63 48 47 40 39 32 31 16 15 0
0x10 — ETH_IF LINK_TYPE MINOR MAJOR
63 0
0x18 — MAX_RATE
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 PHY_ID PHY ID
32-63 ID DPMAC object ID
0x10 0-15 MAJOR DPMAC major version
16-31 MINOR DPMAC minor version
32-39 LINK_TYPE Link type
40-47 ETH_IF Ethernet interface
0x18 0-31 MAX_RATE Maximum supported rate - in Mbps
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-20
14.2.14 DPMAC_MDIO_READ
Command structure
Figure 448. DPMAC_MDIO_READ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 16 15 8 7 0
0x08 — REG PHY_ADDR
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 PHY_ADDR MDIO device address
8-15 REG Address of the register within the Clause 45 PHY device from which data is to be read
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-21
Response structure
Figure 449. DPMAC_MDIO_READ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 0
0x08 — DATA —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 16-31 DATA Data read/write from/to MDIO
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-22
14.2.15 DPMAC_MDIO_WRITE
Command structure
Figure 450. DPMAC_MDIO_WRITE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 16 15 8 7 0
0x08 — DATA REG PHY_ADDR
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x08 0-7 PHY_ADDR MDIO device address
8-15 REG Address of the register within the Clause 45 PHY device from which data is to be read
16-31 DATA Data read/write from/to MDIO
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-23
14.2.16 DPMAC_GET_LINK_CFG
Command structure
Figure 451. DPMAC_GET_LINK_CFG Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-24
Response structure
Figure 452. DPMAC_GET_LINK_CFG Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 OPTIONS
63 32 31 0
0x10 — RATE
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 OPTIONS Enable/Disable DPMAC link cfg features (bitmap)
0x10 0-31 RATE Link’s rate
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-25
14.2.17 DPMAC_SET_LINK_STATE
Command structure
Figure 453. DPMAC_SET_LINK_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 OPTIONS
63 32 31 0
0x10 — RATE
63 1 0
0x18 UP
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 OPTIONS Enable/Disable DPMAC link cfg features (bitmap)
0x10 0-31 RATE Link’s rate
0x18 0 UP Link state
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-26
14.2.18 DPMAC_GET_COUNTER
Command structure
Figure 454. DPMAC_GET_COUNTER Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 8 7 0
0x08 — TYPE
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 TYPE The requested counter
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-27
Response structure
Figure 455. DPMAC_GET_COUNTER Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x0C4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 COUNTER
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-63 COUNTER The requested counter
DPMAC: Data Path MAC
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 14-28
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-1
Chapter 15 DPRTC: Data Path Real Time ClockThe MC exports the DPRTC object to allow GPP software to control the physical IEEE-1588 Real Time Clock. A single DPRTC object is needed to control the IEEE-1588 RTC, and this object is expected to serve the PTP stack running in GPP.
15.1 DPRTC featuresThe following list summarizes the DPRTC main features and capabilities:
• IEEE-1588 RTC accuracy in nanoseconds.
• Supports RTC frequency compensation.
• Supports modification of RTC clock offset.
• Supports direct setting of the RTC time – useful mainly for zeroing the timer, as the recommended method for RTC modifications is through offset and/or frequency change.
• Supports setting an alarm time – generates an event to GPP at a requested time.
• Supports pulse-per-second event.
15.2 DPRTC command referenceThis section contains the detailed programming model of DPRTC commands.
15.2.1 DPRTC_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPRTC_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-2
Command structure
The command format is shown in the figure below.
Figure 456. DPRTC_OPEN Command Description
The following table describes the command fields.
1-
15.2.2 DPRTC_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x804 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPRTC_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 25. DPRTC_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPRTC_ID DPRTC unique ID
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-3
Command structure
Figure 457. DPRTC_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
15.2.3 DPRTC_CREATE
This command creates and initializes an instance of DPRTC according to the specified command parameters. This command is not required for DPRTC instances that are created using the DPL.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-4
Command structure
Figure 458. DPRTC_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x904 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 26. DPRTC_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-5
15.2.4 DPRTC_DESTROY
Command structure
Figure 459. DPRTC_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-6
15.2.5 DPRTC_SET_IRQ
Set IRQ information for the DPRTC to trigger an interrupt.
Command structure
Figure 460. DPRTC_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-7
15.2.6 DPRTC_GET_IRQ
Get IRQ information from the DPRTC.
Command structure
Figure 461. DPRTC_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-8
Response structure
Figure 462. DPRTC_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-9
15.2.7 DPRTC_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 463. DPRTC_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-10
15.2.8 DPRTC_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 464. DPRTC_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-11
Response structure
Figure 465. DPRTC_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-12
15.2.9 DPRTC_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 466. DPRTC_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-13
15.2.10 DPRTC_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 467. DPRTC_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-14
Response structure
Figure 468. DPRTC_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-15
15.2.11 DPRTC_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 469. DPRTC_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPRTC_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-16
Response structure
Figure 470. DPRTC_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 27: DPRTC_EVENT_PPS – indicates a pulse per second eventBit 30: DPRTC_EVENT_ALARM – indicates that the requested alarm time was reached
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-17
15.2.12 DPRTC_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 471. DPRTC_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-18
15.2.13 DPRTC_GET_ATTRIBUTES
Command structure
Figure 472. DPRTC_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-19
Response structure
Figure 473. DPRTC_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ID —
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 ID DPRTC object ID
0x10 0-15 VERSION_MAJOR DPRTC major version
16-31 VERSION_MINOR DPRTC minor version
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-20
15.2.14 DPRTC_SET_CLOCK_OFFSET
Command structure
Figure 474. DPRTC_SET_CLOCK_OFFSET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 OFFSET
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 OFFSET New clock offset (in nanoseconds)
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-21
15.2.15 DPRTC_SET_FREQ_COMPENSATION
Command structure
Figure 475. DPRTC_SET_FREQ_COMPENSATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — FREQ_COMPENSATION
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 FREQ_COMPENSATION The new frequency compensation value to set.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-22
15.2.16 DPRTC_GET_FREQ_COMPENSATION
Command structure
Figure 476. DPRTC_GET_FREQ_COMPENSATION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-23
Response structure
Figure 477. DPRTC_GET_FREQ_COMPENSATION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — FREQ_COMPENSATION
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 FREQ_COMPENSATION Frequency compensation value
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-24
15.2.17 DPRTC_GET_TIME
Command structure
Figure 478. DPRTC_GET_TIME Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-25
Response structure
Figure 479. DPRTC_GET_TIME Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 TIME
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 TIME Current RTC time in nanoseconds
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-26
15.2.18 DPRTC_SET_TIME
Command structure
Figure 480. DPRTC_SET_TIME Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D4 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 TIME
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 TIME New RTC time in nanoseconds
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-27
15.2.19 DPRTC_SET_ALARM
Command structure
Figure 481. DPRTC_SET_ALARM Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1D5 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 TIME
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 TIME In nanoseconds, the time when the alarmshould go off - must be a multiple of the RTC period
DPRTC: Data Path Real Time Clock
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 15-28
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-1
Chapter 16 DPSECI: Data Path SEC InterfaceThe MC exports the DPSECI object as an interface to operate the DPAA2 Security Engine (SEC).
The DPSECI enables sending frame-based requests to SEC and receiving back the processed response, utilizing the DPAA2 QBMan infrastructure. DPSECI object provides up to eight priorities for processing SEC requests.
16.1 DPSECI featuresThe following list summarizes the DPSECI main features and capabilities:
• Supports up to eight scheduling priorities for processing service requests.
— Each DPSECI transmit queue is mapped to one of eight service priorities, allowing further prioritization in hardware between requests from different DPSECI objects.
• Supports up to eight receive queues for incoming response frames.
— Each DPSECI response (receive) queue is mapped to one of eight receive priorities, allowing further prioritization between other interfaces when associating the DPSECI receive queues to DPIO or DPCON objects.
• Supports different scheduling options for processing received packets:
— Queues can be configured either in ‘parked’ mode (default), or attached to a DPIO object, or attached to DPCON object
• Allows interaction with one or more DPIO objects for dequeueing/enqueueing frame descriptors (FD) and for acquiring/releasing buffers.
• Supports enable, disable, and reset operations
16.2 DPSECI functional description
16.2.1 Setting DPSECI for SEC operation
The DPSECI is an interface object that allows GPP software to send service requests to the SEC engine and receive back the processed response. The actual description of requested SEC service is built by GPP software in the form of a frame descriptor. GPP software is also responsible for reading and parsing the response frame descriptor containing the ouptut and status of the processed request.
The DPSECI is not aware of the content of SEC requests being sent, and does not perform any checks on their correctness. It is involved only in setting up the QMan infrastructure for communicating with the SEC engine.
The driver software must declare the number of priorities (either 1 or 2) for SEC processing. The DPSECI priorities are mapped to one of 8 global priorities of the SEC hardware block; this allows further prioritization of service requests between different DPSECI objects.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-2
16.2.2 Relationship with DPIO and DPCON objects
Each of the two DPSECI response (receive) queues may be associated with either a DPIO object or a DPCON object. This serves for notification purposes and/or advanced scheduling of received response frames.
DPIO objects provide configuration of a QBMan software portal, with an option for data availability notifications. GPP software is free to relate DPIO objects to threads, or to share them between cores in SMP mode but this requires synchronized access to the QBMan software portal. It is possible to associate multiple DPIO objects with the same DPSECI, in order to spread responses from this DPSECI across multiple QBMan software portals.
GPP software may decide to enable DPIO notifications, or it may dequeue frames based on its own scheduled polling logic. It is also possible for one GPP entity to receive the notification from one DPIO and alert another entity that will dequeue the packets using a different DPIO.
DPCON objects are used for concentrating traffic from several interfaces into sub-interfaces, mainly for scheduling purposes. It is possible to connect DPCON with DPIO so it generates notifications to the GPP.
Note that the QBMan software portal is used both for enqueue/dequeue operations on packets, and for acquire/release buffer operations. GPP software is responsible for the portal’s operation mode and usage i.e. sharing vs. affinity, association of queue context, etc.
DPIO objects may serve multiple interfaces. This is not limited to multiple DPSECI objects; it can also be extended to network interfaces and communication interfaces. For example, the same DPIO may serve both a DPNI and a DPSECI, assuming they are assigned to the same software context (container).
16.2.3 Buffer requirements
A DPSECI does not need to be directly associated with a DPBP object; in addition, buffers for the SEC service requests (frames) may or may not be managed by buffer pools. However, SEC response frames are usually built by allocation of buffers from BMan buffer pools; therefore, GPP software should specify in the SEC service requests which buffer pool ID to use for allocating the response buffer. The buffer pool ID can be retrieved from the DPBP object (please refer to the DPBP API description).
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-3
16.3 DPSECI command referenceThis section contains the detailed programming model of DPSECI commands.
16.3.1 DPSECI_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPSECI_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
Figure 482. DPSECI_OPEN Command Description
The following table describes the command fields.1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x809 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPSECI_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 27. DPSECI_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPSECI_ID
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-4
16.3.2 DPSECI_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 483. DPSECI_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-5
16.3.3 DPSECI_CREATE
This command creates and initializes an instance of DPSECI according to the specified command parameters. This command is not required for DPSECI instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 484. DPSECI_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x909 — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x08 PRIORITIES7 PRIORITIES6 PRIORITIES5 PRIORITIES4 PRIORITIES3 PRIORITIES2 PRIORITIES1 PRIORITIES0
63 16 15 8 7 0
0x10 — NUM_RX_QUEUES
NUM_TX_QUEUES
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 28. DPSECI_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 PRIORITIES[0-7] Priorities for the SEC hardware processing; valid priorities are configured with values 1-8; the entry following last valid entry should be configured with 0
0x10 0-7 NUM_TX_QUEUES num of queues towards the SEC
8-15 NUM_RX_QUEUES num of queues back from the SEC
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-6
16.3.4 DPSECI_DESTROY
Command structure
Figure 485. DPSECI_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-7
16.3.5 DPSECI_ENABLE
Command structure
Figure 486. DPSECI_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-8
16.3.6 DPSECI_DISABLE
Command structure
Figure 487. DPSECI_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-9
16.3.7 DPSECI_IS_ENABLED
Command structure
Figure 488. DPSECI_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-10
Response structure
Figure 489. DPSECI_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-11
16.3.8 DPSECI_RESET
Command structure
Figure 490. DPSECI_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-12
16.3.9 DPSECI_SET_IRQ
Set IRQ information for the DPSECI to trigger an interrupt.
Command structure
Figure 491. DPSECI_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 8 7 0
0x08 IRQ_VAL IRQ_INDEX
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 IRQ_INDEX Identifies the interrupt index to configure
32-63 IRQ_VAL Value to write into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-13
16.3.10 DPSECI_GET_IRQ
Get IRQ information from the DPSECI.
Command structure
Figure 492. DPSECI_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-14
Response structure
Figure 493. DPSECI_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-15
16.3.11 DPSECI_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 494. DPSECI_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 - 0x3F
– Reserved
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-16
16.3.12 DPSECI_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 495. DPSECI_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-17
Response structure
Figure 496. DPSECI_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-18
16.3.13 DPSECI_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 497. DPSECI_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-19
16.3.14 DPSECI_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 498. DPSECI_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-20
Response structure
Figure 499. DPSECI_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-21
16.3.15 DPSECI_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 500. DPSECI_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPSECI_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-22
Response structure
Figure 501. DPSECI_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-23
16.3.16 DPSECI_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 502. DPSECI_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-24
16.3.17 DPSECI_GET_ATTRIBUTES
Command structure
Figure 503. DPSECI_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-25
Response structure
Figure 504. DPSECI_GET_ATTRIBUTES Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — ID
63 16 15 8 7 0
0x10 — NUM_RX_QUEUES
NUM_TX_QUEUES
63 0
0x18 —
63 0
0x20 —
63 32 31 16 15 0
0x28 —
63 32 31 16 15 0
0x30 — VERSION_MINOR VERSION_MAJOR
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID DPSECI object ID
0x10 0-7 NUM_TX_QUEUES number of queues towards the SEC
8-15 NUM_RX_QUEUES number of queues back from the SEC
0x30 0-15 VERSION_MAJOR DPSECI major version
16-31 VERSION_MINOR DPSECI minor version
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-26
16.3.18 DPSECI_SET_RX_QUEUE
Command structure
Figure 505. DPSECI_SET_RX_QUEUE Command Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x220 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 16 15 0
0x08 — DEST_TYPE
QUEUE DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 33 32 31 0
0x18
OP
E OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPSECI_DEST_NONE' option
40-47 QUEUE Select the queue relative to number of priorities configured at DPSECI creation; use DPSECI_ALL_QUEUES to configure all Rx queues identically.
48-51 DEST_TYPE Destination type. Select one of the supported values:0x0 = DPSECI_DEST_NONE- Unassigned destination; The queue is set in parked mode and does not generate FQDAN notifications; user is expected to dequeue from the queue based on polling or other user-defined method0x1 = DPSECI_DEST_DPIO - The queue is set in schedule mode and generates FQDAN notifications to the specified DPIO; user is expected to dequeue from the queue only after notification is received0x2 = DPSECI_DEST_DPCON - The queue is set in schedule mode and does not generate FQDAN notifications, but is connected to the specified DPCON object; user is expected to dequeue from the DPCON channel
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame; valid only if 'DPSECI_QUEUE_OPT_USER_CTX' is contained in 'options'
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-27
All unspecified fields are reserved and must be cleared (set to zero)
16.3.19 DPSECI_GET_RX_QUEUE
Command structure
Figure 506. DPSECI_GET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
0x18 0-32 OPTIONS Flags representing the suggested modifications to the queue;Use any combination of 'DPSECI_QUEUE_OPT_<X>' flags below:bit 0: DPSECI_QUEUE_OPT_USER_CTX - Select to modify the user's context associated with the queuebit 1: DPSECI_QUEUE_OPT_DEST - Select to modify the queue's destination
32 ORDER_PRESERVATION_EN (OPE) order preservation configuration for the rx queuevalid only if 'DPSECI_QUEUE_OPT_ORDER_PRESERVATION' is contained in ‘options'
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x196 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 0
0x08 — QUEUE
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 40-47 QUEUE Select the queue relative to number of priorities configured at DPSECI creation
Offset Bits Name Description
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-28
Response structure
Figure 507. DPSECI_GET_RX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x196 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — DEST_TYPE
— DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 33 32 31 0
0x18
OP
E
FQID
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPSECI_DEST_NONE' option
48-51 DEST_TYPE Destination type. Select one of the supported values:0x0 = DPSECI_DEST_NONE- Unassigned destination; The queue is set in parked mode and does not generate FQDAN notifications; user is expected to dequeue from the queue based on polling or other user-defined method0x1 = DPSECI_DEST_DPIO - The queue is set in schedule mode and generates FQDAN notifications to the specified DPIO; user is expected to dequeue from the queue only after notification is received0x2 = DPSECI_DEST_DPCON - The queue is set in schedule mode and does not generate FQDAN notifications, but is connected to the specified DPCON object; user is expected to dequeue from the DPCON channel
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame
0x18 0-31 FQID Virtual FQID value to be used for dequeue operations
32 ORDER_PRESERVATION_EN (OPE) Status of the order preservation configuration on the queue
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-29
16.3.20 DPSECI_GET_TX_QUEUE
Command structure
Figure 508. DPSECI_GET_TX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x197 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 0
0x08 — QUEUE —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 40-47 QUEUE Select the queue relative to number of priorities configured at DPSECI creation
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-30
Response structure
Figure 509. DPSECI_GET_TX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x197 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 FQID
63 32 31 0
0x10 — PRIORITY
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 FQID Virtual FQID to be used for sending frames to SEC hardware
0x10 0-31 PRIORITY SEC hardware processing priority for the queue
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-31
16.3.21 DPSECI_GET_SEC_ATTR
Command structure
Figure 510. DPSECI_GET_SEC_ATTR Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x198 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-32
Response structure
Figure 511. DPSECI_GET_SEC_ATTR Response Description
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x198 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 24 23 16 15 0
0x08 — ERA MINOR_REV MAJOR_REV IP_ID
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x10 — CRC_ACC_NUM SNOW_F9_ACC_NUM
SNOW_F8_ACC_NUM
— ZUC_ENC_ACC_NUM
ZUC_AUTH_ACC_NUM
DECO_NUM
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
0x18 AES_ACC_NUM DES_ACC_NUM ARC4_ACC_NUM
MD_ACC_NUM — RNG_ACC_NUM KASUMI_ACC_NUM
PK_ACC_NUM
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 IP_ID ID for SEC.
16-23 MAJOR_REV Major revision number for SEC.
24-31 MINOR_REV Minor revision number for SEC.
32-39 ERA SEC controller era.
0x10 0-7 DECO_NUM The number of copies of the DECO that are implemented in this version of SEC.
8-15 ZUC_AUTH_ACC_NUM The number of copies of ZUCA that are implemented in this version of SEC.
16-24 ZUC_ENC_ACC_NUM The number of copies of ZUCE that are implemented in this version of SEC.
32-39 SNOW_F8_ACC_NUM The number of copies of the SNOW-f8 module that are implemented in this version of SEC.
40-47 SNOW_F9_ACC_NUM The number of copies of the SNOW-f9 module that are implemented in this version of SEC.
48-55 CRC_ACC_NUM The number of copies of the CRC module that are implemented in this version of SEC.
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-33
All unspecified fields are reserved and must be cleared (set to zero)
16.3.22 DPSECI_GET_SEC_COUNTERS
Command structure
Figure 512. DPSECI_GET_SEC_COUNTERS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
0x18 0-7 PK_ACC_NUM The number of copies of the Public Key module that are implemented in this version of SEC.
8-15 KASUMI_ACC_NUM The number of copies of the Kasumi module that are implemented in this version of SEC.
16-24 RNG_ACC_NUM The number of copies of the Random Number Generator that are implemented in this version of SEC.
32-39 MD_ACC_NUM The number of copies of the MDHA (Hashing module) that are implemented in this version of SEC.
40-47 ARC4_ACC_NUM The number of copies of the ARC4 module that are implemented in this version of SEC.
48-55 DES_ACC_NUM The number of copies of the DES module that are implemented in this version of SEC.
56-63 AES_ACC_NUM The number of copies of the AES module that are implemented in this version of SEC.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x199 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
Offset Bits Name Description
DPSECI: Data Path SEC Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 16-34
Response structure
Figure 513. DPSECI_GET_SEC_COUNTERS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x199 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 DEQUEUED_REQUESTS
63 0
0x10 OB_ENC_REQUESTS
63 0
0x18 IB_DEC_REQUESTS
63 0
0x20 OB_ENC_BYTES
63 0
0x28 OB_PROT_BYTES
63 0
0x30 IB_DEC_BYTES
63 0
0x38 IB_VALID_BYTES
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 DEQUEUED_REQUESTS Number of Requests Dequeued
0x10 0-63 OB_ENC_REQUESTS Number of Outbound Encrypt Requests
0x18 0-63 IB_DEC_REQUESTS Number of Inbound Decrypt Requests
0x20 0-63 OB_ENC_BYTES Number of Outbound Bytes Encrypted
0x28 0-63 OB_PROT_BYTES Number of Outbound Bytes Encrypted
0x30 0-63 IB_DEC_BYTES Number of Inbound Bytes Decrypted
0x38 0-63 IB_VALID_BYTES Number of Inbound Bytes Validated
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-1
Chapter 17 DPDCEI: Data Path DCE InterfaceThe MC exports the DPDCEI object as an interface to operate the DPAA2 Data Compression Engine (DCE).
The DPDCEI enables sending frame-based requests to DCE and receiving back the processed response, utilizing the DPAA2 QBMan infrastructure. The DPDCEI object can be configured either for compression mode or for decompression mode (but not for both).
17.1 DPDCEI featuresThe following list summarizes the DPDCEI main features and capabilities:
• A DPDCEI object can be configured either for compression mode or for decompression mode (but not for both). Applications that require both services should create two distinct DPDCEI objects, one for each operation type.
• Supports up to two scheduling priorities for processing service requests.
• Supports one receive queue for incoming response frames.
— DPDCEI response (receive) queue is mapped to one of 8 receive priorities, allowing further prioritization between other interfaces when associating the DPDCEI receive queue to DPIO or DPCON objects.
• Supports different scheduling options for processing received packets:
— DPDCEI receive queue can be configured either in ‘parked’ mode (default), or attached to a DPIO object, or attached to DPCON object
• Allows interaction with one or more DPIO objects for dequeueing/enqueueing frame descriptors (FD) and for acquiring/releasing buffers.
• Supports enable, disable, and reset operations
17.2 DPDCEI command referenceThis section contains the detailed programming model of DPDCEI commands.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-2
17.2.1 DPDCEI_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPDCEI_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
The command format is shown in the figure below.
Figure 514. DPDCEI_OPEN Command Description
The following table describes the command fields.
1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x80D — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPDCEI_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 29. DPDCEI_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPDCEI_ID DPDCEI unique ID
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-3
17.2.2 DPDCEI_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 515. DPDCEI_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-4
17.2.3 DPDCEI_CREATE
This command creates and initializes an instance of DPDCEI according to the specified command parameters. This command is not required for DPDCEI instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 516. DPDCEI_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x90D — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 16 15 8 7 0
0x08 — PRIORITY ENGINE
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 30. DPDCEI_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 ENGINE compression or decompression engine to be selected
8-15 PRIORITY Priority for the DCE hardware processing (valid values 1-8).
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-5
17.2.4 DPDCEI_DESTROY
Command structure
Figure 517. DPDCEI_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-6
17.2.5 DPDCEI_ENABLE
Command structure
Figure 518. DPDCEI_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-7
17.2.6 DPDCEI_DISABLE
Command structure
Figure 519. DPDCEI_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-8
17.2.7 DPDCEI_IS_ENABLED
Command structure
Figure 520. DPDCEI_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-9
Response structure
Figure 521. DPDCEI_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-10
17.2.8 DPDCEI_RESET
Command structure
Figure 522. DPDCEI_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-11
17.2.9 DPDCEI_SET_IRQ
Set IRQ information for the DPDCEI to trigger an interrupt.
Command structure
Figure 523. DPDCEI_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-12
17.2.10 DPDCEI_GET_IRQ
Get IRQ information from the DPDCEI.
Command structure
Figure 524. DPDCEI_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-13
Response structure
Figure 525. DPDCEI_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_PADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-14
17.2.11 DPDCEI_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 526. DPDCEI_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-15
17.2.12 DPDCEI_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 527. DPDCEI_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-16
Response structure
Figure 528. DPDCEI_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-17
17.2.13 DPDCEI_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 529. DPDCEI_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-18
17.2.14 DPDCEI_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 530. DPDCEI_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-19
Response structure
Figure 531. DPDCEI_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-20
17.2.15 DPDCEI_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 532. DPDCEI_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPDCEI_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-21
Response structure
Figure 533. DPDCEI_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-22
17.2.16 DPDCEI_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 534. DPDCEI_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-23
17.2.17 DPDCEI_GET_ATTRIBUTES
Command structure
Figure 535. DPDCEI_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-24
Response structure
Figure 536. DPDCEI_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 — ENGINE ID
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID DPDCEI object ID
32-39 ENGINE DCE engine block
0x10 0-15 VERSION_MAJOR DPDCEI major version
16-31 VERSION_MINOR DPDCEI minor version
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-25
17.2.18 DPDCEI_SET_RX_QUEUE
Command structure
Figure 537. DPDCEI_SET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1B0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — DEST_TYPE
— DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPDCEI_DEST_NONE' option
48-51 DEST_TYPE Destination type
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame;valid only if 'DPDCEI_QUEUE_OPT_USER_CTX' is contained in 'options'
0x18 0-63 OPTIONS Flags representing the suggested modifications to the queue;Use any combination of 'DPDCEI_QUEUE_OPT_<X>' flags
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-26
17.2.19 DPDCEI_GET_RX_QUEUE
Command structure
Figure 538. DPDCEI_GET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1B1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-27
Response structure
Figure 539. DPDCEI_GET_RX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1B1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — DEST_TYPE
— DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 0
0x18 — FQID
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPDCEI_DEST_NONE' option
48-51 DEST_TYPE Destination type
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame;valid only if 'DPDCEI_QUEUE_OPT_USER_CTX' is contained in 'options'
0x18 0-31 FQID Virtual FQID value to be used for dequeue operations
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-28
17.2.20 DPDCEI_GET_TX_QUEUE
Command structure
Figure 540. DPDCEI_GET_TX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-29
Response structure
Figure 541. DPDCEI_GET_TX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A1 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 32 31 0
0x10 — FQID
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-31 FQID Virtual FQID to be used for sending frames to DMA hardware
DPDCEI: Data Path DCE Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 17-30
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-1
Chapter 18 DPDMAI: Data Path DMA InterfaceThe MC exports the DPDMAI object as an interface to operate the DPAA2 QDMA Engine.
The DPDMAI enables sending frame-based requests to QDMA and receiving back confirmation response on transaction completion, utilizing the DPAA2 QBMan infrastructure. DPDMAI object provides up to two priorities for processing QDMA requests.
18.1 DPDMAI featuresThe following list summarizes the DPDMAI main features and capabilities:
• Supports up to two scheduling priorities for processing service requests.
— Each DPDMAI transmit queue is mapped to one of two service priorities, allowing further prioritization in hardware between requests from different DPDMAI objects.
• Supports up to two receive queues for incoming transaction completion confirmations.
— Each DPDMAI receive queue is mapped to one of two receive priorities, allowing further prioritization between other interfaces when associating the DPDMAI receive queues to DPIO or DPCON objects.
• Supports different scheduling options for processing received packets:
— Queues can be configured either in ‘parked’ mode (default), or attached to a DPIO object, or attached to DPCON object
• Allows interaction with one or more DPIO objects for dequeueing/enqueueing frame descriptors (FD) and for acquiring/releasing buffers.
• Supports enable, disable, and reset operations
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-2
18.2 DPDMAI command referenceThis section contains the detailed programming model of DPDMAI commands.
18.2.1 DPDMAI_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPDMAI_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
The command format is shown in the figure below.
Figure 542. DPDMAI_OPEN Command Description
The following table describes the command fields.1
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x80E — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPDMAI_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 31. DPDMAI_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPDMAI_ID DPDMAI unique ID
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-3
18.2.2 DPDMAI_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 543. DPDMAI_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-4
18.2.3 DPDMAI_CREATE
This command creates and initializes an instance of DPDMAI according to the specified command parameters. This command is not required for DPDMAI instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 544. DPDMAI_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x90E — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 16 15 8 7 0
0x08 — PRIORITIES[1] PRIORITIES[0]
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 32. DPDMAI_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-15 PRIORITIES[0..1] Priorities for the DMA hardware processing; valid priorities are configured with values 1-8; the entry following last valid entry should be configured with 0
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-5
18.2.4 DPDMAI_DESTROY
Command structure
Figure 545. DPDMAI_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-6
18.2.5 DPDMAI_ENABLE
Command structure
Figure 546. DPDMAI_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x002 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-7
18.2.6 DPDMAI_DISABLE
Command structure
Figure 547. DPDMAI_DISABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x003 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-8
18.2.7 DPDMAI_IS_ENABLED
Command structure
Figure 548. DPDMAI_IS_ENABLED Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-9
Response structure
Figure 549. DPDMAI_IS_ENABLED Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x006 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 — EN
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Returns '1' if object is enabled; '0' otherwise
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-10
18.2.8 DPDMAI_RESET
Command structure
Figure 550. DPDMAI_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-11
18.2.9 DPDMAI_SET_IRQ
Set IRQ information for the DPDMAI to trigger an interrupt.
Command structure
Figure 551. DPDMAI_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-12
18.2.10 DPDMAI_GET_IRQ
Get IRQ information from the DPDMAI.
Command structure
Figure 552. DPDMAI_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-13
Response structure
Figure 553. DPDMAI_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_PADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-14
18.2.11 DPDMAI_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 554. DPDMAI_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-15
18.2.12 DPDMAI_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 555. DPDMAI_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-16
Response structure
Figure 556. DPDMAI_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-17
18.2.13 DPDMAI_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 557. DPDMAI_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-18
18.2.14 DPDMAI_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 558. DPDMAI_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-19
Response structure
Figure 559. DPDMAI_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-20
18.2.15 DPDMAI_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 560. DPDMAI_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPDMAI_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-21
Response structure
Figure 561. DPDMAI_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-22
18.2.16 DPDMAI_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 562. DPDMAI_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-23
18.2.17 DPDMAI_GET_ATTRIBUTES
Command structure
Figure 563. DPDMAI_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-24
Response structure
Figure 564. DPDMAI_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 — NUM_OF_PRIORITIES
ID
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID DPDMAI object ID
32-39 NUM_OF_PRIORITIES number of priorities
0x10 0-15 VERSION_MAJOR DPDMAI major version
16-31 VERSION_MINOR DPDMAI minor version
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-25
18.2.18 DPDMAI_SET_RX_QUEUE
Command structure
Figure 565. DPDMAI_SET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A0 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — DEST_TYPE
PRIORITY DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPDMAI_DEST_NONE' option
40-47 PRIORITY Select the queue relative to number of priorities configured at DPDMAI creation; use DPDMAI_ALL_QUEUES to configure all Rx queues identically.
48-51 DEST_TYPE Destination type
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame;valid only if 'DPDMAI_QUEUE_OPT_USER_CTX' is contained in 'options'
0x18 0-63 OPTIONS Flags representing the suggested modifications to the queue;Use any combination of 'DPDMAI_QUEUE_OPT_<X>' flags
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-26
18.2.19 DPDMAI_GET_RX_QUEUE
Command structure
Figure 566. DPDMAI_GET_RX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 0
0x08 — PRIORITY —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 40-47 PRIORITY Select the queue relative to number of priorities configured at DPDMAI creation; use DPDMAI_ALL_QUEUES to configure all Rx queues identically.
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-27
Response structure
Figure 567. DPDMAI_GET_RX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A2 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 52 51 48 47 40 39 32 31 0
0x08 — DEST_TYPE
— DEST_PRIORITY DEST_ID
63 0
0x10 USER_CTX
63 32 31 0
0x18 — FQID
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DEST_ID Either DPIO ID or DPCON ID, depending on the destination type
32-39 DEST_PRIORITY Priority selection within the DPIO or DPCON channel; valid values are 0-1 or 0-7, depending on the number of priorities in that channel; not relevant for 'DPDMAI_DEST_NONE' option
48-51 DEST_TYPE Destination type
0x10 0-63 USER_CTX User context value provided in the frame descriptor of each dequeued frame;valid only if 'DPDMAI_QUEUE_OPT_USER_CTX' is contained in 'options'
0x18 0-31 FQID Virtual FQID value to be used for dequeue operations
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-28
18.2.20 DPDMAI_GET_TX_QUEUE
Command structure
Figure 568. DPDMAI_GET_TX_QUEUE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 48 47 40 39 0
0x08 — PRIORITY —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 40-47 PRIORITY Select the queue relative to number of priorities configured at DPDMAI creation;
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-29
Response structure
Figure 569. DPDMAI_GET_TX_QUEUE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x1A3 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 32 31 0
0x10 — FQID
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x10 0-31 FQID Virtual FQID to be used for sending frames to DMA hardware
DPDMAI: Data Path DMA Interface
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 18-30
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-1
Chapter 19 DPAIOP: Data Path AIOP ControlDPAIOP object represents an AIOP tile and is responsible for AIOP tile initialization and management. MC performs initialization of the AIOP tile and its hardware blocks. MC is responsible for loading an AIOP image into appropriate AIOP memory and releasing the AIOP cores for boot.
One of the main responsibilities of MC is loading an image to be used by the AIOP cores. Here are the steps required to load an image. The AIOP cannot run without having a DPAIOP object residing in the container (DPRC) of a GPP software context. that GPP software context will be responsible for controlling the AIOP load and run, through the DPAIOP object.
After an AIOP image was successfully loaded, MC will kick AIOP cores to start running.
19.1 DPAIOP featuresThe following list summarizes the DPAIOP main features and capabilities:
• Create and destroy – DPAIOP object is associated with a single AIOP tile
• Load AIOP software image (including arguments string for the AIOP application)
• Run the AIOP
• Query AIOP state
• Query AIOP Service Layer version
• Set (and get) time of day in AIOP
• Reset the AIOP (not supported in LS2085A revision 1.0)
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-2
19.2 DPAIOP command referenceThis section contains the detailed programming model of DPAIOP commands.
19.2.1 DPAIOP_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPAIOP_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
Figure 570. DPAIOP_OPEN Command Description
The following table describes the command fields.
1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x80A — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPAIOP_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 33. DPAIOP_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPAIOP_ID DPAIOP unique ID
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-3
19.2.2 DPAIOP_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 571. DPAIOP_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-4
19.2.3 DPAIOP_CREATE
This command creates and initializes an instance of DPAIOP according to the specified command parameters. This command is not required for DPAIOP instances that are created using the DPL.
The command format is shown in the figure below.
Command structure
Figure 572. DPAIOP_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x90A — TOKEN — —IN
TR
_DIS
STATUS P — SRCID
63 32 31 0
0x08 AIOP_CONTAINER_ID AIOP_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 34. DPAIOP_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 AIOP_ID AIOP ID
32-63 AIOP_CONTAINER_ID AIOP container ID
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-5
19.2.4 DPAIOP_DESTROY
Command structure
Figure 573. DPAIOP_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-6
19.2.5 DPAIOP_RESET
Command structure
Figure 574. DPAIOP_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-7
19.2.6 DPAIOP_SET_IRQ
Set IRQ information for the DPAIOP to trigger an interrupt.
Command structure
Figure 575. DPAIOP_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 IRQ_INDEX IRQ_VAL
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value to write into IRQ_ADDR address
32-39 IRQ_INDEX Identifies the interrupt index to configure
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-8
19.2.7 DPAIOP_GET_IRQ
Get IRQ information from the DPAIOP.
Command structure
Figure 576. DPAIOP_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-9
Response structure
Figure 577. DPAIOP_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_PADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-10
19.2.8 DPAIOP_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 578. DPAIOP_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-11
19.2.9 DPAIOP_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 579. DPAIOP_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-12
Response structure
Figure 580. DPAIOP_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-13
19.2.10 DPAIOP_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 581. DPAIOP_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-14
19.2.11 DPAIOP_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 582. DPAIOP_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-15
Response structure
Figure 583. DPAIOP_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-16
19.2.12 DPAIOP_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 584. DPAIOP_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state (removing the need for DPAIOP_CLEAR_IRQ_STATUS command). Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-17
Response structure
Figure 585. DPAIOP_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events:None
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-18
19.2.13 DPAIOP_CLEAR_IRQ_STATUS
Clear (mark as handled) pending events of the specified interrupt index.
Command structure
Figure 586. DPAIOP_CLEAR_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x017 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Mask for clearing handled events; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = don’t change event status1 = clear event status bit to indicate that it was handled
32-39 IRQ_INDEX The interrupt index to configure
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-19
19.2.14 DPAIOP_GET_ATTRIBUTES
Command structure
Figure 587. DPAIOP_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-20
Response structure
Figure 588. DPAIOP_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — ID
63 32 31 16 15 0
0x10 — VERSION_MINOR VERSION_MAJOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 ID AIOP ID
0x10 0-15 VERSION_MAJOR DPAIOP major version
16-31 VERSION_MINOR DPAIOP minor version
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-21
19.2.15 DPAIOP_LOAD
Command structure
Figure 589. DPAIOP_LOAD Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x280 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — IMG_SIZE
63 0
0x10 IMG_IOVA
63 0
0x18 OPTIONS
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IMG_SIZE Size of AIOP ELF image in memory (in bytes)
0x10 0-63 IMG_IOVA I/O virtual address of AIOP ELF image
0x18 0-63 OPTIONS AIOP load options
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-22
19.2.16 DPAIOP_RUN
Command structure
Figure 590. DPAIOP_RUN Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x281 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ARGS_SIZE —
63 0
0x10 CORES_MASK
63 0
0x18 OPTIONS
63 0
0x20 ARGS_IOVA
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 ARGS_SIZE Size of AIOP arguments in memory (in bytes)
0x10 0-63 CORES_MASK Mask of AIOP cores to run (core 0 in most significant bit)
0x18 0-63 OPTIONS Execution options (currently none defined)
0x20 0-63 ARGS_IOVA I/O virtual address of AIOP arguments
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-23
19.2.17 DPAIOP_GET_SL_VERSION
Command structure
Figure 591. DPAIOP_GET_SL_VERSION Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x282 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-24
Response structure
Figure 592. DPAIOP_GET_SL_VERSION Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x282 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MINOR MAJOR
63 32 31 0
0x10 — REVISION
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MAJOR AIOP SL major version number
32-63 MINOR AIOP SL minor version number
0x10 0-31 REVISION AIOP SL revision number
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-25
19.2.18 DPAIOP_GET_STATE
Command structure
Figure 593. DPAIOP_GET_STATE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x283 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-26
Response structure
Figure 594. DPAIOP_GET_STATE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x283 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — STATE
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATE AIOP state
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-27
19.2.19 DPAIOP_SET_TIME_OF_DAY
Command structure
Figure 595. DPAIOP_SET_TIME_OF_DAY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x284 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 TIME_OF_DAY
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 TIME_OF_DAY Current number of milliseconds since the Epoch
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-28
19.2.20 DPAIOP_GET_TIME_OF_DAY
Command structure
Figure 596. DPAIOP_GET_TIME_OF_DAY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x285 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-29
Response structure
Figure 597. DPAIOP_GET_TIME_OF_DAY Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x285 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 TIME_OF_DAY
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-63 TIME_OF_DAY Current number of milliseconds since the Epoch
DPAIOP: Data Path AIOP Control
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 19-30
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-1
Chapter 20 DPMCP: Data Path MC PortalThe MC exports the DPMCP object to allow GPP software to control the MC portal operation mode, be it polling mode or interrupt mode.
Each DPMCP object is associated with a single Management Complex Portal, and allows GPP software to configure command completion interrupts for that portal. The DPMCP object is optional if the GPP software is polling the portal and not using portal interrupts. However, for consistency and for better tracking of MC portals that are in use, it is recommended to always create DPMCP objects for MC portals used by GPP.
20.1 DPMCP features
The following list summarizes the DPMCP main features and capabilities:
• DPMCP can be created and destroyed via DPL or dynamically through MC commands.
• IRQ support for command completion.
• Reset support (closes all open tokens on the associated MC portal)
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-2
20.2 DPMCP command referenceThis section contains detailed programming model of DPMCP commands.
20.2.1 DPMCP_OPEN
Open a control session for the specified object.
This function can be used to open a control session for an already created object; an object may have been declared in the DPL or by invoking DPMCP_CREATE command.
This function returns a unique authentication token, associated with the specific object ID and the specific MC portal; this token must be used in all subsequent commands for this specific object.
Command structure
Figure 598. DPMCP_OPEN Command Description
The following table describes the command fields.1-
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x80B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 DPMCP_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 35. DPMCP_OPEN Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 DPMCP_ID DPMCP unique ID
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-3
20.2.2 DPMCP_CLOSE
Close the control session of the object.
After this function is called, no further operations are allowed on the object without opening a new control session.
Command structure
Figure 599. DPMCP_CLOSE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
20.2.3 DPMCP_CREATE
This command creates and initializes an instance of DPMCP according to the specified command parameters. This command is not required for DPMCP instances that are created using the DPL.
The command format is shown in the figure below.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x800 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-4
Command structure
Figure 600. DPMCP_CREATE Command Description
The following table describes the command fields.1-5
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x90B — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 — PORTAL_ID
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Table 36. DPMCP_CREATE Command Field Descriptions1
1 All unspecified fields are reserved and must be cleared (set to zero)
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 PRTAL_ID Portal ID
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-5
20.2.4 DPMCP_DESTROY
Command structure
Figure 601. DPMCP_DESTROY Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x900 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-6
20.2.5 DPMCP_RESET
Command structure
Figure 602. DPMCP_RESET Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x005 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-7
20.2.6 DPMCP_SET_IRQ
Set IRQ information for the DPMCP to trigger an interrupt.
Command structure
Figure 603. DPMCP_SET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x010 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 8 7 0
0x08 IRQ_VAL IRQ_INDEX
63 0
0x10 IRQ_ADDR
63 32 31 0
0x18 IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-7 IRQ_INDEX Identifies the interrupt index to configure
32-63 IRQ_VAL Value to write into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that must be written to signal a message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-8
20.2.7 DPMCP_GET_IRQ
Get IRQ information from the DPMCP.
Command structure
Figure 604. DPMCP_GET_IRQ Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-9
Response structure
Figure 605. DPMCP_GET_IRQ Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 – IRQ_VAL
63 0
0x10 IRQ_PADDR
63 32 31 0
0x18 TYPE IRQ_NUM
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 IRQ_VAL Value that is written into IRQ_ADDR address
0x10 0-63 IRQ_ADDR Address that is written when signalling the message-based interrupt
0x18 0-32 IRQ_NUM A user defined number associated with this IRQ
32-63 TYPE Interrupt type:0 represents message-based interrupt (both IRQ_ADDR and IRQ_VAL are valid)
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-10
20.2.8 DPMCP_SET_IRQ_ENABLE
Set overall interrupt state. Allows GPP software to control when interrupts are generated. Each interrupt can have up to 32 causes. The enable/disable control's the overall interrupt state. if the interrupt is disabled no causes will cause an interrupt.
Command structure
Figure 606. DPMCP_SET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x012 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 1 0
0x08 – IRQ_INDEX – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN Interrupt state: set to ‘1’ to enable, ‘0’ to disable
32-39 IRQ_INDEX Identifies the interrupt index to configure
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-11
20.2.9 DPMCP_GET_IRQ_ENABLE
Get overall interrupt state.
Command structure
Figure 607. DPMCP_GET_IRQ_ENABLE Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x013 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX Identifies the interrupt index to query
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-12
Response structure
Figure 608. DPMCP_GET_IRQ_ENABLE Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x011 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 1 0
0x08 – EN
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0 EN This bit is set if the interrupt is enabled
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-13
20.2.10 DPMCP_SET_IRQ_MASK
Set the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Command structure
Figure 609. DPMCP_SET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
20.2.11 DPMCP_GET_IRQ_MASK
Get the interrupt mask. Every interrupt can have up to 32 causes and the interrupt model supports masking/unmasking each cause independently.
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x014 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
32-39 IRQ_INDEX The interrupt index to configure
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-14
Command structure
Figure 610. DPMCP_GET_IRQ_MASK Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX –
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-39 IRQ_INDEX The interrupt index to query
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-15
Response structure
Figure 611. DPMCP_GET_IRQ_MASK Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x015 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 MASK
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 MASK Event mask for triggering the interrupt; See GET_IRQ_STATUS command for specification of available events. For each bit in MASK:0 = ignore event1 = event is valid; signal the IRQ if this event occurs
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-16
20.2.12 DPMCP_GET_IRQ_STATUS
Get the current status of pending events for the specified interrupt index.
Command structure
Figure 612. DPMCP_GET_IRQ_STATUS Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 40 39 32 31 0
0x08 – IRQ_INDEX STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Optional: any STATUS bits that are set will be cleared from pending state. Note that the STATUS returned in the response is the status before the events are cleared.
Supported events: see response structure definition
32-39 IRQ_INDEX The interrupt index to query
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-17
Response structure
Figure 613. DPMCP_GET_IRQ_STATUS Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x016 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 STATUS
63 0
0x10 –
63 0
0x18 –
63 0
0x20 –
63 0
0x28 –
63 0
0x30 –
63 0
0x38 –
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 0-31 STATUS Events status mask, one bit per event:0 = no interrupt pending1 = interrupt pending
Supported events for IRQ 0:Bit 0: DPMCP_IRQ_EVENT_CMD_DONE – indicates completion of last command
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-18
20.2.13 DPMCP_GET_ATTRIBUTES
Command structure
Figure 614. DPMCP_GET_ATTRIBUTES Command Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 0
0x08 —
63 0
0x10 —
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-19
Response structure
Figure 615. DPMCP_GET_ATTRIBUTES Response Description
All unspecified fields are reserved and must be cleared (set to zero)
Offset from Management Command Portal base Read-Write Access
63 52 51 48 47 38 37 32 31 25 24 23 16 15 14 8 7 0
0x00 CMDID = 0x004 — TOKEN — —
INT
R_D
IS
STATUS P — SRCID
63 32 31 0
0x08 ID —
63 32 31 16 15 0
0x10 — MINOR MAJOR
63 0
0x18 —
63 0
0x20 —
63 0
0x28 —
63 0
0x30 —
63 0
0x38 —
Offset Bits Name Description
0x00 0-63 Command header Refer to Table 2 for the command portal’s general field descriptions.CMDID must be set as specified in the figure above.
0x08 32-63 ID DPMCP object ID
0x10 0-15 MAJOR DPMCP major version
16-31 MINOR DPMCP minor version
DPMCP: Data Path MC Portal
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 20-20
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-1
Chapter 21 Memory Map and Register DefinitionThe MC CCSR space consists of a 64kB block assignment in the SoC CCSR map, and is accessible through the CCSR SkyBlue interface. It is assumed that only trusted software is able to access the MC registers, and all MC registers are Little-Endian; all accesses to MC registers must be naturally aligned to 4-byte word only. The MC configuration, control and status registers are summarized in Table 37.
21.1 General Control Register 1 (GCR1)The GCR1, shown in the following figure, contains general control and configuration for the MC.
Table 37. MC Memory Map
Register offset (Trusted access
only)Register Access Reset
Section/Page
0x0000 GCR1—General Control Register 1 R/W 0x0000_0000 21.1/21-1
0x0004 Reserved — — —
0x0008 GSR—General Status Register R/W 0x0000_0000 21.2/21-3
0x000C - 0x001F Reserved — — —
0x0020 MCFBALR—MC Firmware Base Address Low R/W 0x0000_0000 21.3/21-4
0x0024 MCFBAHR—MC Firmware Base Address High R/W 0x0000_0000 21.4/21-4
0x0028 MCFAPR—MC Firmware Attributes and Partitioning Register
R/W 0x0000_0000 21.5/21-5
0x002C - 0x0BEF Reserved — — —
0x0BF0 PSR—Parameter Summary Register R 0x0000_0000 21.6/21-6
0x0BF4 Reserved — — —
0x0BF8 BRR1—Block Revision Register 1 R 0x0000_0000 21.7/21-6
0x0BFC BRR2—Block Revision Register 2 R 0x0000_0000 21.8/21-7
0x0C00 - 0xFFFF Reserved — — —
Offset <see Table 37> Access:GPP Hypervisor & MC
Read/Write
31 30 29 24 23 22 21 16 15 14 13 3 2 1 0
R P1_STOP
P2_STOP
—P1_
RST_bP2_
RST_b—
M1_RST_b
M2_RST_b
— — —G_
RSTW
Reset 32’b0000_0000_0000_0000_0000_0000_0000_0000
Figure 616. General Control Register 1 (GCR1)
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-2
The following table describes the GCR1 fields.
Table 38. GCR1 Field Descriptions
Bits Name Description
0 G_RST MC Global Reset. This bit asserts the reset signals to MC. This bit is self clearing so that MC firmware may use this bit to self reset the entire MC.1’b0 - the global_reset signal is de-asserted1’b1 - the global_reset signal is asserted, Note that this value will automatically revert to 1’b0 after several cycles.
1-13 — Reserved
14 M2_RST_b Command Portals 256-511 Reset. This bit clears all state associated with these command portal. If a portal transaction is received while this bit is cleared, the MC cannot respond to the transaction and the interconnect behavior is undefined. It is recommended that the GPP boot program sample this bit until it reads as not reset (that is, 1’b1) before enabling or performing any accesses to thee MC portals. The result of resetting the command portals after commencing operation without also resetting the entire MC is undefined and should be avoided. This bit is persistent; it is not self clearing.1’b0 - command portals 256-511 are reset. Portal access is disabled.1’b1 - command portals 256-511 operate normally.
15 M1_RST_b Command Portals 0-255 Reset. This bit clears all state associated with these command portal. If a portal transaction is received while this bit is cleared, the MC cannot respond to the transaction and the interconnect behavior is undefined. It is recommended that the GPP boot program sample this bit until it reads as not reset (that is, 1’b1) before enabling or performing any accesses to thee MC portals. The result of resetting the command portals after commencing operation without also resetting the entire MC is undefined and should be avoided. This bit is persistent; it is not self clearing.1’b0 - command portals 0-255 are reset. Portal access is disabled.1’b1 - command portals 0-255 operate normally.
16-21 — Reserved
22 P2_RST_b Processor 2 Reset. This bit asserts the hard_reset signal to MC processor 2 and to watchdog timer 2. This does not reset the debug subsystems of the associated processor. This bit is persistent; it is not self clearing.In contrast to P1_RST_b, GPP should not alter this bit – MC firmware starts and stops MC cores as necessary.1’b0 - the hard_reset signal is asserted1’b1 - the hard_reset signal is de-asserted and the processor is released to run
23 P1_RST_b Processor 1 Reset. This bit asserts the hard_reset signal to MC processor 1 and to watchdog timer 1. This does not reset the debug subsystems of the associated processor. This bit is persistent; it is not self clearing.This bit should be set by a boot program in order to start MC firmware operation. The bit must be set only after the MC firmware has been loaded into system memory and all other MC registers are programmed as described in this section.1’b0 - the hard_reset signal is asserted1’b1 - the hard_reset signal is de-asserted and the processor is released to run
24-29 — Reserved
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-3
21.2 General Status Register (GSR)The GSR, shown in the following figure, contains MC hardware and firmware status.
The following table describes the GSR fields.
30 P2_STOP Processor 2 Stop. This bit stops MC processor 2 clock. The processor clock does not stop immediately. No state is lost. Command portals are not affected by this bit.1’b0 - the processor is released to run (default out of POR)1’b1 - the processor clock is (will be) stopped
31 P1_STOP Processor 1 Stop. This bit stops MC processor 1 clock. The processor clock does not stop immediately. No state is lost. Command portals are not affected by this bit.1’b0 - the processor is released to run (default out of POR)1’b1 - the processor clock is (will be) stopped
Offset <see Table 37> Access:MC & GPP Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RHErr CErr — BC MCS
W
Reset 32’b0000_0000_0000_0000_0000_0000_0000_0000
Figure 617. General Status Register (GSR)
Table 39. GSR Field Descriptions
Bits Name Description
0-7 MCS MC Status. After MC is kicked to run, MC writes boot status to the MCS bits. The boot program should poll the MCS status field until it is set to a non-zero value.The following codes indicate completion status of the MC boot process:0x01 - MC boot completed successfully. System boot can continue normally.0x03 - MC platform general failure.0x07 - MC resource manager initialization failure.0x0B - MC command portals initialization failure.0x0D - QBMan controller initialization failure.0x0F - WRIOP controller initialization failure.0x11 - AIOP controller initialization failure.0x23 - SEC engine initialization failure.0x3D - DPL processing failure. DPL correctness should be verified by user.
8-15 BC Boot Code. This field can be optionally set to the value listed below by the boot program.0xDD - Delay DPL processing by MCAll other values are ignored.
16-29 — Reserved, must be cleared.
Table 38. GCR1 Field Descriptions (continued)
Bits Name Description
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-4
21.3 MC Firmware Base Address Low Register (MCFBALR)This is the least significant portion of the 512MB MC private memory base address within the SoC Internal Address Map. The GPP should program MCFBALR only while the MC is stopped.
The MCFBALR register format is shown in the following figure.
The following table describes the MCFBALR fields.
21.4 MC Firmware Base Address High Register (MCFBAHR)This is the most significant portion of the 512MB MC private memory base address within the SoC Internal Address Map. The GPP should program MCFBAHR only while the MC is stopped.
The MCFBAHR register format is shown in the following figure.
30 CErr Catastrophic Error. Setting this bit asserts the MC Catastrophic_Error pin intended for input to SoC Interrupt Controller. GPP should never set this bit.
31 HErr Hardware Error. When this bit is set, the MC has encountered an internal error condition. GPP should never set this bit.1’b0 - MC is running normally1’b1 - MC is not running or has encountered an internal error. Setting this bit asserts the MC HReset_Req.
Offset <see Table 37> Access:Read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMCFBAR_LOW — MEMSZ
W
Reset 32’b0000_0000_0000_0000_0000_0000_0000_0000
Figure 618. MC Firmware Base Address Low Register (MCFBALR)
Table 40. MCFBALR Field Descriptions
Bits Name Description
0-7 MEMSZ Size of system memory allocated for MC (and DPAA controllers included) by the boot program.The allocated memory must be in multiples of 256MB, and the value (MEMSZ+1) indicates the allocated number of 256MB memory blocks. For example:0x00 – 256MB allocated (do not use this option if the SoC contains an AIOP)0x01 – 512MB allocated...0x07 – 2GB allocatedetc.
8-28 — Reserved
29-31 MCFBAR_LOW MC Firmware Base Address Low. This is the least significant part of the MC private memory base address, corresponding to address bits [31-29]. Bits [47-32] come from MCFBAHR.
Table 39. GSR Field Descriptions (continued)
Bits Name Description
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-5
The following table describes the MCFBAHR fields.
21.5 MC Firmware Attributes and Partitioning Register (MCFAPR)The MCFARP is the isolation context identifier and memory access qualifiers that the MC uses, attaches as transaction attribute, when accessing any location within its 512MB private memory block in the SoC internal address map. The GPP should program MCFAPR only when the MC is stopped.
The following table describes the MCFAPR fields.
Offset <see Table 37> Access:Read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R— MCFBAR_HIGH
W
Reset 32’b0000_0000_0000_0000_0000_0000_0000_0000
Figure 619. MC Firmware Base Address High Register (MCFBAHR)
Table 41. MCFBAHR Field Descriptions
Bits Name Description
0-16 MCFBAR_HIGH MC Firmware Base Address High. This is the most significant part of the MC private memory base address, corresponding to address bits [48-32]. Bits [31-29] come from MCFBALR.
17-31 — Reserved
Offset <see Table 37> Access:Read-write
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R— PL BMT — — ICID
W
Reset 32’b0000_0000_0000_0000_0000_0000_0000_0000
Figure 620. MC Firmware Attributes and Partitioning Register (MCFAPR)
Table 42. MCFAPR Field Descriptions
Bits Name Description
0-14 ICID ICID. This is the Isolation Context ID value used by the PAMU/SMMU for address translation if the Privilege Level bit is set.
15-16 — Reserved
17 BMT Bypass Memory Translation. This attribute forces bypassing of IOMMU translation.
18 PL Privilege Level. If this bit is set, MC interrupt transactions are labeled using the ICID (Isolation Context ID) field, and are passed through the IOMMU for translation to the SoC internal Address Map. If this bit is cleared, all MC support transactions bypass the IOMMU and the ICID value is unused.
19-31 — Reserved
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-6
21.6 Parameter Summary Register (PSR)PSR, shown in the following figure, provides a summary of the parameterized features for this MC implementation.
NOTEThis register may be removed or modified by the design team; however, the information contained in the register should be provided in some way.
The following table describes the PSR1 fields.
21.7 Block Revision Register 1 (BRR1)BRR1, shown in the following figure, provides MC IP block revision information.
The following table describes the BRR1 fields.
Offset <see Table 37> Access:Read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PROCS ADDR_W DPAA_INTS CMD_PORTALS
W
Reset 0x2 0x9 0x60 0x01FF
Figure 621. Parameter Summary Register 1 (PSR1)
Table 43. PSR1 Field Descriptions
Bits Name Description
0-15 CMD_PORTALS Command Portals - The total number of command portals implemented in all the CPMs in the MC
16-23 DPAA_INTS DPAA2 Interrupt Inputs - The amount of uncommitted DPAA2 interrupt input signals available for connection to other DPAA2 IP blocks.
24-27 ADDR_W External Address Physical Width - The width of the SoC platform address.Values: 0x0 = 32 bits, 0x2 = 36 bits, 0x4 = 40 bits, 0x6 = 44 bits, 0x8 = 48 bits, 0x9 = 49 bits
28-31 PROCS Total number of processors (cores or hardware threads) implemented within MC
Offset <see Table 37> Access:Read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IPMN IPMJ IPID
W
Reset 0x00 - Implementation specific 0x01 - Implementation specific 0x0A00
Figure 622. Block Revision Register 1 (BRR1)
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-7
21.8 Block Revision Register 2 (BRR2)BRR2, shown in the following figure, provides information about the IP block integration and configuration options. Note, that version information in this register is of the hardware block and not of the loaded firmware.
The following table describes the BRR2 fields.
Table 44. BRR1 Field Descriptions
Bits Name Description
0-15 IPID IP block ID - 0x0A00 denotes Management Complex
16-23 IPMJ The major revision of the IP block. 0x01 in the initial MC implementation.
24-31 IPMN The minor revision of the IP block. 0x00 in the initial MC implementation.
Offset <see Table 37> Access:Read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IPCFGO—
IPINTO—
W
Reset 0x00 - Implementation specific 0x00 0x00 - Implementation specific 0x00
Figure 623. Block Revision Register 2 (BRR2)
Table 45. BRR2 Field Descriptions
Bits Name Description
0-7 — Reserved
8-15 IPINTO IP block integration options - This field is set to 0x00 for the initial MC implementation.
16-23 — Reserved
24-31 IPCFGO IP block configuration options - This field is set to 0x00 for the initial MC implementation.
Memory Map and Register Definition
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 21-8
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-1
Chapter 22 Data Path Layout (DPL) ReferenceSystems do not need to dynamically create and destroy DPAA2 objects, and system design can be simpler if the DPAA2 objects topology is declared statically at boot time. The MC is capable of consuming a binary data structure named the Data Path Layout (DPL) that describes the initial a set of objects created when the system is initialized; it is processed only once when the MC is initialized.
The DPL is based on a text source file that is similar in syntax to a device tree source file, and compiled with DTC (Device Tree Compiler) to form a binary structure (blob). This binary structure is loaded by the SoC boot program (U-Boot, for example) as an MC input. The purpose of the DPL is not to describe hardware attributes, but rather to describe the initial topology and attributes of logical objects that the MC should create.
This section describes the DPL syntax. The DPL source file syntax is a ‘tree’ of named nodes and properties. Nodes contain properties (name and value pairs), and also optionally child nodes.
22.1 High-level DPL structureThe DPL structure is composed of three top-level nodes:
• “containers”—defines the initial set of containers in the system, where each container represents a different software context that needs DPAA2 objects. This node also gives the initial assignment of DPAA2 objects and resources to different containers.
• “objects”—defines the initial set of DPAA2 objects and their attributes.
• “connections”—defines connections between DPAA2 network objects; allows users to set up a required network topology.
Example – high level DPL structure:
/dts-v1/;/ {
containers {. . .
};objects {
. . .};connections {
. . .};
};
The following sections describe each of the top-level nodes in more detail.
22.2 Node: containersThe “containers” node contains the initial set of ICID pools for the MC, as well as initial set of containers with their assigned DPAA2 resources and objects; the “containers” node has no properties of its own.
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-2
22.2.1 Child node: dprc
The “dprc” node specifies an instantiation of the Data Path Resource Container (DPRC), where the container ID is as specified in the node name “dprc@<id>”. The “dprc” node contains three sections: container properties, and two child nodes: “resources” and “objects”.
Table 46. Properties of “dprc” node
PropertyRequired / Optional
Expected Value(s) Description
parent R “dprc@<id>”, or “none” Containers hierarchy is set by specifying the parent container ID, or use “none” if this is a root-level container
icid O <uint16_t> or“DPRC_GET_ICID_FROM_POOL”
Select specific ICID value for the child container, or use “DPRC_GET_ICID_FROM_POOL” (default value) to have MC allocate the ICID from the pool of free ICID values
portal_id O <int>or“DPRC_GET_PORTAL_ID_FROM_POOL”
Primary MC command portal for this container, or use “DPRC_GET_PORTAL_ID_FROM_POOL” (default value) to have MC allocate the portal ID from the pool of free portals
options O Zero or more of comma-separated options may be selected from the list below. If this property is omitted, none of these options will be set.
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-3
22.2.1.1 Child node: resources
The “resources” node lists specific container resource assignment. The “resources” node has no properties of its own, and it only contains child “res” nodes.
22.2.1.1.1 Child node: res
The “res@<n>” node declares a specific resource assignment; multiple “res” nodes may be declared in a “resources” node. The value of <n> has no significance.
“DPRC_CFG_OPT_SPAWN_ALLOWED” The container is allowed to spawn its own child containers
“DPRC_CFG_OPT_ALLOC_ALLOWED” The container is allowed to allocate resources from its parent container; if not set, the container is only allowed to use resources from its own pools. This is the container's global policy, but the parent container may override it and set specific quota for each resource type.
“DPRC_CFG_OPT_OBJ_CREATE_ALLOWED” The software context associated with this container is allowed to create new objects
“DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED” The software context associated with this container is allowed to invoke topology changes, such as connect or disconnect of objects
“DPRC_CFG_OPT_AIOP” The container is associated with the AIOP
“DPRC_CFG_OPT_IRQ_CFG_ALLOWED” The software context associated with this container is allowed to set IRQ configuration for objects
label O up to 16 characters Container’s label
PropertyRequired / Optional
Expected Value(s) Description
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-4
Table 47. Properties of “res” node
PropertyRequired / Optional
Expected Value(s) Description
type R Name of resource pool (specify only one from the list below).Note that resource pool types may differ between SoC variants.
“mcp” MC portals
“swp” QBMan SW portals
“bp” QBMan buffer pools
“fq” QBMan frame queues
“qpr” QBMan queuing priority records
“qd” QBMan queuing destinations
“cg” QBMan congestion groups
“swpch” QBMan software portal channels
“cqch” QBMan class queue channels
“rplr” QBMan replication list records
“ifp.wr0” WRIOP interface profiles
“kp.wr0.ctlue” WRIOP CTLU egress key profiles
“kp.wr0.ctlui” WRIOP CTLU ingress key profiles
“prp.wr0.ctlue” WRIOP CTLU egress parser profiles
“prp.wr0.ctlui” WRIOP CTLU ingress parser profiles
“plcy.wr0.ctlui” WRIOP CTLU ingress policy tables
“plcye.wr0.ctlui” WRIOP CTLU ingress policy entries
“kp.aiop0.ctlu” AIOP CTLU key profiles
“kp.aiop0.mflu” AIOP MFLU key profiles
“prp.aiop0.ctlu” AIOP CTLU parser profiles
“prp.aiop0.mflu” AIOP MFLU parser profiles
num R <uint32_t> Number of resources to assign
options O Select only one of the resource allocation options below, or none (omit this property or set to <0>).Note the impact on ‘id_base_align’ property.
“DPRC_RES_REQ_OPT_EXPLICIT” Indicates that requested resources are explicit and sequential, with base ID as specified by ‘id_base_align’ property
“DPRC_RES_REQ_OPT_ALIGNED” Indicates that resources’ base ID should be aligned to the value specified by ‘id_base_align’ property
id_base_align R <int> In case of explicit assignment, indicates the base (first) resource ID for the allocation.In case of aligned (and non-explicit) assignment, indicates the required alignment for the resource ID(s); set to <0> if no special alignment is required.
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-5
22.2.1.2 Child node: objects
The “objects” node lists specific container object assignment for the container. The “objects” node has no properties of its own, and it only contains child “obj” nodes.
22.2.1.2.1 Child node: obj
The “obj@<n>” node declares a specific object assignment; multiple “obj” nodes may be declared in an “objects” node. The value of <n> has no significance.
Table 48. Properties of “obj” node
22.2.1.2.2 Child Node: obj_set
The “obj_set@<n>” node declares a set of a specific object assignment; multiple “obj_set” nodes may be declared in an “objects” node. The value of <n> has no significance.
PropertyRequired / Optional
Expected Value(s) Description
obj_name R “<object>@<id>”
Examples: “dpni@3”, “dpsw@5”
Object name and ID
plugged O <0> or <1> Indicates if the object is considered plugged to the container, or not. Default value is <1>. If this property is omitted, the object is considered plugged.
label O up to 16 characters Object’s label
PropertyRequired / Optional
Expected Value(s) Description
type R up to 16 characters
Examples: “dpni”, “dpsw”
Object type
ids R <Array of int> The required IDs for objects in set
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-6
Example – declare a root-level container DPRC-1, with ICID 11, two configuration options, primary command portal 7, additional command portals 15-16, and some DPAA2 objects assigned to the DPRC: a set of four DPNI objects (with IDs: 1,2,5,30) and a single DPBP object (with ID=1 and a label):
dprc@1 {parent = "none"; icid = <11>;portal_id = <7>;options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED";resources {
res@1 {type = "mcp";num = <2>;options = <1>;id_base_align = <15>;
};};objects {
obj_set@1{type = "dpni";ids = <1 2 5 30>;
};obj@1{
obj_name = "dpbp@1";label = “my label”;
};};
};
22.3 Node: objectsThe top-level “objects” node, not to be confused with the child node of “dprc” node, contains the initial set of objects created during boot by MC. The “objects” node has no properties of its own, and it only contains child nodes that specify the different object attributes. Objects in this section are assigned to any of the containers declared previously in the “containers” section.
Objects declared in the DPL are created during MC initialization, and do NOT need to be created later using CREATE commands. These objects are available to their associated software contexts by submitting an OPEN command for each object.
22.3.1 Child node: dpni
The “dpni” node specifies an instantiation of Data Path Network Interface (DPNI) object, where the DPNI ID is as specified in the node name “dpni@<id>”.
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-7
Table 49. Properties of “dpni” node
PropertyRequired / Optional
Expected Value(s) Description
mac_addr R <six uint8_t values separated by spaces> Primary MAC address
max_senders O <uint8_t> Maximum number of different network interface senders; used as the number of dedicated Tx flows; <0> is treated as <1>
options O One or more of comma-separated options may be selected from the list below.
“DPNI_OPT_ALLOW_DIST_KEY_PER_TC” Support different distribution key per receive traffic class
“DPNI_OPT_PRIVATE_TX_CONF_ERR_DISABLED”
Disable private Tx confirmation/error queues
“DPNI_OPT_TX_CONF_DISABLED” Disable all Tx confirmation
“DPNI_OPT_DIST_HASH” Support hash-based distribution
“DPNI_OPT_DIST_FS” Support distribution by explicit flow steering
“DPNI_OPT_POLICING” Support policing
“DPNI_OPT_UNICAST_FILTER” Support unicast filtering
“DPNI_OPT_MULTICAST_FILTER” Support multicast filtering
“DPNI_OPT_VLAN_FILTER” Support VLAN filtering
“DPNI_OPT_IPR” Support IP reassembly
“DPNI_OPT_IPF” Support IP fragmentation
“DPNI_OPT_VLAN_MANIPULATION” Support VLAN add/remove
“DPNI_OPT_QOS_MASK_SUPPORT” Support masking of QoS lookup keys
“DPNI_OPT_FS_MASK_SUPPORT” Support masking of flow steering lookup keys
max_tcs O <uint8_t> Maximum number of traffic classes (1-8); affects both transmit and receive flows; <0> is treated as <1>
max_dist_per_tc O <‘max_tcs’ (up to 8) uint16_t values separated by spaces>
Maximum distribution size per receive traffic class; determines the maximum number of receive queues and DPIO objects that can be referenced by this traffic class.Valid only if “DPNI_OPT_DIST_HASH” or “DPNI_OPT_DIST_FS” options are set.
max_fs_entries_per_tc O <‘max_tcs’ (up to 8) uint16_t values separated by spaces>
Maximum FS entries for Rx traffic class;'0' means no support for this TC;
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-8
max_unicast_filters O <uint8_t> Maximum number of unicast filters; '0' is treated as 'DPNI_MAX_NUM_OF_UNICAST_FILTERS'.Valid only if “DPNI_OPT_UNICAST_FILTER” option is set.
max_multicast_filters O <uint8_t> Maximum number of multicast filters; '0' is treated as 'DPNI_MAX_NUM_OF_MULTICAST_FILTERS’.Valid only if “DPNI_OPT_MULTICAST_FILTER” option is set.
max_vlan_filters O <uint8_t> Maximum number of VLAN filters; '0' is treated as 'DPNI_MAX_NUM_OF_VLAN_FILTERS'.Valid only if “DPNI_OPT_VLAN_FILTER” option is set.
max_qos_entries O <uint8_t> If 'max_tcs' is greater than 1, declares the maximum entries for the QoS table; '0' is treated as 'DPNI_MAX_NUM_OF_QOS_ENTRIES'.Valid only if “max_tcs” > 1.
max_qos_key_size O <uint8_t> Maximum key size for the QoS table; '0' will be treated as '24' which enough for IPv4 5-tuple.Valid only if “max_tcs” > 1.
max_dist_key_size O <uint8_t> Maximum key size for distribution; '0' will be treated as '24' which enough for IPv4 5-tuple.Valid only if “DPNI_OPT_DIST_HASH” or “DPNI_OPT_DIST_FS” options are set.
max_policers O <uint8_t> Maximum number of policers;should be between '0' and max_tcs
max_congestion_ctrl O <uint8_t> Maximum number of congestion control groups; covers early drop and congestion notification requirements;should be between '0' and ('max_tcs' + 'max_senders')
max_open_frames_ipv4 O <uint16_t> Maximum concurrent IPv4 packets in reassembly process
PropertyRequired / Optional
Expected Value(s) Description
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-9
Example – declare DPNI-1 object with Unicast filter (16 entries), VLAN filter (16 entries), and QoS support for 3 traffic classes, with 48-bytes key size and 32 QoS table entries.
dpni@1{mac_addr = <0 1 1 4 1 3>;max_senders = <2>;options = “DPNI_OPT_UNICAST_FILTER”, “DPNI_OPT_VLAN_FILTER”, max_tcs = <3>;max_dist_per_tc = <1 1 1>; max_unicast_filters = <16>;max_multicast_filters = <0>;max_vlan_filters = <16>;max_qos_entries = <32>;max_qos_key_size = <48>;max_dist_key_size = <0>;
};
22.3.2 Child node: dpio
The “dpio” node specifies an instantiation of Data Path I/O (DPIO) object, where the DPIO ID is as specified in the node name “dpio@<id>”.
Table 50. Properties of “dpio” node
Example – declare DPIO-3 object with a local notifications channel and 8 priority classes for notifications:
max_open_frames_ipv6 O <uint16_t> Maximum concurrent IPv6 packets in reassembly process
max_reass_frm_size O <uint16_t> Maximum size of the reassembled frame
min_frag_size_ipv4 O <uint16_t> Minimum fragment size of IPv4 fragments
min_frag_size_ipv6 O <uint16_t> Minimum fragment size of IPv6 fragments
PropertyRequired / Optional
Expected Value(s) Description
channel_mode R Select only one of the options from the list below
“DPIO_NO_CHANNEL” No notification channel
“DPIO_LOCAL_CHANNEL” Notifications associated with this DPIO will be received at the DPIO’s dedicated channel
num_priorities R <uint8_t> Number of priorities (1-8); relevant only if “DPIO_LOCAL_CHANNEL” is selected
PropertyRequired / Optional
Expected Value(s) Description
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-10
dpio@3{channel_mode = "DPIO_LOCAL_CHANNEL";num_priorities = <8>;
};
22.3.3 Child node: dpbp
The “dpbp” node specifies an instantiation of Data Path Buffer Pool (DPBP) object, where the DPBP ID is as specified in the node name “dpbp@<id>”.
Table 51. Properties of “dpbp” node
Example – declare DPBP-5 object (no other properties are required):
dpbp@5{};
22.3.4 Child node: dpcon
The “dpcon” node specifies an instantiation of Data Path Concentrator (DPCON) object, where the DPCON ID is as specified in the node name “dpcon@<id>”.
Table 52. Properties of “dpcon” node
Example – declare DPCON-1 object with 4 priority classes for scheduling.dpcon@1{
num_priorities = <4>;};
22.3.5 Child node: dpci
The "dpci” node specifies an instantiation of Data Path Communication Interface (DPCI) object, where the DPCI ID is as specified in the node name “dpci@<id>”.
PropertyRequired / Optional
Expected Value(s) Description
N/A
PropertyRequired / Optional
Expected Value(s) Description
num_priorities R <uint8_t> Number of priorities (1-8) for scheduling
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-11
Table 53. Properties of “dpci” node
Example – declare DPCI-1 object with 2 receive priorities.dpci@1{
num_priorities = <2>;};
22.3.6 Child node: dpseci
The ”dpseci” node specifies an instantiation of Data Path SEC Interface (DPSECI) object, where the DPSECI ID is as specified in the node name ”dpseci@<id>”.
Table 54. Properties of “dpseci” node
Example – declare DPSECI-1 object with 2 priorities for hardware processing.dpseci@1{
priorities = <2 5 1 2 3 4 3 1>;};
22.3.7 Child node: dpdmux
The “dpdmux” node specifies an instantiation of Data Path DeMux (DPDMUX) object, where the DPDMUX ID is as specified in the node name “dpdmux@<id>”.
PropertyRequired / Optional
Expected Value(s) Description
num_priorities R <uint8_t> Number of receive priorities (queues) for the DPCI; valid range is 1-2.
PropertyRequired / Optional
Expected Value(s) Description
priorities R < 1 to 8 uint8_t values separated by spaces> Priorities for the SEC hardware processing; valid priorities are configured with values 1-8; if a single priority is required, set the second priority to 0.
num_tx_queues O <uint8_t> Num of queues towards the SEC
num_rx_queues O <uint8_t> Num of queues back from the SEC
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-12
Table 55. Properties of “dpdmux” node
Example – declare DPDMUX-1 object with 4 internal interfaces, no manipulation, and demux done based on MAC and VLAN:
dpdmux@1{method = “DPDMUX_METHOD_C_VLAN_MAC”;manip = “DPDMUX_MANIP_NONE”;num_ifs = <4>;
};
PropertyRequired / Optional
Expected Value(s) Description
method R Defines the method of the DPDMUX address table.
“DPDMUX_METHOD_C_VLAN_MAC” DeMux based on C-VLAN and MAC address
“DPDMUX_METHOD_MAC” DeMux based on MAC address
“DPDMUX_METHOD_C_VLAN” DeMux based on C-VLAN
“DPDMUX_METHOD_S_VLAN” DeMux based on S-VLAN
manip O Required manipulation operation. Default is “DPDMUX_MANIP_NONE”
“DPDMUX_MANIP_NONE” No manipulation on frames
“DPDMUX_MANIP_ADD_REMOVE_S_VLAN” Add S-VLAN on egress, remove it on ingress
num_ifs R <uint16_t> Number of interfaces (excluding the uplink interface)
options O DPDMUX configuration options; One or more of comma-separated options may be selected from the list below.
“DPDMUX_OPT_BRIDGE_EN” Enable bridging between internal interfaces; allowed only if selected “method” is either “DPDMUX_METHOD_C_VLAN_MAC” or “DPDMUX_METHOD_MAC”
max_dmat_entries O <uint16_t> Maximum entries in DPDMUX address table; 0 indicates default: 64 entries per interface
max_mc_groups O <uint16_t> Number of multicast groups in DPDMUX table; 0 indicates default: 32 multicast groups
max_vlan_ids O <uint16_t> max vlan ids allowed in the system -relevant only case of working in mac+vlan method.0 indicates default: 16 VLAN ids
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-13
22.3.8 Child node: dpsw
The “dpsw” node specifies an instantiation of Data Path Switch (DPSW) object, where the DPSW ID is as specified in the node name “dpsw@<id>”.
Table 56. Properties of “dpsw” node
Example – declare DPSW-1 object with 8 interfaces.dpsw@1{
num_ifs = <8>;};
22.3.9 Child node: dpmac
The "dpmac" node specifies an instantiation of Data Path MAC (DPMAC) object, where the DPMAC ID is as specified in the node name "dpmac@<id>".
PropertyRequired / Optional
Expected Value(s) Description
num_ifs R <uint16_t> Number of switch interfaces
options O Enable/ disable DPSW features
“DPSW_OPT_FLOODING_DIS” Disable flooding
"DPSW_OPT_CTRL_IF_DIS" Disable control interface
"DPSW_OPT_FLOODING_METERING_DIS" Disable flooding metering
“DPSW_OPT_MULTICAST_DIS” Disable Multicast support
"DPSW_OPT_METERING_EN" Enable metering
max_vlans O <uint16_t> Maximum number of VLANs;0 indicates default: 16 VLANs
max_fdbs O <uint16_t> Maximum number of FDBs;0 indicates default: 16 FDBs
max_fdb_entries O <uint16_t> Number of FDB entries for default FDB table; 0 indicates default: 1024 entries
fdb_aging_time O <uint16_t> Default FDB aging time for default FDB table; 0 indicates default: 300 seconds
max_fdb_mc_groups O <uint16_t> Number of multicast groups in each FDB table; 0 indicates default: 32 multicast groups
max_meters_per_if O <uint8_t> Number of meters per interface
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-14
Table 57. Properties of "dpmac" node
Example — declare DPMAC-1.dpmac@1{
};
22.3.10 Child node: dpdcei
The "dpdcei" node specifies an instantiation of Data Path Data Compression Interface (DPDCEI) object, where the DPDCEI ID is as specified in the node name "dpdcei@<id>".
Table 58. Properties of "dpdcei" node
Example — declare DPDCEI-1.dpdcei@1{
engine = "DPDCEI_ENGINE_COMPRESSION";tx_priority = <1>;
};
22.3.11 Child node: dpdmai
The "dpdmai" node specifies an instantiation of Data Path DMA Interface (DPDMAI) object, where the DPDMAI ID is as specified in the node name "dpmai@<id>".
Table 59. Properties of "dpdmai" node
Example — declare DPDMAI-1.
PropertyRequired / Optional
Expected Value(s) Description
N/A
PropertyRequired / Optional
Expected Value(s) Description
engine R DCE engine block
DPDCEI_ENGINE_COMPRESSION Compression engine
DPDCEI_ENGINE_DECOMPRESSION Decompression engine
priority R <int> Priority for the DCE hardware processing (valid values 1-8).
PropertyRequired / Optional
Expected Value(s) Description
priorities R < 1 or 2 uint8_t values separated by spaces> Priorities for the DMA hardware processing; valid priorities are configured with values 1-8; the entry following last valid entry should be configured with 0.
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-15
dpdmai@1{priorities = <2 5>;
};
22.3.12 Child node: dpmcp
The "dpmcp" node specifies an instantiation of Data Path MC Portal (DPMCP) object, where the DPMCP ID is as specified in the node name "dpmcp@<id>".
Table 60. Properties of "dpmcp" node
Example — declare DPMCP-1.dpmcp@1{};
22.3.13 Child node: dpaiop
The "dpaiop" node specifies an instantiation of Data Path AIOP (DPAIOP) object, where the DPAIOP ID is as specified in the node name "dpaiop@<id>".
Table 61. Properties of "dpaiop" node
Example — declare DPAIOP-1.dpaiop@1{
aiop_container_id = <1>;
};
22.4 Node: connectionsThe “connections” node specifies the initial object topology. The “connections” node has no properties of its own, and it only contains child nodes that specify the required connections.
22.4.1 Child node: connection
The “connection@<n>” node declares a connection between two objects; multiple “connection” nodes may be declared in a “connections” node. The value of <n> has no significance. The connection is completely symmetric in nature, and therefore the “endpoint1” and “endpoint2” properties below are
PropertyRequired / Optional
Expected Value(s) Description
N/A
PropertyRequired / Optional
Expected Value(s) Description
aiop_container_id R <int> AIOP container ID
Data Path Layout (DPL) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 22-16
interchangeable – there is no significance to which object is listed as “endpoint1” and which is listed as “endpoint2.”
Table 62. Properties of “connection” node
Example – set up one connection between DPNI-1 and DPMAC-2, and another connection between DPMAC-3 and interface #1 of DPSW-1:
connections {connection@1{
endpoint1 = "dpni@1";endpoint2 = "dpmac@2";
};connection@2{
endpoint1 = "dpsw@1/if@1";endpoint2 = "dpmac@3";
};};
PropertyRequired / Optional
Expected Value(s) Description
endpoint1 R “<object>@<id>” or “<object>@<id>/if@<if_id>”
Examples: “dpni@3”, “dpsw@5/if@1”
Object name and ID to connect with endpoint2 object; objects with multiple interfaces (such as DPSW), must specify also the interface ID
endpoint2 R Peer object name and ID to connect with the first object; for objects with multiple interfaces (such as DPSW), must specify also the interface ID
committed_rate O <uint32_t> Committed rate (Mbits/s)
max_rate O <uint32_t> Maximum rate (Mbits/s)
Data Path Configuration (DPC) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 23-1
Chapter 23 Data Path Configuration (DPC) ReferenceThe MC is capable of consuming a binary data structure named the Data Path Configuration (DPC) that describes the initial board configuration when the system is initialized; it is processed only once before MC is initialized.
The DPC is based on a text source file that is similar in syntax to a device tree source file, and compiled with DTC (Device Tree Compiler) to form a binary structure (blob). This binary structure is loaded by the SoC boot program (U-Boot, for example) as an MC input. The purpose of the DPC is to provide inputs to MC on DPAA configuration constraints for current system or board.
This section describes the DPC syntax. The DPC source file syntax is a ‘tree’ of named nodes and properties. Nodes contain properties (name and value pairs), and also optionally child nodes.
0.1 High-level DPC structureThe DPC structure is composed of three top-level nodes:
• “mc_general”—contains general configuration for MC firmware, such as logging options.
• “resources”—contains the initial set of system resources for MC.
• “controllers”—may be used to override the default configuration of DPAA controllers.
• “board_info”—contains various board hardware constraints.
Example – high level DPC structure:
/dts-v1/;/ {
mc_general {. . .
};resources {
. . .};controllers {
. . .};board_info {
. . .};
};
The following sections describe each of the top-level nodes in more detail.
Data Path Configuration (DPC) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 23-2
0.2 Node: mc_generalThe “mc_general” node contains general configuration for MC firmware, such as logging options.
0.2.1 Child node: log
The “log” node specifies the configuration of the log. Table 63. Properties of “log” node
Example – declare log mode ON with ‘debug’ log level:
log {mode = “LOG_MODE_ON”;level = “LOG_LEVEL_DEBUG”;
};
PropertyRequired / Optional
Expected Value(s) Description
mode O “LOG_MODE_ON” set log mode to ON or OFF.default is “LOG_MODE_ON”
“LOG_MODE_OFF”
level O “LOG_LEVEL_GLOBAL” set the requested log level
“LOG_LEVEL_DEBUG”
“LOG_LEVEL_INFO”
“LOG_LEVEL_WARNING”
“LOG_LEVEL_ERROR”
“LOG_LEVEL_CRITICAL”
“LOG_LEVEL_ASSERT”
Data Path Configuration (DPC) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 23-3
0.3 Node: resourcesThe “resources” node contains the initial set of system resources for MC.
0.3.1 Child node: icid_pools
The “icid_pools” node specifies the initial set of ICID pools for MC. The MC uses the ICID pools to assign an ICID value to a newly created container. Multiple “icid_pool” nodes may be declared. A child node is defined for each “icid_pool” as following:
0.3.1.1 Child node: icid_pool
For each “icid_pool” the node name is “icid_pool@<id>”. Table 64. Properties of “icid_pool” node
Example – declare two icid pools:
icid_pools {icid_pool@1 {
base_icid = <0>;num = <10>;
};icid_pool@2 {
base_icid = <30>;num = <100>;
};};
PropertyRequired / Optional
Expected Value(s) Description
base_icid R <uint32_t> First value in the range of ICIDs
num R <int> Number of consequent ICIDs in the pool
Data Path Configuration (DPC) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 23-4
0.4 Node: controllersThe “controllers” node may be used to override the default configuration of DPAA controllers.
0.4.1 Child node: qbman
The “qbman” node may be used to override selected items of the QBMan controller’s default configuration.
Table 65. Properties of “qbman” node
Example – declare QBMAN:
qbman {total_bman_buffers = <1000000>;wq_ch_conversion = <8>;
};
PropertyRequired / Optional
Expected Value(s) Description
total_bman_buffers O <uint32_t> Specify the total number of buffers that the BMan needs to handle.Default is 900K buffers.
wq_ch_conversion O <uint16_t> Specify the number of WQ channels to convert from 8-WQ mode (with 8 priorities) to 2-WQ mode (with 2 priorities). An 8-WQ channel will be converted to four 2-WQ channels. Default is 0.
Data Path Configuration (DPC) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 23-5
0.5 Node: board_infoThe “board_info” node contains various board hardware constraints.
0.5.1 Child node: ports
The “ports” node specifies board-specific configuration of hardware ports.
0.5.1.1 Child node: mac
For each MAC the node name is “mac@<id>”. Table 66. Properties of “mac” node
Example – declare two macs, mac-1 is fixed link and mac-3 is uses PHY-1:
ports {mac@1 {
link_type = “MAC_LINK_TYPE_FIXED”;};mac@3 {
link_type = “MAC_LINK_TYPE_PHY”;phy_id = <1>;
};
};
PropertyRequired / Optional
Expected Value(s) Description
link_type O MAC link types.default is “MAC_LINK_TYPE_FIXED”
“MAC_LINK_TYPE_NONE” MAC has no link
“MAC_LINK_TYPE_FIXED” MAC is fixed link
“MAC_LINK_TYPE_PHY” MAC uses PHY to link
phy_id O <int> In case of “MAC_LINK_TYPE_PHY”, use the phy ID.
Data Path Configuration (DPC) Reference
DPAA2 User Manual, Rev. 2, 05/2016
NXP Semiconductors 23-6