Domino Ckts Using Dual Vt

SHORT PAPER International Journal of Recent Trends in Engineering, Vol 2, No. 7, November 2009

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Low Power, Energy- efficient Domino Logic Circuits

Salendra.Govindarajulu1, Dr.T.Jayachandra Prasad2 1Associate Professor, ECE, RGMCET, JNTU

1Email: [email protected] 2Principal, RGMCET, JNTU 2Email: [email protected]

Abstract— Sub-threshold leakage power is soon expected to dominate the total power consumed by a CMOS circuit in deep submicron ( DSM ) technology. Circuit techniques aimed at lowering leakage currents are therefore highly desirable. In this work, low power CMOS designs using dual threshold voltage ( dual-Vt ) domino logic are proposed. Single threshold voltage ( single-Vt ), standard dual-Vt and modified dual-Vt domino logic circuits regarding power and speed are compared. These design styles are compared by performing detailed transistor-level simulations on bench mark circuits using DSCH3 and Microwind3 CAD tool. Index Terms— CMOS, Delay, Deep Submicron technology, Dual threshold voltage, Energy-efficient circuits, Microwind tool, Power-delay product, Threshold voltage.

I. INTRODUCTION

The power consumed in high performance microprocessors has increased to levels that impose a fundamental limitation to increasing performance and functionality [1]–[3]. If the current trend in increasing power continues, high performance microprocessors will soon consume thousands of watts. The power density of a high performance microprocessor will exceed the power density levels encountered in typical rocket nozzles within the next decade [2]. The generation, distribution, and dissipation of power are at the forefront of current problems faced by the integrated circuit industry [1]–[5]. The application of aggressive circuit design techniques which only focus on enhancing circuit speed without considering power is no longer an acceptable approach in most high complexity digital systems. Dynamic switching power, the dominant component of the total power consumed in current CMOS technologies, is quadratically reduced by lowering the supply voltage. Lowering the supply voltage, however, degrades circuit speed due to reduced transistor currents. Threshold voltages are scaled ______________________________________________

1Salendra.Govindarajulu:- He is working as an Associate Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal, Andhra Pradesh, India. He presented more than 06 International/National Technical Papers. He is a Life Member of ISTE, New Delhi. His interest includes Low Power VLSI CMOS design.

2Dr.T.Jayachandra Prasad:- He is working as a Principal and Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal Andhra Pradesh, India. He presented more than 20 International/National Technical Papers. He is Life Member in IE (I), CALCUTTA, Life Member in ISTE, NEW DELHI, Life Member in

NAFEN, NEW DELHI, and IEEE Member. His interest includes Digital Signal Processing. to reduce the degradation in speed caused by supply voltage scaling while maintaining the dynamic power consumption within acceptable levels [1]–[5]. At reduced threshold voltages, however, subthreshold leakage currents increase exponentially. Energy efficient circuit techniques aimed at lowering leakage currents are, therefore, highly desirable. Domino logic circuit techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics of domino CMOS circuits as compared to static CMOS circuits [7]–[8]. However, deep sub micrometer (DSM) domino logic circuits utilizing low power supply and threshold voltages have decreased noise margins [9] - [11]. As on-chip noise becomes more severe with technology scaling and increasing operating frequencies, error free operation of domino logic circuits has become a major challenge [9], [10], [11]. Domino logic is a CMOS-based evolution of the dynamic logic techniques which is based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing and is developed to speed up circuits. Using this technique, glitch-free operation can be obtained as each gate can make only one transition. But the main problem is that of the charge distribution. The major necessity of making use of CMOS domino logic for the design of combinational logic circuits is that of low-power high-speed operation The focus of this paper is to implement various domino logic circuit techniques which offer better speed, energy-efficiency and noise immunity in DSM technology. The organization of the paper is as follows. A brief review of the sources of power dissipation in CMOS circuits is provided in Section II. In Section III various techniques in domino logic circuits for power reduction are proposed. In Section IV simulation and implementation results are presented. Finally, conclusions are presented in Section V.

II. SOURCES OF POWER DISSIPATION

The power consumed by CMOS circuits can be classified into two categories: A. Dynamic Power Dissipation For a fraction of an instant during the operation of a circuit, both the PMOS and NMOS devices are “on” simultaneously. The duration of the interval depends on

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the input and output transition (rise and fall) times. During this time, a path exists between Vdd and Gnd and a short-circuit current flows. However, this is not the dominant factor in dynamic power dissipation. The major component of dynamic power dissipation arises from transient switching behavior of the nodes. Signals in CMOS devices transition back and forth between the two logic levels, resulting in the charging and discharging of parasitic capacitances in the circuit. Dynamic power dissipation is proportional to the square of the supply voltage. In deep sub-micron processes, supply voltages and threshold voltages for MOS transistors are greatly reduced. This, to an extent, reduces the dynamic power dissipation. B. Static Power Dissipation This is the power dissipation due to leakage currents which flow through a transistor when no transactions occur and the transistor is in a steady state. Leakage power depends on gate length and oxide thickness. It varies exponentially with threshold voltage and other parameters. Reduction of supply voltages and threshold voltages for MOS transistors, which helps to reduce dynamic power dissipation, becomes disadvantageous in this case. The sub threshold leakage current increases exponentially, thereby increasing static power dissipation.

III. CIRCUIT TECHNIQUES

The various techniques proposed in domino logic circuits for power reduction are given as follows. A. Standard single threshold ( low-Vt ) voltage In this, all standard low-threshold voltage transistors ( Vt = 0.4 volts ) are used in implementing the bench mark circuits and are simulated using DSCH and Microwind 3.1. The advantage with low-Vt transistor is that, the propagation delay provided by the transistor is minimum, but the problem with these low-Vt transistors is that, the leakage current and the power dissipation is increased.

B. Standard single threshold ( high-Vt ) voltage In this, all standard high-threshold voltage transistors ( Vt = 0.7 volts ) are used in implementing the bench mark circuits and are simulated using DSCH and Microwind 3.1. The advantage with high-Vt transistor is that, the leakage current and power dissipation is minimum, but the disadvantage is that, the propagation delay increases.

C. Standard dual threshold voltage The requirement of integrated circuits with small running times, low power dissipation, high integration density and high performance resulted in an aggressive downscaling per each technology generation, and lowering of the supply voltage. To meet the performance requirements, the transistor threshold voltage has to be scaled down. Unfortunately, such scaling increases the sub-threshold leakage current, thereby increasing leakage power. One approach in minimizing this sub-threshold leakage current is the Dual-threshold voltage technology.

This Dual Threshold CMOS (DTCMOS) design technique uses fast low threshold voltage (LTV) and slow high threshold voltage (HTV) devices. Thus, the aim of DTCMOS is to maximize the gain in leakage at the HTV devices without worsening the performance of the circuit. It can decrease the leakage greatly, but the performance may be undermined comparing with CMOS. In this, the PMOS and NMOS transistors in the output inverter are used with high Vt and remaining are used with low Vt devices. D. Modified dual-Vt technology This technology is the proposed technology, which is a modification of standard dual-threshold technology. In standard dual-Vt technology, the transistors of the output inverter circuit in CMOS domino logic are introduced with high-Vt transistors. In this modified dual-Vt technology, only the pull-down transistor is introduced with the standard high-Vt transistor and the pull-up transistor is introduced with standard low-Vt transistor.

IV. SIMULATION AND IMPLEMENTATION

In this work, the benchmark circuits using the above four technologies are implemented . The figure of merit used to compare these technologies is Power-Delay Product (PDP). The benchmark circuits implemented are two input OR gate, two input AND gate, two input XOR gate, eight input OR gate and 8x1 Multiplexer. The OR2 gate is illustrated for the proposed technologies which are given below.

Fig.1. OR2 Standard Low-Vt



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Fig.2. OR2 Standard High-Vt

Fig.3. OR2 Standard Dual-Vt

Fig.4. OR2 Modified Dual-Vt

Table 1. OR2 gate

POWER DELAY[nS]

PDP [WS]

STANDARD LOW-Vt

0.178 mW 0.001 0.178x10^-15

STANDARDHIGH-Vt

0.062 µW 0.005 0.31x10^-18

DUAL -Vt 0.027 µW 0.005 0.135x10^-18

MODIFIED DUAL –Vt

0.027 µW 0.005 0.135x10^-18

Table 2. AND2 gate

POWER DELAY[nS]

PDP [WS]

STANDARD LOW-Vt

0.190 mW 0.006 1.14x10^-15

STANDARDHIGH-Vt

0.045µW 0.005 0.225x10^-18

DUAL -Vt 0.0432 µW 0.005 0.216x10^-18

MODIFIED DUAL –Vt

0.0430µW 0.005 0.215x10^-18

Table 3. OR8 gate

POWER DELAY[nS]

PDP [WS]

STANDARD LOW-Vt

0.367 mW 0.004 1.468x10^-15

STANDARDHIGH-Vt

0.380 µW 0.005 1.9x10^-18

DUAL -Vt 0.315 µW 0.005 1.575x10^-18

MODIFIED DUAL –Vt

0.022 µW 0.005 0.11x10^-18

OR8:



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Table 4. XOR2 gate

POWER DELAY[nS]

PDP [WS]

STANDARD LOW-Vt

0.723mW 0.004 2.892x10^-15

STANDARDHIGH-Vt

0.0355µW 0.005 0.1775x10^-18

DUAL -Vt 0.035 µW 0.005 0.175x10^-18

MODIFIED DUAL –Vt

0.035µW 0.005 0.175x10^-18

XOR2:

Table. 5. An 8:1 Multiplexer

POWER DELAY[nS]

PDP [WS]

STANDARD LOW-Vt

0.446mW 0.054 24.08x10^-15

STANDARDHIGH-Vt

0.439 mW 0.035 15.53x10^-15

DUAL -Vt 0.257mW 0.009 2.313x10^-15

MODIFIED DUAL –Vt

0.876 mW 0.004 3.504x10^-15

V. CONCLUSION

In this work, the benchmark circuits or2, and2 xor2, or8 and 8:1 multiplexer are successfully implemented using CMOS domino logic. Considering the power-delay product [PDP] as the figure of merit, each of the circuits for standard low-Vt, standard high-Vt, standard dual-Vt and modified dual-Vt technologies is compared. It is observed that the proposed modified dual-Vt technology produces the minimal power-delay product [PDP] among the four techniques. Hence with the use of low-Vt transistors in critical timing paths and high-Vt transistors in noncritical timing paths, the performance characteristics of the domino logic circuit can be significantly improved. Therefore the proposed modified dual-Vt technology is a better solution for the

optimization of sub-threshold leakage and minimizing the overall power consumption of the domino circuit.

ACKNOWLEDGMENT

The authors wish to thank RGMCET, Nandyal, A.P, India for providing the Microwind3 and DSCH tools.

REFERENCES

[1] S. Borkar, “Obeying moore’s law beyond 0.18 micron,” in Proc. IEEE Int. ASIC/SOC Conf., Sept. 2000, pp. 26–31. [2] R. Ronen et al., “Coming challenges in microarchitecture and architecture,”Proc. IEEE, vol. 89, pp. 325–339, Mar. 2001. [3] M. T. Bohr, “Nanotechnology goals and challenges for electronic applications,”IEEE Trans. Nanotechnol., vol. 1, pp. 56–62, Mar. 2002. [4] D. J. Frank et al., “Device scaling limits of Si MOSFET’s and their application dependencies,” Proc. IEEE, vol. 89, pp. 259–288, Mar. 2001. [5] R. K. Krishnamurty, A. Alvandpour, V. De, and S. Borkar, “High-performance and low-power challenges for sub-70 nm microprocessor circuits,”in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp.125–128. [6] S. Mutoh et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol.30, pp. 847–854, Aug. 1995. [7] V. Kursun and E. G. Friedman, “Domino logic with dynamic body biasedkeeper,” in Proc. Eur. Solid- State Circuits Conf., Sept. 2002, pp.675–678. [8] “Variable threshold voltage keeper for contention reduction in dynamic circuits,” in Proc. IEEE Int. ASIC/SOC Conf., Sept. 2002, pp.314–318. [9] S. Borkar, .Low Power Design Challenges for the Decade,. Proceedings of the IEEE/ACM Design Automation Conference, pp. 293-296, June 2001. [10] P. Srivastava, A. Pua, and L. Welch, .Issues in the Design of Domino Logic Circuits,. Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 108-112, February 1998. [11] G. Balamurugan and N. R. Shanbhag, .Energy- efficient Dynamic Circuit Design in the Presence of Crosstalk Noise,. Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 24-29, August 1999.


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Domino Ckts Using Dual Vt