Designing PCB’s in the Electronics ShopC. MurphyFebruary, 1997

IntroductionThe purpose of this document is to provide an introduction to the PCB design process in the Physics Department electronics shop. This is a fairly complicated procedure, so this document should be used as a supplement to the regular Mentor documentation available and to the assistance of the staff engineers.

The process of designing a printed circuit board begins with schematic entry, and ends with computer generated artwork files that are sent to a company to have the board manufactured. The electronics shop utilizes a set of software packages from Mentor Graphics that cover the entire process. What a printed circuit board is and how it is made is beyond the scope of this document. It is assumed that you are familiar with certain terminology related to circuit board design. If you need more information on PCB basics or terminology, please do not hesitate to ask one of the engineers.

The first step in designing a PCB is creating a set of schematics. The shop has the Mentor Graphics tutorial for Design Architect, which will step you through the process of entering schematics1. Before using Design Architect however, you will need to add a few lines to your .cshrc file in your home directory. The necessary lines are included in an appendix to this document.

One other note; when you make your schematics - style IS important. The designs created in the electronics shop will be existent for many years. Because they go off to experiments at other locations and are often maintained by graduate students, the schematics need to be readable. If you do not have experience with other electronics shop schematics, take a look at schematics that have been done here and make yours similar. Do not try to cram too much onto a sheet, and have the logic flow from left to right across the sheets. Also, use signal names that convey some meaning when naming signals. Only uses buses for address and data lines, do not bus control signals or power nets or any other type of net.

When creating a sheet for an electronics shop design, the first few steps should always be the same. In the schematic window of Design Architect, type physics(). This will create a new menu heading on the top menu bar named Physics and also put a sub-menu heading in the Libraries menu that links to the Physics parts libraries. Select Physics>bsize and a page outline will appear 1 One thing it neglects is a very handy way of entering commands in the Mentor programs called “strokes.” Using the middle mouse button in any Mentor program, draw a question mark (without the bottom period) and information on stroke commands will appear.

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that will make your schematic print correctly on our 11x17 printer. Next, go to the Libraries>Physics Libraries menu item. In the menu palette, select the Gen_Lib and find a part called ledger. This should be placed in the bottom right corner of your sheet and the design information changed for your design. These initial steps and the Mentor tutorial should get you started. Do not forget to keep your schematics clean and readable. Text should not overlap anything else.

There are four other programs involved in creating a finished PCB design. Here is a short introduction to each of them.

1. Librarian- In Librarian, you collect and edit the files that describe the physical shapes of the various circuit elements as they will appear on the board. These shapes are referred to as geometries. The geometry files can be found in $PHYS/parts/pcb_geoms/...

2. Package- In Package, you map the logic symbols used in Design Architect to the physical parts collected in Librarian, and determine how many of each part you will need.

3. Layout- In Layout, you place the parts on the circuit board and route the traces between pins. You also check to make sure that the power and signal nets will be connected properly.

4. Fablink- In Fablink, you create the information that the manufacturing company will need to produce your circuit board. This includes a drill file, aperture table, artworks, and possibly a fabrication drawing.

After you have finished a circuit schematic in Design Architect you need to input the physical characteristics of all of the various components that you will be using. Librarian is the tool that you will use to tell the computer the physical shape and size of all components.

LibrarianIn Librarian, you collect the appropriate geometries together to be used later in Package and Layout. These geometries tell the computer the various physical characteristics of the component, such as length and width. As far as we are concerned, most parts are made up of two elements; pins or pads, and a general shape and size. Parts also come in two types, through hole and surface mount. Information about a part in Librarian is organized on different layers (much as in Autocad). Some layers have physical significance on the final circuit board, while others represent logical functions only (i.e., placement keepout).

For all components, the through hole and surface mount pads have separate geometries that describe the actual connection points of the chip to the board. These are called padstacks. The

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padstack contains the drill hole size (if a through hole), the pad size, and other information. So to have a complete geometry, you need to have both the padstack geometry and the actual part geometry. You can assign a default padstack for the board and also a default padstack for individual components.

For some components you will have to make new geometries, such as custom components made by the shop, or other very specialized components. But for the most part, the geometries that you will be loading into Librarian are standard and will be used for many different logical components. For example, you may have both a shift register and a counter that each come in dip20 packages, but you only need to read in the dip20 geometry once. The e-shop geometries are found in the directories $PHYS/parts/pcb_geoms/geoms, pads, smd_pads, smd_geoms, and boards. There are also mentor provided geometries, but these should be checked before use and the surface mount parts should not be used. These are in /nfs/voyager/l2/mentor_parts/pcb_parts/pcb_geoms/padstacks, std_geom, smd_geom, and smd_padstacks. If you need to create a surface mount geometry, we have a manual that specifies the standard pad sizes and component sizes that must be used. This is the IPC Land Pattern Manual.

To explain the Librarian process in greater detail, we will go through an example. Consider an imaginary circuit. The outputs from a 10474, which is a RAM, go to a Bt501. This chip converts the ECL signals to TTL. The TTL outputs are connected to two OR gates (74hct32). The first thing to do is to make a list of the symbols in the schematic.

In this case we have:1 Bt5011 104742 74hct32

After you have this information, use the data books to find out what packages each component comes in. Sometimes you have a choice for particular component, so determine which package you will use. If a part is not used by the shop very often, it is to your benefit to call and get price and availability on the chosen package. A package can be in the data book but be obsolete or take months to arrive. In our example:

The Bt501 comes in a dip24The10474 comes in a plcc28The 74hct32 comes in a dip16, with 4 logic gates in one package

Now you are ready to open Librarian. Double click on the Librarian icon in Design Manager. You will be asked if you wish to open Librarian on a design or stand-alone. Open it on your

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design and use the Navigator window highlight the name of your design (i.e. the top level of your design directory) and click OK. This allows Librarian to create files to contain your design geoms, design maps, and other information that will be needed later on in your design directory. After choosing your design, you will be asked to choose a technology. Choose standard pcb at the prompt.

Now you are in Librarian. All that you need to do in this program is collect the necessary geometries for your design into one place. To do this, open the menu File->Restore->ASCII Geometries. Then navigate to the geometry you need. The geometries created by the e-shop should be used as we have taken pains to check them for correctness. For our example, we are going to need a dip14 geom for the OR gates. So we Restore ASCII Geometries, and navigate to $PHYS/parts/pcb_geoms/geoms/dip14 and click OK. We then see a picture of the top view of a dip14.

This is more or less what you will see, with numbers in each of the circles from 1-14, with the square pad being number 1. These circles (and square) are the pads. If you have just restored the dip14 geom in Librarian, you will notice that the pads are pink. That is because the pad geometry that this part references has not been restored yet.

To load in the pads, you must first determine which pad to load. Pad60_42 is the pad most commonly used, especially in dip packages. The next thing you must do is change the default padstack characteristic of the geometry to the pad that you have decided to use. To do this, you must make sure that the geometry that you wish to assign the pad to is open (i.e. in the view window). Then click on the right mouse button to bring up the pop-up menu. Click on Attributes>Change Padstack Override>Modify Padstack Override. If the chip already has a default padstack assigned to it, you can change it here. If it does not, then bring up the pop-up menu and choose Change This Geometry>Change This Geometry... You will see a dialog box

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pop up, and an empty box labeled Default Padstack, which you can fill with the pad of your choice. You should not change the pad referenced by any surface mount geometries. These pads have precise measurements for creating the best solder joints with the least amount of shorts, etc.

After you have assigned the pad to the package you must load the pad geometry into Librarian. This is an identical process to loading any other geometry, but the pads are stored in a different directory. The e-shop pads are stored in $PHYS/parts/pcb_geoms/pads and smd_pads. When you have loaded in the pad that is now assigned as the default for your component, you will see it on the screen. If you look at the dip14 geom again, you will see that the circles have gone from pink to looking like the pad geom that you loaded. On dip geometries, you usually have to load two pads, the standard pad and the square pad. The square pad is important because it denotes pin 1- which tells what orientation the package should have when placed on the circuit board. The square pads for a certain size pad are easy to spot, if you use pad60 then the appropriate pad for pin 1 is pad60_sq. If your through hole geometry does not have a square pad for pin 1, it is a good idea to create a padstack override for pin 1 and make it square. The surface mount geometries have all of the same pads, but there should be markings on the silkscreen layer that show the proper orientation of the chip.

You may find that you need to create your own geometry. For this, you should look at the manual that Mentor provides. However, here are a couple of hints. Usually you do not need to start completely from scratch. For instance, if you need a dip40, and one does not exist, you could simply take the dip24 geometry, extend the body and add 16 pins, moving and renumbering appropriately. Under the Geometries menu there is a Rename option. This will allow you to change the name from dip24 to dip40, so that you can have a real dip24 in your collection of geoms along with your modified dip24. Note though, that if in this case I did need a dip24 along with my dip40, I would need to load in the dip24 again after modifying the first to be a dip40. Another crucial item when creating a geometry from scratch is that every geometry MUST have an attribute called a component placement outline. To add this pop up the edit window attribute menu and select Add Component Placement Outline- you will then be prompted to draw a polygon where you want the placement outline. This polygon will be added on the place layer. You should make sure that the outline is as large or larger than the actual physical component since this outline defines the bounds of the part for placement on the board. Do not make it too large however, because you cannot overlap this outline when you are placing parts on the board in Layout.

To change the layers that are visible, use the F7 key. To set the edit layer, use the F6 key. Also- if you are having problems editing a geometry, use the Setup>Grid menu item to set the grid smaller so that you can position things more easily.

There are a few geometries that you will always need. One is a via geometry. This part (actually a small through hole) allows the board router to switch between signal layers. The standard part

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is called via40 and is located in $PHYS/parts/pcb_geoms/pads. Another crucial geometry isthat of your circuit board itself. You need to describe to Librarian the dimensions of the physical outline of the circuit board that you will need. If you are designing a board that fits a certain form factor (such as VME, Fastbus, or CAMAC), you can read in a board from $PHYS/parts/pcb_geoms/boards. You should NOT make new geometries for these boards. The ones in the library have been manufactured successfully and are known to be correct.

You can also modify an existing geometry if you are making a free-standing board with fewer size restrictions. Many of these board geometries exist in the design_geom directory of other projects instead of in the pcb_geoms directory. You can estimate the size you will need; if you need more space you can always come back and expand the board later.

There are many attributes associated with a board geometry that need to be set up in librarian. Most of them can be changed by executing Change This Geometry in the pop-up window while the board geometry is active. This will bring up the form on the following page.

You will have to find out what values you need for your board. The order of the power net names is important, because that is the order they are assigned to the physical power layers. This will be discussed further in the next paragraph. Also, if you need to do a split power plane you enter each of the powers separately.

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With the board geometry open, there is another thing to set up. From the menu bar at the top of the screen, select Setup>Physical Layers. In this pop-up window, you define the actual copper layer makeup of the board. On the next page is the physical layer setup for a board with three routing and three power layers. The important things here are that the outer layers on the top and bottom of the board are the routing layers, and the inner layers are the power layers. Also notice that the topmost and bottom most layers are specified as the signal layer and a pad layer. This is so that solder pads are placed on the surfaces of the board.

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There is one final geometry to create in Librarian. This is called the Artwork stack up. In the main window menu select Geometries>Create Geometry>Artwork Order. This will give you a blank librarian window. The artwork order part does not have any graphical components to it. It simply has attributes. To add these attributes, click on the Edit Order button. These attributes define what layers will show up on each artwork. I will list an example artwork order for a six layer board:

Artwork_1 board_outline,drawing_1,signal_1,pad_1Artwork_2 board_outline,drawing_1,signal_2Artwork_3 board_outline,drawing_1,power_1Artwork_4 board_outline,drawing_1,power_2Artwork_5 board_outline,drawing_1,power_3Artwork_6 board_outline,drawing_1,signal_3,pad_2Artwork_7 board_outline,drawing_1,solder_mask_1Artwork_8 board_outline,drawing_1,silkscreen_1Artwork_9 board_outline,drawing_1,drill,drill_holesNotice that each artwork has the board_outline and drawing_1 layers included. Also notice that the artworks are arranged in the layer order that the board will have. When you edit the artwork layers that will be power layers, be sure to select the “Flash Via Thermal Relief on Power Plane Vias only” option. If you have any surface mount, you will also have to have another artwork with the solder_mask_2 layer. Also, you may want to have silkscreen on the back of the board so you would add an artwork with the silkscreen_2 layer. If you have any split power planes, you would have an artwork with two power layers defined. This is the only way the software knows that your board has a split power plane. If you do have a split power plane, then the physical

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layers and power net names (from the board geometry) should be set up as if each power has its own plane.

While in Librarian, you will probably want to make a package configuration file. You may have to complete the next section- Preparing to Package- before you can crate this file. When you gather or create your mapping files, some of them may have different names for the same power net. The purpose of the package configuration (or pkg config file) is to tell the software all of the different names that you may call the a power net and associate them with the correct global net. To create this file, under Setup Design Rules, select Pkgconf.. This pops up a dialog box with many options. The Alias Power Statement at the bottom is the option you want to use. Leave all other values the defaults.

You first enter the local name, and second the associated global net. You want to make sure that the names you use for the global power nets are the same names that you used in your board geometry’s “Power Net Names.” That way the software knows which nets to connect to the board’s internal power planes. You will have to go through your mapping files and the power symbols on the schematics and write down all of the various names you have used for a power connection, and alias those to the name you will be using on the board. Below is an example of the output file for a design that uses four different names for ground, VCC1, VCC2, GND, and GROUND.

ALIAS_POWER VCC1 GROUND ALIAS_POWER VCC2 GROUND ALIAS_POWER GND GROUND Once you have done all of that, you are (ostensibly) finished with Librarian. You will probably have to come back at later points in the process to correct mistakes or tweak geoms or whatever, but now it’s time to move onto the next step. Since you have all of the symbols for your design (from your schematic) and a complete set of the geometries they map into, you are ready to start the packaging process.

Preparing to PackageThis is done by assembling mapping files and creating a catalog file. The mapping file tells the software how many logical symbols go into one of the geometries, and how the pins on the logic symbol map to pins on the chip. Here is an example of a mapping file for our OR gates, the 74hct32:

symbol 1 1pin out 3 0pin i1 2 1pin i0 1 1

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symbol 2 1pin out 6 0pin i1 5 1pin i0 4 1

symbol 3 1pin out 8 0pin i1 10 1pin i0 9 1

symbol 4 1pin out 11 0pin i1 13 1pin i0 12 1

power vcc 14power ground 7

From this you can tell that 4 symbols map to one chip. In symbol 1, the output of the gate is pin3, and the two inputs are 2 and 1. Notice that there is a final number on each line. That number is either a 1 or a 0. That number tells whether or not the item on that line is exchangeable with another item of the same type. Thus, the first line reads: symbol 1 1. This means that symbol 1 is interchangeable with other symbols that have a 1 after them in the mapping file. A 0 means that the object is not exchangeable at all.

In the case of the pins, under symbol 1, notice that the lines read:pin i1 2 1pin i0 1 1

This means that pins i1 and i0 are interchangeable. The “i” pins under symbol 2 are also interchangeable. In the case of pins, Mentor will keep all exchanges within the same symbol. So for the OR gate example, it does not matter which input pin is which- they are logically equal. Since the symbols in this example have swapping codes of “l” that means that any 74hct32 OR gate is logically the same as any other. Once the board is placed, these swapping codes will allow the software to “swap” symbols and pins to improve routing without altering logic functionality. Some mapping files will have quotations around the pin names, may be in capitals or lower case, and may have the symbol name in quotations after the symbol line. Mentor will read mapping files with or without these items.

For most components, the mapping file already exists. They can be found in either the appropriate directory in $PHYS/parts/pcb_maps, or /nfs/voyager/l2/mentor_parts/pcb_parts/pcb_maps. If you need to make a mapping file, navigate

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to the design_maps directory that librarian has created in your design directory. Then just create a text file that has the proper pin names, etc. You can also copy a similar mapping file and then edit it. The first thing to put in the mapping file is the number of logical symbols that go into one chip. In many cases, it will be just one symbol per chip. Sometimes, as in the case of logic gates (AND’s, NAND’s, etc.), you will have several symbols per chip. In either case, you will at least have 1 symbol. So type symbol 1. Decide whether or not it is exchangeable with the other symbols in the chip, and put the appropriate 1 or 0 (0 is the default). On the next line, indent a space, type pin (pin name) (pin number) (swap number), where pin name matches exactly the PIN property on the symbol in Design Architect, pin number is the number of the pin on the geometry that you wish to map to, and the swap number is, again, 1 or 0. Put a space between each of these elements of the line. That was a little thick, so I will try to illustrate it a little better with the OR gate example that I have been using:

The OR gate’s symbol in Design Architect:

Thus, the mapping file:

symbol 1 1pin out 3 0pin i1 2 1pin i0 1 1

maps in this way:

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or this way:

Because, remember, pins 1 and 2 have a swap value of 1, and thus are eligible to be switched.So, finally, after you have input the symbols and their pins, you add the power pins to the mapping file. This is fairly simple. If our chip has pin 7 attached to TTL high and pin 14 attached to ground, then you would type:

power vcc 7power ground 14

Caution must be taken with power net names. If you use vcc when you mean 5V in one place and when you mean ground somewhere else, you are in big trouble.

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After you have typed in the last line of your mapping file, be sure and hit the Return key. This is necessary for the program to read your mapping file correctly. Note that you specify the pins in a POWER statement rather than a PIN statement if the pins are always connected to that particular power level. For instance, you may have connected the input of an OR gate to ground in Design Architect, but this is different from actually mapping that pin to a power plane.

One note of warning about mapping files: some parts can map to different geometries and for each geometry they map to, they may have different pin numbers. You must pay close attention to integration of the symbol, geometry and map file. If you have a mismatch somewhere along the line, the Package program will usually give you warnings which are tip-offs, but it helps to pay attention as you go through the design process.

As you find (or create) mapping files for all of your symbols, place them all in your design_maps directory under your design name. That way, when you go through Package, you can find all of the files for your design in one directory and if there are problems, you will have a much easier time finding out where they are coming from.

When a mapping file exists for each of the components in your schematic, you must worry about one more file. That is your catalog file. The catalog file is a complete list of the symbols you need for the circuit, the names of the geometries they are mapped to, their mapping file names, and the numbers of each symbol that fit in one chip. There should be a catalog file, called design.catalog or maps.catalog in any other project’s design_maps directory. If you open one of these, you will see the format that a catalog file should take. Note that the Part_No column is filled with entries that are just PN-(comp_property). In the past, we have not used this entry correctly. It should be the specific manufacturer’s part number for that symbol. The other columns are filled with the appropriate entries, corresponding to the symbol’s component property, the name of the geometry, the name of the mapping file, and the number of symbols that can be mapped to one chip. The easiest way to get this file correct is to copy one and edit it for your design. A word of warning, do not use any tabs when typing this file. Mentor will only accept spaces in between the text entries.

When you have a catalog file that contains this information for all of the symbols you used in Design Architect, and in the proper format, you are ready for Package.

PackageLoading Package is similar to loading Librarian; you must open it on your design and it may ask you what board technology you want to use (choose Standard PCB). Also, choose the Default Viewpoint when it asks. When Package has loaded, you will see a menu of icons on the right side of the window. The startup for Package loads in by default all of the Mentor catalogs. You should choose Load/Forget Catalog Library from the palette and forget all catalogs. Then choose it again, and read in the catalog file from your design area. If you have your catalog file

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in your design_maps directory and have named it design.catalog, you only need to click the button by design and Package will find it automatically.

Next, click the Check Build icon in the right hand menu. You will get a transcript window with warnings. This is the most important part of the design process for paying attention to warnings and errors. I cannot predict every kind of error you may run across, but I will try to clue you into some of the common ones. If a map file is not found, go into your catalog file and make sure that the name of the map file corresponds to the actual file name. If you get unconnected pins, verify that these are either listed as NC in the data book or that you actually are not using the pin and it does not need to be tied high or low. Finally, if you get pin name in map not found in file or vice versa, then make sure that the PIN property on the symbol is identical to what you refer to in your mapping file. There are probably errors that you will encounter that I haven’t listed here, but usually the software is specific enough in stating the problem that you can scrutinize the problem area and find out what you need to fix.

You will need to either quit and re-load package, or use the “forget catalog” option and re-load the catalog to be sure Package is looking at the fixed version. Then Check Build again, and press Build. On the dialog box that comes up, use the default settings. Once again, you will get a transcript window with errors and warnings for you to address. If, after building you find warnings that are a problem, close Package, but don’t save the changes. When these problems have been taken care of and the build does not have any errors, you will want to write out a bill of materials for the purpose of ordering parts for the board. This can be found in the top menu bar item Report>Bill of Materials. You get a pop-up window that prompts you for a path name (use the default) and directly below this are buttons for Part Number, Reference, and both. This is how the parts will be listed- you need to select Part Number. Leave the rest of the selections to the defaults and press OK. Then you can save and quit Package. This leaves you with one last transcript window to check for problems. The transcript shell associated with your Package session will have a set of warnings and notes between its record of your order to close and the point where Package actually does close. Check this last transcript for any new errors or warnings. Any 1 pin nets should be named the default. If they are not, they usually are typos in net names. Go back to DA and try to find them and either correct them or erase them. It may be necessary for you to go through the build process again.

LayoutWhen you have finally waded through all of this, you are ready for Layout (this is the fun part). In Layout, you will place the components on the board, then the computer will route the electrical connections. Open Layout on the design, and leave the Trace Analysis Menus off. When Layout has finished loading and you close the transcript window, you will see the outline of your circuit board. Bring up the place menu on the palette by clicking on the Place button in the upper right hand corner. Then click on Map, and in the pop-up window choose top only, specify area, and all components. After you click OK, make a box next to the board that is large

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enough to hold all of the components. You will now have all of the components that need to be placed arranged next to the board. You may have to play with the items under the Display Controls button and also with the view layers to get your view of the board uncluttered. I would recommend clicking on the Display Controls button and turning off the guides, then going to the menu bar item Setup Placement>Interactive Placement>View Connections.. and in the pop-up menu, selecting Nets. This will show the guides (which are lines representing the connections between pins) only when a component is selected. The strokes for layout are quite similar to those used in Design Architect. Draw a question mark with the middle mouse button depressed to see a list of them. To move a component onto the circuit board, select it, use the move stroke (the left half of an “M”) and you can drag the component to the place on the board where you would like it.

While moving the chip, the guides will show the nearest components that the highlighted piece is connected to, to assist in placement. Note that the guides will not show all of the components directly electrically connected to the pins, just the nearest ones on your logical schematic. To see everything that is directly connected to a certain pin, choose the Highlight Net option on the palette. Then click on the pin you want. You will see every pin connected to the selected one. Click on one of the selected pins again to turn the highlight off. You can also turn all of the guides back on by going back to Display Controls. These options should help you place the components logically.

Some useful guides for placement: · Place the I/O connectors first and then use them as a starting point by placing next the chips

that have nets from the connectors, then the chips that have nets to those chips, etc., etc. · The main guide to placement should be making all connections as short as possible within

reason. · Use the schematics to help visualize the data flow on your board. They are the best guide to

placing components. · If your board is not excessively full or complicated, put pin 1 on all chips facing in the same

direction. This makes assembly and testing much easier. · Stick to a placement grid so that pins line up. This will make routing easier as pins block

routing and/or via areas, so if they are aligned on a grid, there are vertical and horizontal paths across the board.

· If you are putting surface mount components on the back of the board, put them so the pads overlap pads on the front of the board- this minimizes the via areas that are blocked.

· If you have any high speed signals, the components connected to them should always be placed to minimize the net length.

· Put the decoupling capacitors near the components that use the power to which they are connected. Usually you will have a capacitor for every two chips that use a certain power net.

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· If you have the space, spread out the components. Make the layout look neat and well balanced.

When you have finished placement, you can use the automatic swap feature in Layout to shorten your net lengths. (Remember the swap code in the mapping file?) First it is usually a good idea to select and protect components that you do not want swapped (like connectors), just in case someone made an error in a mapping file. Swapping is something you do not always need to do, but is especially helpful for ECL boards where each net has an identical pull down resistor. Go to the Auto Place palette and click on Auto Swap. In the pop-up, if you have protected connectors and critical components then select all items (otherwise, you may want to do only selected components), components - don’t swap, swap gates, and let it take10 or so passes. You will see in the session transcript window the total net length reduction. This is usually impressive. You may want to repeat this procedure a few times until the net length reduction is close to 0. Also, once you have done this, you may actually want to move things like sip resistors, that now have guides to different locations and iterate the process.

The last thing to do before routing the board is to check that the power nets have been processed correctly. You should use the Route icon button Highlight Net and then type in the name of the power nets for your board. It is a good idea to try all of the various names and spellings for each power, to make sure that everything aliases correctly. For example, if you type in GND and GROUND and get two separate nets highlighted, your aliasing did not work. If a net is supposed to be connected to an inner power plane, than any through holes connecting to the power should just show the pin highlighted rather then a guide connection. Any surface mount pads connected to the net should show a guide going to the nearest through hole connected to the power. If the power shows up as all guides, then the power net name in the board geometry does not match the power net name that was alaised. You may have a power net that goes to relatively few pins that you want to route on the signal layers. In this case, you usually want to route it with a thick trace, say about 0.05” and then it should not be listed in the power net names for the board geometry. . It is also a good idea to hand route this net first and protect it before you route the rest of the board. You may also want to hand route any high-speed clock traces and then protect them.

Now you should be ready to route your board. To set up the auto router, change the palette menu to Auto Route, and click on Setup Routing Rules. You will see the following pop-up menu.

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This is the standard setup for the routing rules. You can use a smaller trace and via grid but the router will then run slower and use more memory. The next menu setup is the Layer Rules button. The menu on the following page then pops-up.

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Any physical layers that are signal layers should have routing enabled. Also, in general the board routes better if you have a specified direction on each layer. If you have a large number of layers, it may pay off to have one or more diagonal layers, otherwise vertical and horizontal are fine. If there are an odd number of layers, look at your board with all of the guides showing and see if there are more nets going in one direction than another and put the extra layer in that direction. Having every other layer vertical and horizontal switching off helps to cancel crosstalk between layers.

The final set up menu is the Net Rules menu. You will get a pop-up window that asks if you want to set up net rules for a specific net or for the DEFAULT_NET_TYPE. Usually you want to do the default net type (which encompasses all nets). Click change and the second pop-up on the next page will appear.

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This sets up the width of the traces and also all of the clearances. Usually these are the same value; for example, if you have 0.008” traces, the standard is to have 0.008” clearances. The via40 pad should be listed as the via and it should show all signal layers as enabled for routing.

Finally, click on Auto Route. In the upper left corner of the resulting menu, you can choose several different types of passes. If you have surface mount on your board, choose Breakout for your first pass, and then below it choose Automatic. 10 passes for the Automatic selection is usually a good start if your board isn’t too large or dense. Lastly, click on the Save Every Pass option (the router can crash fairly often on large jobs). Click on OK and wait for the board to finish routing. The transcript window will show the statistics for each pass that the router makes. If there are any unroutes when the router finishes, you can start the autorouter up again, but first see if you can find out why the routes did not route. It may be that the density is too high for the number of routing layers you have assigned, or there may be an off grid problem or a routing keepout area. If there are only a few traces left, you may want to try routing them by hand. There is a Mentor document solely on the use of the auto-router. For additional information, open bold_browser and take a look at this. There is also an excellent router made by another company that can be used in conjunction with Layout. Information on this is available from the staff engineers.

Once all of the components are placed and the board is routed, you will want to set the display to

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show only the pads and the silkscreen layer. At this point, you will need to change all of the references on your board. References should be assigned on a grid system, with the chip in the upper left hand corner of the board as chip A1, and all chips in the first row should continue- A2, A3,..., with the second row starting B1, etc. Any passive components should have references changed to match the nearest chip. If you have a resistor next to chip F5, the reference should be RF5. This is so that when you are debugging the board and need to find a part from the schematic, with this reference system you will be able to find it immediately on the actual board. Of course, in order to work, you have to ensure that the reference changes are back-annotated to the schematics.

The silkscreen and references need to be neat and readable. Usually you will want to set all references for the same type of part (e.g., all integrated circuits) to the same size. Connectors and IC’s should have the largest references, and resistors and capacitors should be smaller. All references should be below the components to which they belong.

The last thing you may need to do before going to Fablink is to take care of any split power planes if your board has them. Fablink will automatically create full power planes for planes that are not split, but you will need to draw a power fill for one of the powers on the split plane. If you have a split plane, hopefully during placement you were careful to place all of the pins connected to one of the powers together. You will probably want to highlight the power net that you do not want the fill to touch. Then in the Area Fill palette menu, click on Setup Fill. Leave the check on, select snap to display grid and set the display grid to 0.02”. The Polygon/text/trace style can be whatever you want. Then click on Add Pwr Fill. On the little menu bar at the bottom of the screen, click the Options button. Change the Manufacturing Aperture Size to 0.02”. Then fill out in the menu bar the power layer and the power net name for the fill you are making. Click OK and draw the polygon around the fill area. Check the power fill using the main menu to make sure you connected to all pins for that power net. You are now ready for Fablink.

FablinkFinally, you have reached the last step in the long arduous process. When you open Fablink on your design, it should come up with your board geometry in view. You will need to create a manufacturing panel for your design. Select Geometries>Create Geometries>Manufacturing Panel.. In the pop up window, you will want to select Step and Repeat and Inches for the units. You can either include an outline or not. The manufacturing panel is used as a template for the artwork creation and artwork comes in standard sizes- so if you use an outline, you will want to make sure it is a standard size and will fit your board with room to spare. Some of the standard sizes are 8 x 10, 10 x 12, 12 x 18, and 16 x 20 (you can reverse the dimensions).

You will need to add various geometries to your panel. First, read in and add a sheet geometry to your panel. These come in various sizes for the various size artworks. The sheet geometries can

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be found in $PHYS/parts/pcb_geoms/geoms. You will need to edit the sheet before adding it to your panel to be sure the appropriate labels are in the lower right hand corner (and are on the correct layer) for your artwork stack up. The next thing to add to the panel is the board geometry- click the Add Board palette button. You need to add target geometries to the panel. The manufacturing company uses these for alignment purposes between the artworks. Read in $PHYS/parts/pcb_geoms/geoms/target and add two to the panel. One should be by the top right corner of the board and one by the bottom left. Exact placement is not important. The next figure shows a simplified panel with a board and two targets.

Once the panel is complete, the next step is to generate the drill data. This consists of filling the drill table, reading in the hole symbols, changing the drill table, and creating the drill data. First, fill the drill table by selecting Drill>Change Drill Table>Fill Drill Table from the pop-up edit menu. Next you will want to read in hole symbols. When you create artwork, each different drill hole size is represented by a different symbol. You have to read these geometries in from

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$PHYS/parts/pcb_geoms/geoms. They are named holesymb1, holesymb2, etc. You will need to read in as many of these geometries as you have different size drill holes using File>Restore> ASCII Geometries. Now you will change the drill table by selecting Drill>Change Drill Table> Change Drill Table. The following pop-up form will appear.

Select the drill position 1 and click on Change. The drill information form on the next page will appear.

Leave Drill Hole Type as plated. For Upper Bound enter the drill size plus the tolerance for that drill size. For the Lower Bound, enter the drill size minus the tolerance (this should be same tolerance). Usually the tolerance is ten percent of the drill size. Then, for the symbol field, enter holesymb1 for the first position, then 2, etc.

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The next figure shows the Change Drill Table pop-up after all the drill positions have been edited. Click on the Close button.

Next create the drill data by selecting Drill>Create Drill Data from the edit menu. The Create Drill Data pop-up form will appear. In the form select Generate For: Step & Repeat Panel.

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Leave all other options unchanged. Click OK. The drill data will be created and placed in a file named Drill in your design/pcb/mfg directory.

Now you create the drill schedule. Before you do this, it is a good idea to make sure the line width is set to something other than 0. (Select Setup>Line Width>Line Width and set it to be .010). Now select Drill from the palette menu and then click on Create Drill Sch. The Create Drill Schedule form will pop-up. Set Create Drill For: Panel. You can change the title for Board Drill Schedule to your board name, but leave everything else unchanged. Click on OK. You should see the drill schedule appear.

The drill schedule needs to be sent with the artwork for fabrication of the board. You can print out the drill schedule and fax it to the manufacturer, or if there is room you can add it to the manufacturing panel. To add it to the man panel, bring up the panel and select the Add Geom palette button. Enter drill_schedule_panel_master in the pop-up form. Place the schedule on the panel so that it does not overlap any of the other added geometries. Before you move on to artwork creation, you will need to view the board geometry and turn the view drill holes switch to on.

The next step is to create the artwork data. This involves filling the aperture table, setting up the artwork information, and then creating the artwork. Start by selecting Artwork from the palette menu and then clicking on the Setup Art button. The Setup Artwork pop-up form is show on the next page. Fill it out as shown.

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Click on OK. The Change Artwork Format form shown on the next page should then pop up. Change the Film Size Height and Width to the size of your panel. Fill the rest of the entries as shown.

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Next check the aperture table by clicking on the Check Aper Tbl button. Make sure there are no missing apertures. You will need to define the power apertures. Click on Report>Aperture Table and in the form that comes up, select Display. There is a column in the aperture table labeled “power”. You will need to note the aperture number for any row that has a “true” entry. For each of these apertures you need to define the power aperture. Click the Change Pwr Aperture palette button. This will pop-up a menu box. Enter the first power aperture position number and click on Specify. Enter .010 for both the Tie Width and the Air Gap Width. Repeat this process for all power apertures. Now you will need to check and write out the aperture table so that it can be sent to the board manufacturer along with the artworks. Click on Report>Aperture Table and select Display and Save, and save to the default design area.

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Before you create the artwork, be sure you have viewed the board geometry and turned the drill holes on. Otherwise your drill artwork will be blank.

Create the artworks by clicking on the Create Art Data button in the palette menu. For Output Type, select Step & Repeat Panel. Leave the rest of the options unchanged. Click on OK. All of the artwork files should be generated. The artwork data is saved in files named artwork_1 through artwork_n, where n is the number of artworks in your artwork order. These files are placed in design/pcb/mfg.

Display each artwork layer generated by clicking on Open Art Data box in the palette menu and select an artwork. Visually inspect each layer. One common problem: if your artwork has any large strange shapes that you know do not belong, this is often because of a problem with the board outline. You will need to go back to Librarian and make sure your board outline has some width to it and is drawn as a line and not a polygon. This is a bug in the software.

This completes all the artwork data creation. Save and quit Fablink and select Back Annotate.

Take a moment and breathe a sigh of relief and closure. You have just completed a PCB design from start to finish and are ready to see your design come to life. OK, time’s up. You will now need to get quotes for fabrication of your board and make sure that all necessary parts for the design are ordered. Now is also the time to start worrying whether the board will work or not when it gets here.

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