Do An Mon Hoc I

n Mn Hc I in T

GVHD: Thy Nguyn Ng Lm

B GIO DC V O TO TRNG I HC S PHM K THUT THNH PH H CH MINHKHOA IN IN T

TI:

NGHIN CU S DNG CHP VI IU KHIN AVR ATMEGA8 VO NG DNG O NHIT V IU KHIN CC THIT B IN IN TGVHD: Thy NGUYN NG LM SVTH: 1.O THANH MAI MSSV:06119058 2.NGUYN C I MSSV:06119009

20091

SVTH Do Thanh Mai+Nguyn c i

n Mn Hc I in T


Li Cm nXin chn thnh cm n tt c cc Thy C trong Trng H S Phm K Thut Thnh Ph H Ch Minh dy d cho n ngy hm nay, cc Thy C ca b mn in t Vin Thng. Xin chn thnh cm n Thy Nguyn Ng Lm ,Ging Vin Khoa in - in t ngi gi v hng dn tho lun v gip em thc hin n mn hc ny. V xin cm n tt c nhng ngi gin tip to iu kin thun li trong qu trnh n mn hc 1. D c rt gng nhng vn khng trnh khi sai st, xin c hc hi nhng li ch dn. Xin cm n rt nhiu.

Ngi thc hin 1.o Thanh Mai 2.Nguyn c i

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Mc lcChng 1 Gii thiu chung -----------------------------------------------------------------------------------3 1. t vn ----------------------------------------------------------------------------------------------3 2. Cc vn cn gii quyt ---------------------------------------------------------------------------4 Chng 2 Tm Hiu Cu Trc Cc Phn Cng --------------------------------------------------------5

I.Atmega8 ----------------------------------------------------------------------------------------51.Tng Quan --------------------------------------------------------------------------------------------5 2.Cu trc chung ca AVR ---------------------------------------------------------------------------9 3.Cu trc ngt Atmega8 -----------------------------------------------------------------------------9 4.Cu trc b nh ------------------------------------------------------------------------------------11 4.1 B nh chng trnh (B nh Flash) ------------------------------------------------11 4.2 B nh d liu SRAM -----------------------------------------------------------------13 4.3 B nh d liu EEPROM --------------------------------------------------------------21 5 .Cc cng vo ra (I/O) ----------------------------------------------------------------------------23 5.1 Cc chc nng ca Port B ------------------------------------------------------------23 5.2 Cc chc nng ca Port C -----------------------------------------------------------24 5.3 Cc chc nng ca Port D ----------------------------------------------------------24 5.4 M t thanh ghi ca port I/O --------------------------------------------------------25 6. B nh thi 8bit timer/counter 0 ------------------------------------------------------------------ 27 6.1 Hot ng --------------------------------------------------------------------------------27 6.2 n v m ------------------------------------------------------------------------------29 6.3 n v so snh ng ra ----------------------------------------------------------------29 6.4 M t cc thanh ghi ------------------------------------------------------------------30 7. B nh thi/m timer/counter 1 16-bit ---------------------------------------------------- 32 7.1 s khi v mt s c im ------------------------------------------------------32 7.2 Mt s nh ngha ---------------------------------------------------------------------32 8.SPI(Serial peripheral interface) ------------------------------------------------------------------379.TWI Two Wire Interface ----------------------------------------------------------------------40 10.B so snh tng t(Alalog Comparator) ----------------------------------------------------41 11.USART

( Universal asynchronous receiver/transmitter )--------------------------------43 11.1 c im --------------------------------------------------------------------------------43 11.2 To xung clock ------------------------------------------------------------------------44 11.3 nh dng khung truyn --------------------------------------------------------------45 11.4 Khi to USART -----------------------------------------------------------------------45 11.5 Truyn thng d liu-b truyn USART --------------------------------------------45

12.H thng xung Clock-----------------------------------------------------------------------------46

12.1 B dao ng Thch Anh --------------------------------------------------------------47 12.2. B dao ng Thch Anh Tn s thp-----------------------------------------------48 12.3 B dao ng R-C bn ngoi ------------------------------------------------------------49 12.4 B dao ng ni R-C tinh chnh c ------------------------------------------------503


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm 12.5 B to xung Clock bn ngoi ----------------------------------------------------------51 12.6 B dao ng nh thi -----------------------------------------------------------------51 13.B Bin i A/D( Analog/Digital) ------------------------------------------------------------53

II. Cu trc cng ni tip

--------------------------------------------------------------------57

1.Khi Qut -------------------------------------------------------------------------------------------57 2. Truy xut trc tip thng qua cng -------------------------------------------------------------62 III .LM35(Cm bin nhit ) ----------------------------------------------------------------------------65 Chng III: Thit K Phn Cng ----------------------------------------------------------------661.Mch Ngun Cung Cp Cho H Thng ------------------------------------------------------------------ 66

Chng I:

Gii Thiu Ti1- T VN Ngy nay cng s pht trin khng ngng ca khoa hc k thut, th k thut s em li cho con ngi nhng thnh tu to ln, gip cho con ngi d dng t c mc ch ca mnh trong mi thit k. Ho nhp cng xu hng , vi iu khin khng nh c v th vng chc ca mnh trong mi ng dng. in hnh trong cng ngh o lng v iu khin bng my tnh c bit l vic o nhit v iu khin cc h thng. vn t ng n nh nhit l yu t quan trng hng u nng cao cht lng cuc sng , sn xut. V vy, vic ng dng vi iu khin trong t ng iu khin nhit v hin th kt qu trn my tnh c nghin cu v ng dng. Vi iu khin Atmega8 AVR c cng sut cao, tiu th nng lng thp, cu trc RISC tin vi 130 lnh vi chu k thc hin n xung ln nht, 32 thanh ghi a mc ch 8 bt, 16 MIPS ti tn s t 16 MHz, b nhn 2 chu k On-chip, Power-on Reset v Brown-out Detection c th lp trnh, b dao ng RC bn trong c th lp trnh cc mc, 5 Mode ng (Idle, ADC Noise Reduction, Power-save, Power-down v Standby), c kh nng Reset khi bt ngun, kh nng d li Brown out lp trnh c, c ngun ngt trong v ngt ngoi. Ct li ca AVR l s kt hp cc cu lnh phong ph vi 32 thanh ghi a mc ch. Tt c 32 thanh ghi u trc tip kt ni ti b x l logc s hc - Arithmetic Logic Unit (ALU), cho php truy nhp 2 thanh ghi c lp trong mt cu lnh n c thc hin trong mt chu k xung. Kt qu ca cu trc tr nn gn nh, hiu qu hn, trong khi vn t c thi gian x l nhanh hn gp 10 ln cc vi iu khin CISC thng thng khc. 8K byte Flash trn chp c th lp trnh vi cc kh nng c trong khi ghi (Read-While-Write), 512 byte EEPROM, 1K byte SRAM, 23 ng vo ra a mc ch, 32 thanh ghi a mc ch, 3 Timer/Counter rt linh hot vi cc compare mode, cc ngt trong v ngt ngoi, mt b USART ni tip c th lp trnh c, ghp ni ni tip 2 dy nh hng byte, 6 knh ADC (8 knh vi loi TQFP v MLF packages) trong 4 (hoc 6) knh c chnh xc 10-bit v 2 knh c chnh xc 8-bit, Watchdog Timer c th lp trnh c vi b dao ng bn trong, mt cng ni tip SPI v 5 mode tit kim nng lng c th la chn mm. - Idle mode dng CPU trong khi vn cho php SRAM, Timer/Counters, cng SPI, v h thng ngt tip tc chc nng ca chng.4


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm - Power-down mode tit kim ni dung thanh ghi, nhng hn nh b dao ng, khng cho php tt c cc chc nng khc ca chp c hot ng cho n khi ngt tip theo hoc Reset phn cng xut hin. - Trong Power-save mode, timer khng ng b tip tc chy, cho php s dng duy tr thi gian nn, trong khi cc phn cn li ca thit b c ng. - ADC Noise Reduction mode dng CPU v tt cc module I/O ngoi tr timer khng ng b v ADC ti thiu ha nhiu mch trong sut qu trnh ADC trong chuyn i. - Trong Standby mode, b dao ng thch anh/ resonator c php chy trong khi cc phn cn li ca thit b c ng. iu ny cho php start-up rt nhanh cng vi hiu qu tiu th t nng lng. Thit b c sn sut p dng cng ngh tch hp b nh non-volatile cao ca Atmel. B nh chng trnh Flash ny c th lp trnh thng qua ghp ni tip SPI bng chng trnh lp trnh b nh non-volatile ring, hoc bng mt chng trnh boot on chip, chy trong AVR core. Chng trnh boot c th s dng bt k mt ghp ni no download chng trnh ng dng trong b nh Flash. Phn mm trong Boot Flash s tip tc chy trong khi cc phn s dng Flash vn c update, h tr cho hot ng c trong khi ghi (Read-While-Write). Bng vic kt hp vi mt CPU 8-bit RISC vi b nh Flash t lp trnh trong h thng trn mt chp, Atmel ATmega8 l mt vi iu khin cc mnh, tha mn yu cu v mt b vi iu khin vi linh hot cao v em li li nhun ln vi rt nhiu cc ng dng iu khin tc ng nhanh. ATmega8 AVR cng h tr y v lp trnh v pht trin cc tool h thng, bao gm b dch C, macro assemblers, b m phng/g ri chng trnh, In-Circuit Emulators, v evaluation kits.

2. Cc vn cn gii quyt o nhit phng Hin th trn my tnh iu khin bng my tnh mt s thit b nh n,qut ng c. Mch gm c Atmega8, cm bit nhit LM35, cng COM trong phn chnh l Atmega8. Tn hiu c nhn bi LM35 qua ADC(tch hp sn trong Atmega8) bin i tn hiu tng t thnh s. tn hiu ny truyn vi giao thc RS 232 i vo COM v kt mi vi my tnh, Qua ,chng ta c th iu khin thit b nh sau: nh nhit bt tt thit b, v d khi nhit phng >30 C th Qut c bt,>100 C th n tt. iu khin trn my tnh hoc set nhit bng bin tr trn board.

Chng II :

Tm Hiu Cu Trc Cc Phn Cng I.ATMEGA81. TNG QUAN Nhng Tnh Nng Chnh Ca ATmega8: o C 8Kbyte b nh flash o C th xa lp trnh c v c th chu c 10000 ln ghi xa. o C 32 thanh ghi a nng 8 bit, o C 512 byte b nh EEPROM tch hp trn chp, o Cc 1 kbyte SRAM ni. o C hai b Timer/counter 8 bit v mt b timer/counter 16 bit vi b chia tn lp trnh c. o C ba knh iu xung, 6 knh li vo chuyn i ADC vi phn gii 10 bit. o Atmega8 c 28 chn, trong c 23 cng vo ra. o Ngun nui t 2.7 n 5.5 i vi Atmega8L v t 4.5 n 5.5 i vi Atmega8, o Lm vic tiu th dng 3.6mA.5


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm o S dng mch dao ng ngoi t 0 n 8 Mhz vi Atmega8L v t 0 n 16 Mhz vi Atmega8. o Ngoi ra chp Atmega8 cn c b xung ni bn trong c th lp trnh ch xung nhp Vi iu khin AVR do hng Atmel ( Hoa K ) sn xut c gi thiu ln u nm 1996. AVR c rt nhiu dng khc nhau bao gm dng Tiny AVR ( nh AT tiny 13, AT tiny 22) c kch thc b nh nh, t b phn ngoi vi, ri n dng AVR ( chn hn AT90S8535, AT90S8515,) c kch thc b nh vo loi trung bnh v mnh hn l dng Mega ( nh ATmega32, ATmega128,) vi b nh c kch thc vi Kbyte n vi trm Kb cng vi cc b ngoi vi a dng c tch hp trn chip, cng c dng tch hp c b LCD trn chip ( dng LCD AVR ). Tc ca dng Mega cng cao hn so vi cc dng khc. S khc nhau c bn gia cc dng chnh l cu trc ngoi vi, cn nhn th vn nh nhau, Hnh 1.1

Block Diagram

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n Mn Hc I in T GVHD: Thy Nguyn Ng Lm . t bit, nm 2008, Atmel li tip tc cho ra i dng AVR mi l XmegaAVR, vi nhng tnh nng mnh m cha tng c cc dng AVR trc . C th ni XmegaAVR l dng MCU 8 bit mnh m nht hin nay.

1.1 Cc dng AVR khc nhau: Tiny, AVR v Mega B Nh D Liu : B nh d liu ca AVR chia lm 2 phn chnh l b nh SRAM v b nh EEPROM. Tuy cng l b nh d liu nhng hai b nh ny li tch bit nhau v c nh a ch ring. B nh SRAM c dng lng 1 K bytes, B nh SRAM c hai ch hot ng l ch thng thng v ch tng thch vi ATmega103, mun thit lp b nh SRAM hot ng theo ch no ta s dng bit cu ch M103C ( M103C fuse bit (9) ). Atmega8 l vi iu khin 8 bit da trn kin trc RISC. Vi kh nng thc hin mi lnh trong vng mt chu k xung clock, Atmega8 c th t c tc 1MIPS trn mi MHz (1 triu lnh/s/MHz). Di y l s khi ca Atmega8

S cu trc Atmega8 ATmega 8 h tr y cc chng trnh v cng c pht trin h thng nh: trnh dch C, macro assemblers, chng trnh m phng/sa li, kit th nghim,..8


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm 2. CU TRC CHUNG AVR CPU ca AVR c chc nng bo m s hot ng chnh xc ca cc chng trnh. Do n phi c kh nng truy cp b nh, thc hin cc qu trnh tnh ton, iu khin cc thit b ngoi vi v qun l ngt. 2.1.Cu trc tng qut AVR s dng cu trc Harvard, tch ring b nh v cc bus cho chng trnh v d liu. Cc lnh c thc hin ch trong mt chu k xung clock. B nh chng trnh c lu trong b nh Flash. 2.2. ALU ALU lm vic trc tip vi cc thanh ghi chc nng chung. Cc php ton c thc hin trong mt chu k xung clock. Hot ng ca ALU c chia lm 3 loi: i s, logic v theo bit. 2.3. Thanh ghi trng thi y l thanh ghi trng thi c 8 bit lu tr trng thi ca ALU sau cc php tnh s hc v logic.

Thanh ghi trng thi SREG C: Carry Flag ;c nh (Nu php ton c nh c s c thit lp) Z: Zero Flag ;C zero (Nu kt qu php ton bng 0) N: Negative Flag (Nu kt qu ca php ton l m) V: Twos complement overflow indicator (C ny c thit lp khi trn s b 2) V, For signed tests (S=N XOR V)S: N H: Half Carry Flag (c s dng trong mt s ton hng s c ch r sau) T: Transfer bit used by BLD and BST instructions(c s dng lm ni chung gian trong cc lnh BLD,BST). I: Global Interrupt Enable/Disable Flag (y l bit cho php ton cc ngt. Nu bit ny trng thi logic 0 th khng c mt ngt no c phc v.) 2.4. Cc thanh ghi chc nng chung

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Thanh ghi chc nng chung Tip ghanh ghi ( register file ) : Tip 32 thanh ghi a chc nng ( $0000 - $001F ) c ni trn, ngoi chc nng l cc thanh ghi a chc nng, th cc thanh ghi t R26 ti R31 tng i mt to thnh cc thanh ghi 16 bit X, Y, Z c dng lm con tr tr ti b nh chng trnh v b nh d liu .Thanh ghi con tr X, Y c th dng lm con tr tr ti b nh d liu, cn thanh ghi Z c th dng lm con tr tr ti b nh chng trnh. Cc trnh bin dch C thng dng cc thanh ghi con tr ny qun l Data stack ca chng trnh C.

Chc nng con tr ca cc thanh ghi R26 R31 2.5. Con tr ngn xp (SP) L mt thanh ghi 16 bit nhng cng c th c xem nh hai thanh ghi chc nng c bit 8 bit. C a ch trong cc thanh ghi chc nng c bit l $3E (Trong b nh RAM l $5E). C nhim v tr ti vng nh trong RAM cha ngn xp.

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Thanh ghi con tr ngn xp Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngn xp gim hai v tr. V con tr ngn xp s gim 1 khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng trnh con c gi hoc cc ngt c cho php phc v. V gi tr ngn xp t nht cng phi ln hn hoc bng 60H (0x60) v 5FH tr li l vng cc thanh ghi. 3.CU TRC NGT CA Atmega8 3.1. KHI NIM V NGT Ngt l mt c ch cho php thit b ngoi vi bo cho CPU bit v tnh trng sn xng cho i d liu ca mnh.V d:Khi b truyn nhn UART nhn c mt byte n s bo cho CPU bit thng qua c RXC,hc khi n truyn c mt byte th c TX c thit lp Khi c tn hiu bo ngt CPU s tm dng cng vic ng thc hin li v lu v tr ang thc hin chng trnh (con tr PC) vo ngn xp sau tr ti vector phuc v ngt v thc hin chng trnh phc v ngt ch ti khi gp lnh RETI (return from interrup) th CPU li ly PC t ngn xp ra v tip tc thc hin chng trnh m trc khi c ngt n ang thc hin. Trong trng hp m c nhiu ngt yu cu cng mt lc th CPU s lu cc c bo ngt li v thc hin ln lt cc ngt theo mc u tin .Trong khi ang thc hin ngt m xut hin ngt mi th s xy ra hai trng hp. Trng hp ngt ny c mc u tin cao hn th n s c phc v. Cn n m c mc u tin thp hn th n s b b qua. B nh ngn xp l vng bt k trong SRAM t a ch 0x60 tr ln. truy nhp vo SRAM thng thng th ta dng con tr X,Y,Z v truy nhp vo SRAM theo kiu ngn xp th ta dng con tr SP. Con tr ny l mt thanh ghi 16 bit v c truy nhp nh hai thanh ghi 8 bit chung c a ch :SPL :0x3D/0x5D(IO/SRAM) v SPH:0x3E/0x5E. Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngn xp gim hai v tr.V con tr ngn xp s gim 1 khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng trnh con c gi hoc cc ngt c cho php phc v. V gi tr ngn xp t nht cng phi ln hn 60H (0x60) v 5FH tr li l vng cc thanh ghi. 3.2. TRNH PHC V NGT V BNG VECTOR NGT i vi mi ngt th phi c mt trnh phc v ngt ISR (Interrupt Service Routine) hay trnh qun l ngt (Interrupt handler). Khi mt ngt c gi th b vi iu khin phc v ngt. Khi mt ngt c gi th b vi iu khin chy trnh phc v ngt. i vi mi ngt th c mt v tr c nh trong b nh gi a ch ISR ca n. Nhm cc v tr nh c dnh ring gi cc a ch ca cc ISR c gi l bng vc t ngt.11


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm Khi kch hot mt ngt b vi iu khin i qua cc bc sau: Vi iu khin kt thc lnh ang thc hin v lu a ch ca lnh k tip (PC) vo ngn xp. N nhy n mt v tr c nh trong b nh c gi l bng vc t ngt ni lu gi a ch ca mt trnh phc v ngt. B vi iu khin nhn a ch ISR t bng vc t ngt v nhy ti . N bt u thc hin trnh phc v ngt cho n lnh cui cng ca ISR l RETI (tr v t ngt). Khi thc hin lnh RETI b vi iu khin quay tr v ni n b ngt. Trc ht n nhn a ch ca b m chng trnh PC t ngn xp bng cch ko hai byte trn nh ca ngn xp vo PC. Sau bt u thc hin cc lnh t a ch . 3.3. BNG VECTOR NGT

3.4. TH T U TIN NGT Khng nh vi iu khin h 8051, th t u tin ca cc ngt c th thay i c ( bng cch lp trnh ). Vi vi iu khin AVR th t u tin cc ngt l khng th thay i v theo qui tc: Mt vec t ngt c a ch thp hn trong b nh chng trnh c mc u tin cao hn . Chn hn ngt ngoi 0 ( INT0 ) c mc u tin cao hn ngt ngoi 1 ( INT1 ). cho php mt ngt ngi dng cn cho php ngt ton cc ( set bit I trong thanh ghi SREG ) v cc bit iu khin ngt tng ng. Khi mt ngt xy ra v ang c phc v th bit I trong thanh ghi SREG b xa, nh th khi c mt ngt khc xy ra n s khng c phc v, do cho php cc ngt trong khi mt ISR ( interrupt service routine ) khc ang thc thi, th trong chng trnh ISR phi c lnh SEI set li bit I trong SREG. 3.5. NGT TRONG NGT. Khi AVR ang thc hin mt trnh phc v ngt thuc mt ngt no th li c mt ngt khc c kch hot. Trong nhng trng hp nh vy th mt ngt c mc u tin cao hn c th ngt mt ngt c mc u tin thp hn. Lc ny ISR ca ngt c mc u tin cao hn s c thc thi(*) .12


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm Khi thc hin xong ISR ca ngt c mc u tin cao hn th n mi quay li phc v tip ISR ca ngt c mc u tin thp hn trc khi tr v chng trnh chnh. y gi l ngt trong ngt

Ch : - Gi nh l khi mt ISR no ang thc thi th xy ra mt yu cu ngt t mt ISR khc c mc u tin thp hn th ISR c mc u tin thp hn khng c phc v, nhng n s khng b b qua lun m trng thi ch. Ngha l ngay sau khi ISR c mc u tin cao hn thc thi xong th n lt ISR c mc u tin thp hn s c phc v. - (*) : iu ny ch xy ra khi trong code ca ISR ca ngt c mc u tin thp hn c lnh set bit I trong thanh ghi SREG ( l lnh SEI ). Cc ngt ngoi Cc ngt ngoi c kch hot bi 2 chn INT0, v INT1. Ch rng nu kch hot, cc ngt s kch bng (trigger even)nu cc chn INT0,INT1 c cu hnh l cc ng ra . Ci c im ny cung cp 1 con ng chung cho ngt mm.Cc ngt ngoi c th c kch bi cnh xung hoc ln hoc mc thp. S ci t ny c ch nh c bit trong thanh ghi iu khin MCU MCUCR. MCU Control Register MCUCR Thanh ghi MCU cha cc bit iu khin ngt c thc kim sot v chc nng MCU chung .

Bit 3, 2 ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

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n Mn Hc I in T GVHD: Thy Nguyn Ng Lm External Interrupt 1 c kch hot bi chn ngoi INT1 nu SREG I-bit v mt n ngt tng ng trong GICR l set(1). Cc mc v cnh trong chn INT1 ngoi kch hot ngt c nh ngha trong

bng sau: Bit 1, 0 ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 External Interrupt 0 c kch hot bi chn ngoi INT0 nu SREG I-bit v mt n ngt tng ng trong GICR l set(1). Cc mc v cnh trong chn INT0 ngoi kch hot ngt c nh ngha trong bng sau:

General Interrupt Control Register GICR

Bit 7 INT1: External Interrupt Request 1 Enable Khi bit INT1 set ln 1 v I-bit trong thanh ghi trng thi SRGE l 1,ngt chn ngoi c kch hot. Ngt tng ng ca External Interrupt Request 1 c thc thi t INT0 Interrupt Vector. Bit 6 INT0: External Interrupt Request 0 Enable Khi bit INT0 set ln 1 v I-bit trong thanh ghi trng thi SRGE l 1,ngt chn ngoi c kch hot. Ngt tng ng ca External Interrupt Request 0 c thc thi t INT0 Interrupt Vector. General Interrupt Flag Register GIFR

Bit 7 INTF1: External Interrupt Flag 1 Khi 1 s kin ti chn INT1 kch hot 1 yu cu ngt INTF1 s ln 1. Nu I-bit trong SREG v bit INT1 trongGICR l 1,MCU s nhy n vector ngt tng ng. C s xa khi thc hin ngt thng xuyn. i khi, c c th c xa nu ta ghi trc tip 1 gi tr vo n Bit 6 INTF0: External Interrupt Flag 0 Khi 1 s kin ti chn INT0 kch hot 1 yu cu ngt INTF0 s ln 1. Nu I-bit trong SREG v bit INT1 trongGICR l 1,MCU s nhy n vector ngt tng ng. C s xa khi thc hin ngt thng xuyn. i khi, c c th c xa nu ta ghi trc tip 1 gi tr vo n 4.CU TRC B NH14


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm AVR c 2 khng gian b nh chnh l b nh d liu vo b nh chng trnh. Ngoi ra Atmega8 cn c thm b nh EEPROM lu tr d liu. 4.1 B nh chng trnh (B nh Flash) B nh Flash 16KB ca Atmega8 dng lu tr chng trnh. Do cc lnh ca AVR c di 16 hoc 32 bit nn b nh Flash c sp xp theo kiu 8KX16. B nh Flash c chia lm 2 phn, phn dnh cho chng trnh boot v phn dnh cho chng trnh ng dng.

Bn b nh chng trnh 4.2 B nh d liu SRAM 1120 nh ca b nh d liu nh a ch cho file thanh ghi, b nh I/O v b nh d liu SRAM ni. Trong 96 nh u tin nh a ch cho file thanh ghi v b nh I/O, v 1024 nh tip theo nh a ch cho b nh SRAM ni.

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Bn b nh d liu SRAM Cc ch truy nhp a ch ca AVR 4.2.1 a ch thanh ghi n trc tip ch d ny a ch ca thanh ghi c ly trc tip t vng cc thanh ghi (t 0 ti 31).

V d: COM Rd NEG Rd 4.2.2 a ch hai thanh ghi trc tip16


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm y l ch m trong mt lnh ALU truy nhp trc tip vo hai thanh ghi. Ch ny hon ton tng t nh ch trn.

V d: ADD Rd,Rr 4.2.3 a ch trc tip cng vo ra Trong a ch ca ton hng c cha trong 6 bit ca mt t lnh .n l a ch ca thanh ghi ngun hoc ch.

V d: Out DDRB, R16 In R12, DDRB

4.2.4 Trc tip d liu a ch ca d liu trong RAM c a trc tip vo lnh.

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V d: LDS R12,0x0fff STS 0x0fff,R11

4.2.5 a ch d liu gin tip cng vi dch chuyn

V d: LDD R11,Y+10 a ch ca ton hng ngun hoc ch c tr bi thanh ghi Y hoc Z cng thm mt ch s no

4.2.6 a ch gin tip d liu: y l cch m CPU truy nhp ti d liu trong RAM thng qua thanh ghi X,Y,Z a ch ca d liu c lu trong thanh ghi ny.

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V d: ST X,R11 LD R13,Y

4.2.7 a ch d liu gin tip cng vi tng hoc gim con tr

V d: LD R17,X+ LD -Y,R14 4.2.8 a ch ca hng s trong b nh chng trnh. Cch ny ch s dng cho lnh LPM a ch ca hng s c lu trong thanh ghi Z

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V d: LDI R30,0x07;dia chi truc tiep du lieu 0x07 LDI R31,0xFF LPM ; a ni dung ca nh c a ch trong Z (0x07FF )v thanh ghi R0. 4.2.9 a ch b nh chng trnh gin tip: a ch on m c tr bi thanh ghi Z s dng trong cc lnh IJMP v ICALL.

V d: Label: LDI R29,High(Label) LDI R28,Low(Lebel) ICALL 4.2.10 a ch tng di ca b nh chng trnh Cch nh a ch ny dng cho cc lnh RJMPv RCALL khi CPU s c gi tr PC+k+1.

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V d: Label: LDI R29,High(Label) LDI R28,Low(Lebel) RCALL Label

4.2.11 Cc thanh ghi chc nng c bit Bao gm cc thanh ghi d liu v cc thanh ghi iu khin cc cng vo ra. Chng c th truy nhp c bng 2 cch: Bng a ch trc tip V d: STR $3F,R11 hoc: STR SREG.R11 Hoc c th truy nhp gin tip chng thng qua thanh ghi X, Y, Z. V d : LDI R28,0x00 LDI R27,0x5F STD X,R11 Hai v d ny hon ton tng ng, u ghi d liu vo thanh ghi SREG.

4.2.12 Status Register (SREG) y l thanh ghi trng thi c 8 bit lu tr trng thi ca ALU sau cc php tnh s hc v logic.

C: Carry Flag ;c nh (Nu php ton c nh c s c thit lp)21


n Mn Hc I in T Z: Zero Flag ;C zero (Nu kt qu php ton bng 0) N: Negative Flag (Nu kt qu ca php ton l m)


V: Twos complement overflow indicator (C ny c thit lp khi trn s b 2) V, For signed tests (S=N XOR V)S: N H: Half Carry Flag (c s dng trong mt s ton hng s c ch r sau) T: Transfer bit used by BLD and BST instructions(c s dng lm ni chung gian trong cc lnh BLD,BST). I: Global Interrupt Enable/Disable Flag (y l bit cho php ton cc ngt.Nu bit ny trang thi logic 0 th khng c mt ngt no c phc v.) Registers and Operands (k hiu cc thanh ghi v cc ton hng) Rd: Thanh ghi ch (mt trong 32 cc thanh ghi chc nng chung) Rr: Thanh ghi ngun (Mt trong 32 thanh ghi chc nng chung) R: Kt qu sau khi lnh chy. K: Hng s d liu k: Hng s a ch (C th l mt nhn hoc mt a ch c th) b: Bit trong thanh ghi chc nng chung hoc trong thanh ghi chc nng c bit (0-7). s: Bit trong thanh ghi trng thi (0-7). X,Y,Z: Thanh ghi a ch ( tr ti a ch trong RAM,hoc Z c th tr ti a ch trong ROM). (X=R27:R26, Y=R29:R28 and Z=R31:R30) A: I/O location address q:Ch s cho cc a ch trc tip (0-63).

4.2.13 Stack Pointer L mt thanh ghi 16 bit nhng cng c th c xem nh hai thanh ghi chc nng c bit 8 bit. C a ch trong cc thanh ghi chc nng c bit l $3E (Trong b nh RAM l $5E). C nhim v tr ti vng nh trong RAM cha ngn xp.

22


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngn xp gim hai v tr. V con tr ngn xp s gim 1 khi thc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng trnh con c gi hoc cc ngt c cho php phc v. V gi tr ngn xp t nht cng phi ln hn hc bng 60H (0x60) v 5FH tr li l vng cc thanh ghi.

4.3 B nh d liu EEPROMAtmega8 cha b nh d liu EEPROM dung lng 512 byte, v c sp xp theo tng byte, cho php cc thao tc c/ghi tng byte mt. y l b nh d liu c th ghi xa ngay trong lc vi iu khin ang hot ng v khng b mt d liu khi ngun in cung cp b ct. C th v b nh d liu EEPROM ging nh l cng ( Hard disk ) ca my vi tnh. EEPROM c xem nh l mt b nh vo ra c nh a ch c lp vi SRAM, iu ny c ngha l ta cn s dng cc lnh in, out khi mun truy xut ti EEPROM. iu khin vo ra d liu vi EEPROM ta s dng 3 thanh ghi sau : 4.3.1 Thanh Ghi EEAR ( EEARH v EEARL )

EEAR l thanh ghi 16 bit lu gi a ch ca cc nh ca EEPROM, thanh ghi EEAR c kt hp t 2 thanh ghi 8 bit l EEARH v thanh ghi EEARL. 4.3.2 Thanh Ghi EEDR y l thanh ghi d liu ca EEPROM, l ni cha d liu ta nh ghi vo hay ly ra t EEPROM.

4.3.3 Thanh Ghi EECR y l thanh ghi iu khin EEPROM, ta ch s dng 4 bit u ca thanh ghi ny, 4 bit cui l d tr, ta nn ghi 0 vo cc bit d tr. Sau y ta xt chc nng ca tng bit.

Bit 3 EERIE: EEPROM Ready Interrupt Enable : y l bit cho php23


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm EEPROM ngt CPU, khi bit ny c set thnh 1 v ngt ton cc c cho php ( bng cch set bit I trong thanh ghi SREG ln 1 ) th EEPROM s to ra mt ngt vi CPU khi bit EEWE c xa, iu ny c ngha l khi cc ngt c cho php ( bit I trong thanh ghi SREG v bit EERIE trong thanh ghi EECR c set thnh 1 ) v qu trnh ghi vo ROM va xong th s to ra mt ngt vi CPU, chng trnh s nhy ti vc t ngt c a ch l $002C thc thi chng trnh phc v ngt ( ISR ). Khi bit EERIE l 0 th ngt khng c cho php. Bit 2 EEMWE: EEPROM Master Write Enable : Khi bit EEMWE v bit EEWE l 1 s ra lnh cho CPU ghi d liu t thanh ghi EEDR vo EEPROM, a ch ca nh cn ghi trong EEPROM c lu trong thanh ghi EEAR . Khi bit ny l 0 th khng cho php ghi vo EEPROM. Bit EEMWE s c xa bi phn cng sau 4 chu k my. Bit 1 EEWE: EEPROM Write Enable : Bit ny va ng vai tr nh mt bit c, va l bit iu khin vic ghi d liu vo EEPROM. vai tr ca mt bit iu khin nu bit EEMWE c set ln 1 th khi ta set bit EEWE ln 1 s bt u qu trnh ghi d liu vo EEPROM. Trong sut qu trnh ghi d liu vo EEPROM bit EEWE lun gi l 1. vai tr ca mt bit c khi qu trnh ghi d liu vo EEPROM hon tt, phn cng s t ng xa bit ny v 0. Trc khi ghi d liu vo EEPROM ta cn phi bit chc l khng c qu trnh ghi EEPROM no khc ang xy ra, bit c iu ny ta cn kim tra bit EEWE. Nu bit EEWE l 1 tc l EEPROM ang c ghi, ta phi ch cho cho qu trnh ghi vo EEPROM hon tt th mi ghi tip. Nu bit EEWE l 0 tc l khng c qu trnh ghi EEPROM no ang din ra, lc ny ta c th bt u ghi d liu vo EEPROM. Khi bit EEWE c set ln 1 ( bt u ghi vo EEPROM ) CPU s tm ngh trong 2 chu k my trc khi thc hin lnh k tip. Bit 0 EERE: EEPROM Read Enable : Khi bit ny l 1, s cho php c d liu t EEPROM, d liu t EEPROM c a ch lu trong thanh ghi EEAR lp tc c chuyn vo thanh ghi EEDR. Khi bit EERE l 0 th khng cho php c EEPROM. Trc khi c d liu t EEPROM ta cn bit chc l khng din ra qu trnh ghi EEPROM bng cch kim tra bit EEWE. l sau khi qu trnh c EEPROM hon tt, bit EERE s c t ng xo bi phn cng. Nu EEPROM ang c ghi th ta khng th c c d liu t EEPROM. Khi bt u qu trnh c d liu t EEPROM, CPU s tm ngh 4 chu k my trc khi thc hin lnh k tip. Tm li ghi vo EEPROM ta cn thc hin cc bc sau: 1. Ch cho bit EEWE v 0. 2. Cm tt c cc ngt. 3. Ghi a ch vo thanh ghi EEAR. 4. Ghi d liu m ta cn ghi vo EEPROM vo thanh ghi EEDR. 5. Set bit EEMWE thnh 1. 6. Set bit EEWE thnh 1 . 7. Cho php cc ngt tr li. Nu mt ngt xy ra gia bc 5 v 6 s lm hng qu trnh ghi vo EEPROM bi v bit EEMWE sau khi set ln 1 ch c gi trong 4 chu k my, chng trnh ngt s lm ht thi gian ( time out ) duy tr bit ny mc 1. Mt ngt xut hin cui bc 4 cng c th lm cho a ch v d liu cn ghi vo EEPROM tr nn khng chnh xc nu trong chng trnh phc v ngt c chnh sa li cc thanh ghi EEAR v EEDR. l l do ta cn cm cc ngt trc khi thc hin tip cc bc 3, 4, 5, 6. Qu trnh ghi d liu vo EEPROM cng c th khng an ton nu in th ngun nui ( Vcc ) qu thp. c d liu t EEPROM: Vic c d liu t EEPROM n gin hn ghi d liu vo EEPROM, c d liu t EEPROM ta thc hin cc bc sau: 1. Ch cho bit EEWE v 0. 2. Ghi a ch vo thanh ghi EEAR. 3. Set bit EERE ln 1.

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n Mn Hc I in T


5 .Cc cng vo ra (I/O)Vi iu khinATmega8 c 23 ng vo ra chia lm 2 nhm 8 bit,mt nhm 7 bit . Cc ng vo ra ny c rt nhiu tnh nng v c th lp trnh c. y ta s xt chng l cc cng vo ra s. Nu xt trn mt ny th cc cng vo ra ny l cng vo ra hai chiu c th nh hng theo tng bit. V cha c in tr pull-up (c th lp trnh c). Mc d mi port c cc c im ring nhng khi xt chng l cc cng vo ra s th dng nh iu khin vo ra d liu th hon ton nh nhau. Chng ta c thanh ghi v mt a ch cng i vi mi cng, l : thanh ghi d liu cng ( PORTB, PORTC, PORTD), thanh ghi d liu iu khin cng (DDRB, DDRC, DDRD) v cui cng l a ch chn vo ca cng (PINB, PINC, PIND). 5.1 Cc chc nng ca Port B XTAL2/TOSC2 Port B, Bit 7 XTAL2: Chn 2 dao ng to clock. S dng chn clock thch anh,hoc dao ng thch anh tn s thp. Khi dng chn lm dao ng th khng th lm chn nhp xut c na. TOSC2: Chn 2 l dao dng Timer. Nu PB7 c dng lm clock pin, DDB7, PORTB7 and PINB7 s s hiu l mc 0 XTAL1/TOSC1 Port B, Bit 6 XTAL1: Chip clock Oscillator pin 1. TOSC1: Timer Oscillator pin 1. Nu PB6 dng lm chn clock, DDB6, PORTB6 and PINB6 s hiu l mc 0.

SCK Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. Khi SPI c kch hot l Slave, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB5. MISO Port B, Bit 4 MISO: Master Data input, Slave Data output pin for SPI channel. Khi SPI c kch hot l Master, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB4. MOSI/OC2 Port B, Bit 3

25


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm MOSI: SPI Master Data output, Slave Data input for SPI channel. Khi SPI c kch hot l Slave, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB3. Khi SPI c kch hot l Master, d liu trc tip ca chn ny c iu khin bi DDB3. SS/OC1B Port B, Bit 2 SS: Slave Select ng vo. Khi SPI c kch hot l Slave, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB2. OC1A Port B, Bit 1 OC1A, Output Compare Match output:Chn PB1 c th x l nh 1 ng ra bn ngoi Timer/Counter1 Compare Match A. ICP1 Port B, Bit 0 ICP1 chn gi(cht) ng vo : Chn PB0 c th tc ng lm 1 chn gi cho Timer/Counter1. 5.2 Cc chc nng ca Port C RESET Port C, Bit 6 RESET, Reset pin: Khi cu ch RSTDISBL lp trnh, chc nng ca chn ny l vo ra binh thng,v 1 phn s phi da vo Power-on Reset v Brown-out Reset nh l ngun reset ca n. Nu chn PC6 dng l chn reset , DDC6, PORTC6 v PINC6 s hiu l mc 0.

SCL/ADC5 Port C, Bit 5 SCL, giao din ni tip hai dy Xung nhp: Khi bit TWEN trong TWCR set (one) bt giao din ni tip hai dy, pin PC5 b ngt t port v tr thnh chn Serial Clock I/O cho Two-wire Serial Interface. SDA/ADC4 Port C, Bit 4 SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for the Twowire Serial Interface. ADC3 Port C, Bit 3 PC3 cng c th dng l ADC input Channel 3. Ch l ADC input channel 3 dng ngun xoay chiu. ADC2 Port C, Bit 2 PC2 cng c th dng l ADC input Channel 2. Ch l ADC input channel 2 dng ngun xoay chiu. ADC1 Port C, Bit 1 PC1 cng c th dng l ADC input Channel 1. Ch l ADC input channel 1 dng ngun xoay chiu. ADC0 Port C, Bit 0 PC0 cng c th dng l ADC input Channel 0. Ch l ADC input channel 0 dng ngun xoay chiu 5.3 Cc chc nng ca Port D

26


n Mn Hc I in T


AIN1 Port D, Bit 7 AIN1,b so snh tng t th ng ng vo. Cu hnh chn ca port l nhp vo vi ngt pull-up bn trong trnh nhiu t port s vi chc nng ca b so snh tng t. AIN0 Port D, Bit 6 AIN0,B so snh tng t ng vao tch cc. Cu hnh chn ca port l nhp vo vi ngt pull-up bn trong trnh nhiu t port s vi chc nng ca b so snh tng t. T1 Port D, Bit 5 T1, s lng m ngun Timer/Counter1. XCK/T0 Port D, Bit 4 XCK, USART xung nhp ngoi. T0, s lng m ngun Timer/Counter0. INT1 Port D, Bit 3 INT1, Ngt ngun bn ngoi 1: Chn PD3 c th lm chc nng nh 1 ngun ngt ngoi. INT0 Port D, Bit 2 INT0, Ngt ngun bn ngoi 0: Chn PD2 c th lm chc nng nh 1 ngun ngt ngoi. TXD Port D, Bit 1 TXD, Truyn ti d liu (chn d liu ra ca USART). Khi b truyn USART c kch hot ,chn ny c cu hnh nh l mt ng ra bt k gi tr ca DDD1. RXD Port D, Bit 0 RXD, Nhn d liu (chn d liu vo ca USART). Khi b nhn USART c kch hot ,chn ny c cu hnh nh l mt ng vo bt k gi tr ca DDD0

5.4 M t thanh ghi ca port I/OThe Port B Data Register PORTB

The Port B Data Direction Register DDRB

The Port B Input Pins Address PINB

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n Mn Hc I in T


The Port C Data Register PORTC

The Port C Data Direction Register DDRC

The Port C Input Pins Address PINC

The Port D Data Register PORTD

The Port D Data Direction Register DDRD

The Port D Input Pins Address PIND

Tm li: 1. c d liu t ngoi th ta phi thc hin cc bc sau: a d liu ra thanh ghi iu khin DDRxn t cho PORTx (hoc bit n trong port) l u vo (xa thanh ghi DDRx hoc bit). Sau kch hot in tr pull-up bng cch set thanh ghi PORTx ( bit). Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit).

2. a d liu t vi iu khin ra cc cng cng c cc bc hon ton tng t. Ban u ta cng phi nh ngha l cng ra bng cch set bit tng ng ca cng .v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx.

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n Mn Hc I in T


6. B nh thi 8bit timer/counter 0B nh thi (timer/counter0) l mt module nh thi/m 8 bit, c cc c im sau: B m mt knh Xa b nh thi khi trong mode so snh (t ng np) PWM To tn s B m s kin ngoi B chia tn 10 bit Ngun ngt trn b m v so snh S cu trc ca b nh thi:

Hnh 5.1. S cu trc b nh thi AVR Atmega8 c tch hp b timer/counter. Ta bt u phn ny bng s khi sau:

6.1 Hot ng ca b Timer/Couter+ Mch m ln lm thanh ghi TCNTn tng 1 n v mi khi c xung clkTn, khi t gi tr ln nht (8bit=255), c TOVn c set (logic 1) v b m trn, gi tr b n TCNTn tr v 00 v tip tc m. + Xung clkTn c th c la chn t nhiu ngun khc nhau. Khi chn xung ni (system clock), Timer/Counter l mt Timer. Khi chn xung ngoi (thng qua chn Tn) Timer/Counter l Counter. Hot ng ny c th din t bng gin xung sau:

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n Mn Hc I in T


Cng ging nh b timer/counter trong cc vi iu khin khc, chng ta quan tm n 2 thanh ghi: Timer/Counter Control v Timer/Counter Value. Trong AVR, l thanh ghi TCCRn v TCNTn.

Clock Select Bit Description

TCNT0 - Timer/C TCNT0 v OCR0 l cc thanh ghi 8 bit. Cc tn hiu yu cu ngt u nm trong thanh ghi TIFR. Cc ngt c th c che bi thanh ghi TIMSK.

30


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm B nh thi c th s dng xung clock ni thng qua b chia hoc xung clock ngoi trn chn T0. Khi chn xung clock iu khin vic b nh thi/b m s dng ngun xung no tng gi tr ca n. Ng ra ca khi chn xung clock c xem l xung clock ca b nh thi (clkT0). Thanh ghi OCR0 lun c so snh vi gi tr ca b nh thi/b m. Kt qu so snh c th c s dng to ra PWM hoc bin i tn s ng ra ti chn OC0. 6.2 n v m Phn chnh ca b nh thi 8 bit l mt n v m song hng c th lp trnh c. Cu trc ca n nh hnh di y:

Hnh 5.2. n v m count: tng hay gim TCNT0 1 direction: la chn gia m ln v m xung clear: xa thanh ghi TCNT0 clkT0: xung clock ca b nh thi TOP: bo hiu b nh thi tng n gi tr ln nht BOTTOM: bo hiu b nh thi gim n gi tr nh nht (0) 6.3 n v so snh ng ra

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n Mn Hc I in T


Hnh 5.3. S n v so snh ng ra B so snh 8 bit lin tc so snh gi tr TCNT0 vi gi tr trong thanh ghi so snh ng ra (OCR0). Khi gi tr TCNT0 bng vi OCR0, b so snh s to mt bo hiu. Bo hiu ny s t gi tr c so snh ng ra (OCF0) ln 1 vo chu k xung clock tip theo. Nu c kch hot (OCIE0=1), c OCF0 s to ra mt ngt so snh ng ra v s t ng c xa khi ngt c thc thi. C OCF0 cng c th c xa bng phn mm.

6.4 M t cc thanh ghi6.4.1 Thanh ghi iu khin b nh thi/b m TCCR0

Hnh 5.4. Thanh ghi iu khin b nh thi Bit 7-FOC0: So snh ng ra bt buc Bit ny ch tch cc khi bit WGM00 ch nh ch lm vic khng c PWM. Khi t bit ny ln 1, mt bo hiu so snh bt buc xut hin ti n v to dng sng. Bit 6, 3-WGM01:0: Ch to dng sng Cc bit ny iu khin m th t ca b m, ngun cho gi tr ln nht ca b m (TOP) v kiu to dng sng s c s dng. Bit 5:4-COM01:0: Ch bo hiu so snh ng ra Cc bit ny iu khin hot ng ca chn OC0. Nu mt hoc c hai bit COM01:0 c t ln 1, ng ra OC0 s hot ng. Bit 2:0: CS02:0: Chn xung ng h Ba bit ny dng la chn ngun xung cho b nh thi/b m.32


n Mn Hc I in T


6.4.2 Thanh ghi b nh thi/b m

Hnh 5.5. Thanh ghi b nh thi Thanh ghi b nh thi/b m cho php truy cp trc tip (c c v ghi) vo b m 8 bit. Thanh ghi ny cha mt gi tr 8 bit v lin tc c so snh vi gi tr ca b m. 6.4.3 Thanh ghi mt n ngt

Hnh 5.7. Thanh ghi mt n ngt TIMSK . Bit 1-OCIE0: Cho php ngt bo hiu so snh Bit 0-TOIE0: Cho php ngt trn b m 6.4.4 Thanh ghi c ngt b nh thi

Bit 1-OCF0: C so snh ng ra 0 Bit 0-TOV0: C trn b m Bit TOV0 c t ln 1 khi b m b trn v c xa bi phn cng khi vector ngt tng ng c thc hin. Bit ny cng c th c xa bng phn mm.

33


n Mn Hc I in T


7. B nh thi/m timer/counter 1 16-bit7.1 s khi v mt s c im

B nh thi (timer/counter1) l mt module nh thi/m 16 bit, c cc c im sau: True 16-bit Design (i.e., allows 16-bit PWM) 2 n v ng vo so snh c lp(Two Independent Output Compare Units) i thanh ghi so snh ng ra m(Double Buffered Output Compare Registers) 1 n v cht ng vo(One Input Capture Unit) B chng nhiu li vo(Input Capture Noise Canceler) Xa timer trong Compare Match (Clear Timer on Compare Match (Auto Reload)) chng nhiu sc ngang(Glitch-free, Phase Correct Pulse Width Modulator (PWM) Gi tr chu k PWM B pht tn s chung B m s kin ngoi 4 ngun ngt c lp (TOV1, OCF1A, OCF1B, and ICF1)

7.2 Mt s nh nghaBOTTOM B m t ti BOTTOM khi co gi tr 0x0000 MAX B m t ti MAXimum khi khi t gi tr 0xFFFF (decimal 65535). TOP B m t ti TOP khi n bng vi gi tr ln nht ca chui m. Gi tr ny c th c gn bi cc gi tr c nh : 0x00FF, 0x01FF, or 0x03FF,hoc gi tr trong b nh ca cc thanh ghi OCR1A ,ICR1 . 7.3 M t cc thanh ghi34


n Mn Hc I in T 7.3.1 Timer/Counter 1 Control Register A TCCR1A


Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 COM1A1:0: Compare Output Mode for channel A Bit 5:4 COM1B1:0: Compare Output Mode for channel B COM1A1: 0 v COM1B1: 0 iu khin chn so snh trng thi ng ra (OC1A v OC1B tng ng). Nu mt hay c hai bit COM1A1:0 c set ln 1 th ng ra OC1A s u tin hn chc nng port I/O thng thng m n kt ni ti . Nu mt hay c hai bit COM1B1:0 c set ln 1 th ng ra OC1B s u tin hn chc nng port I/O thng thng m n kt ni ti . Tuy nhin ch l bit ca thanh ghi DDR tng ng vi cc chn OC1A, OC1B, OC1C phi c set cho php ng ra. Khi OC1A, OC1B, OC1C c kt ni ti chn th tc dng ca cc bit COM1X1:0 cn ph thuc vo la chn ca cc bit WGM3:0. Nh bng sau th hin chc nng khi cc bit WGM13:0 l set bnh thng.

Table 37 hin th chc nng ca bit COM1x1:0 khi cc bit WGM13:0 l set ch PWM nhanh.

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n Mn Hc I in T


Bit 3 FOC1A: Force Output Compare for channel A Bit 2 FOC1B: Force Output Compare for channel B Cc bit FOC1A/FOC1B ch hot ng khi cc bit c bit WGM13:0 khng ch PWM. .khi bit FOC1A/FOC1B c gi tr l 1,ngay lp tc Compare Match(Compare Match :y l mt chc nng ca b nh thi, theo , gi tr ca b nh thi (tc gi tr thanh ghi TCNTn (n=0,..,2)) lin tc c so snh snh vi gi tr ca thanh ghi OCRn (n=0,..,2). Khi hai gi tr ny bng nhau s to ra s thay i mc logic chn OCn (n=0,..,2). Nh , ta c th to ra xung PWM ng ra OCn (n=0,..,2) ca vi iu khin.) b buc vo dng sng n v chung (waveform generation unit). Ng ra OC1A/OC1B b thay i cho ph hp vi iu chnh cc bit COM1x1:0.Cc bit FOC1A/FOC1Blun trng thi 0. Bit 1:0 WGM11:0: Waveform Generation Mode S kt hp vi cc bit WGM13:2 tm thy trong thanh ghi TCCR1B,nhng bit ny iu khin dy m ca b m, gc gi tr ln nht (TOP) ca b m, v nhng loi sng chung c s dng , nhn bng Table 39. Cc ch ca h thng c h tr boier Timer/Counter l : Normal mode (counter), Clear Timer on Compare Match (CTC) mode,v ba loi ca cc ch Pulse Width Modulation (PWM).

7.3.2 Timer/Counter 1 Control Register B TCCR1B

Bit 7 ICNC1: Input Capture Noise Canceler iu chnh bit ny ln 1 kch hot Input Capture Noise Canceler. Khi noise canceler hot ng, ng vo t chn Input Capture Pin (ICP1) c lc. Yu cu chc nng ca b 4 gi tr k bng vi chn ca ICP1 cho s thay i ca ng ra. Bit 6 ICES1: Input Capture Edge Select Bit ny c chn sao cho cnh ln trong Input Capture Pin (ICP1) dng khi ng bt gi s kin. Khi bit ICES1 set l 0, cnh xung c dng , v khibit ICES1 set l 1, cnh ln s khi ng bt gi. Khi vic bt gi c kch hot theo iu chnh ca ICES1 ,gi tr b m sao chp vo Input Capture Register (ICR1). S kin cng s set c Input Capture Flag (ICF1), v iu ny c th dng v mt Input Capture Interrupt,nu ngt ny c kch hot. Khi ICR1 c dng vi gi tr TOP (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), ICP1 b ngt kt ni v gi nguyn chc nng Input Capture l disable.36


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm Bit 5 Reserved Bit Bit ny dng trong tng lai. Bit 4:3 WGM13:2: Waveform Generation Mode Tng t thanh ghi TCCR1A. Bit 2:0 CS12:0: Clock Select Ba bit la chn xung nhp la chn xung ngun c dng bi Timer/Counter

7.3.3 Timer/Counter 1 TCNT1H and TCNT1L

Thanh ghi b nh thi TCNT1 l thanh ghi 16 bit c kt hp t hai thanh ghi TCNT1H v thanh ghi TCNT1L. Thanh ghi TCNT1 c th c hay ghi. c 2 byte ca TCNT 1 c c hay ghi ng thi ngi ta dng mt thanh ghi tm 8 bit byte cao 8-bit Temporary High Byte Register (TEMP). Thanh ghi TEMP c chia s cho tt c cc thanh ghi 16 bit khc. Khng nn chnh sa thanh ghi TCNT1 khi n ang m trnh b hng Compare Match gia TCNT1 v mt trong nhng thanh ghi OCR1X . 7.3.4 Output Compare Register 1 A OCR1AH and OCR1AL

7.3.5 Output Compare Register 1 B OCR1BH and OCR1BL

Thanh ghi output compare register (OCR1A/OCR1B) l thanh ghi 16 bit, gi tr ca n c lin tc so snh vi b m (TCNT1). Khi c s bng nhau ca hai thanh ghi ny s to ra mt ngt so snh hay mt dng sng chn ng ra so snh OC1X. Ng ra cua thanh ghi so snh co c l 16 bit. nn c hai byte cao v thp ca thanh ghi c ghi hay c ng thi khi CPU cn truy xut thanh ghi ny, ngi ta dng thanh ghi tm byte cao (TEMP), thanh ghi TEMP lun lu gi byte cao ca cc thanh ghi 16 bit khi cc thanh ghi ny cn dng ti n37


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm Ch l khi ghi mt gi tr vo thanh ghi OCR1X trong lc b m ang chy, th gi tr ca thanh ghi OCR1X c th cp nht tc thi, nhng cng c th ch c cp nht khi b m t ti mt gi tr no , chn hn, gi tr TOP, BOTTOM 7.3.6 Input Capture Register 1 ICR1H and ICR1L

Tng t nh trn! Cc bn c th tham khao k hn trong datasheet. 7.3.7 Timer/Counter Interrupt Mask Register TIMSK

Bit 5 TICIE1: Timer/Counter1, Input Capture Interrupt Enable Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt bt mu ng vo b Timer/couter1 (Timer/Counter1 Input Capture interrupt) c cho php. Vector ngt tng ng s c thc thi khi c ICF1 trong thanh ghi TIFR c set.. Bit 4 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 1A (Timer/Counter1 Output Compare A Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF1A trong thanh ghi TIFR c set. Bit 3 OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt so snh ng ra 1B (Timer/Counter1 Output Compare B Match Interrupt) c cho php. Vector ngt tng ng s c thc thi khi c OCF1B trong thanh ghi TIFR c set. Bit 2 TOIE1: Timer/Counter1, Overflow Interrupt Enable Khi bit ny c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt c trn b nh thi 1 (Timer/Counter1 overflow interrupt) c cho php. Vector ngt tng ng s c thc thi khi c TOV1 trong thanh ghi TIFR c set. 7.3.8 Timer/Counter Interrupt Flag Register TIFR

Bit 5 ICF1: Timer/Counter1, Input Capture Flag C ny c set khi xy ra s kin bt mu ng vo (Input Capture) ca chn ICP1. Khi thanh ghi ICR1 (Input Capture Register) c thit lp bi cc bit WGMn3:0 s dng nh mt gi tr TOP th c ICF1 s c set khi b m t ti gi tr TOP. C ICF1 s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 4 OCF1A: Timer/Counter1, Output Compare A Match Flag C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1A (Output Compare Register A). Ch l mt so snh cng bc (FOC1A) s khng set c ny. C OCF1A s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 3 OCF1B: Timer/Counter1, Output Compare B Match Flag

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n Mn Hc I in T GVHD: Thy Nguyn Ng Lm C ny c set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1B (Output Compare Register B). Ch l mt so snh cng bc (FOC1B) s khng set c ny. C OCF1B s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bng cch ghi mt gi tr logic vo v tr ca n. Bit 2 TOV1: Timer/Counter1, Overflow Flag Vic thit lp c ny ph thuc vo thit lp ca cc bit WGMn3:0, trong ch bnh thng v CTC c TOV1 c set khi b nh thi trn.

8.SPI(Serial peripheral interface)8.1 S v nh nghaSPI l mt giao din thc hin vic trao i d liu gia cc thit b tng thch vi khung d liu 8bit v c truyn ng b (cng xung nhp ng h). SPI cho php truyn d liu ni tip ng b gia thit b ngoi vi v vi iu khin AVR hoc gia cc vi iu khin AVR. SPI ca AT90S8535 c cc c im c bit sau: Ch song cng, truyn d liu ng b 3 dy. C th gi vai tr Master hoc Slave. Bit MSB hoc LSB c th c truyn trc ty vo ngi lp trnh. Bn tc truyn c th lp trnh thng qua hai bit C ngt bo kt thc truyn Vn hnh t trng thi ng (c nh thc t trng thi ng). S cu trc:

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n Mn Hc I in T GVHD: Thy Nguyn Ng Lm iu khin khi giao tip SPI th chng ta c 3 thanh ghi. l 1 thanh ghi iu khin SPCR (SPI control Register), thanh ghi trang thi SPSR (SPI status Register) v cui cng l thanh ghi d liu SPDR (SPI Data Register). 8.2 M t thanh ghi 8.2. 1.Thanh ghi SPCR: y l thanh ghi 8 bit c a ch trong cc thanh I/O l 0x0D v trong SRAM l 0x2D, cc bit trong thanh ghi ny u c th c hoc ghi. Bit 7-SPIE: SPI interrupt enable Bit ny cho php ngt ca b truyn tin SPI (nu ngt ton cc v ngt ny c cho php th nu c SPIF c bt th ngt s c phc v.) Bit 6-SPE: SPI Enable Nu bit ny c set th khi SPI s c hot ng v n phi c set trong sut qu trnh SPI hot ng. Bit 5-DORD: Data order Khi m DORD c set th LSB ca byte d liu s c truyn trc v ngc li. Bit 4-MSTR: Master/Slave select y l bit dng la chn ch master hay slave.Nu bit ny c set th b SPI ny c vai tr l Master v ngc li.Nu nh SS c cu hnh l li vo v c t xung mc thp th MSTR b xa v 0v SPIF v SPSR b t ln 1 khi ta s phi t li MSTR v 1. Bit 3-CPOL: Clock polarity Khi bit ny c set th SCK mc cao trong trang thi ng v ngc lai. Bit 2-CPHA:Clock Phase Quy nh pha kch hot ca xung nhip. Bit 1,0-SPR1,SPR0 :Clock rate select: y l hai bit iu khin tc xung nhp truyn ca kt ni v c thit lp trn Master. N khng c tc dng g nu nh ta thit lp trn slave. V gi tr ca chng ng theo t hp cc bit nh sau:

SPR1 0 0 1 1

SPR0 0 1 0 1

Tn s SCK Fcl/4 Fcl/16 Fcl/64 Fcl/128

Nh vy y l thanh ghi iu khin ton b khi SPI t vai tr (Master/slave n tc truyn,cho php ngt,cho php hot ng,mc logic trong trang thi ng v pha kch hot xung nhp. 8.2.2.Thanh ghi SPSR:40


n Mn Hc I in T GVHD: Thy Nguyn Ng Lm y l thanh ghi 8 bit (c a ch 0x0e/0x2e)lu gi trng thi ca b truyn nhn SPI.Nhng n ch c hai bt c nh ngha c kh nng c v ghi.Cc bit cn li khng c nh ngha v khi c chng th c gi tr zero. Bit 7-SPIF: SPI interrupt Flag Khi truyn xong mt byte d liu th bit ny c set v mt ngt c to ra.Nu bit cho php ngt SPIE trong thanh ghi SPCR c set v ngt ton cc c cho php th ngt c thi hnh.Nu khng n s b b qua.Khi m chn ss ca Master c nh ngha l cng vo li c thit lp mc thp th c ny cng c set.N c xa bi phn cng hi ngt c phc v. Bit 6-WCOL: wite collision flag C bo xung t khi ghi:C ny c set ln 1 nu nh d liu c ghi ln thanh ghi d liu SPI khi ang din ra mt cuc truyn.V n c xa cng vi c SPIF khi c thanh ghi trng thi v truy nhp vo thanh ghi d liu. bt u mt cuc truyn th ta cn cho php b truyn nhn hot ng.Khi truyn ta ch cn ghi byte d liu cn truyn ln thanh ghi d liu v i cho ti khi c c SPIF bt ln ri tip tc truyn byte mi. bt u nhn d liu cng vy.SPI c khi ng,ch khi no c SPIF bt ln th ta c d liu (c t xa khi ta c thanh ghi trng thi). 8.2.3.Thanh ghi SPDR: y cng l thanh ghi 8 bit (0x0f/0x2f) c th c v ghi c.N c s dng truyn d liu gia hai bn truyn nhn SPI.Ghi d liu vo thanh ghi ny c ngha l ta bt u cuc truyn.V c d liu t thanh ghi ny l c d liu c nhn. 8.2.4.Nguyn l hot ng:

y l s ghp ni gia hai b SPI song cng (nh ca 2 vi iu khin AVR). i vi VK AVR th cc chn SCK (Serial clock) l chn PB7,y l chn xung nhp ra trong trng hp n l Master v l chn xung nhp vo nu n l Slave.khi ghi d liu ln thanh ghi d liu SPDR ca khi Master s khi ng b to xung v d liu c dch v a ra chn MOSI (PB5) v vo chn MOSI ca slave (PB5 i vi AVR).Sau khi dch ht mt byte b to xung ngng hot ng,v c SPIF c pht bo kt thc truyn.Nu nh ngt ny c php th chng trnh phc vu ngt s c phc v v khi c s b xa.u vo la chn slave (SS v l chn PB4) c set mc tch cc thp la chn thit b SPI slave v c dng cho vic ghp ni nhiu VK.Hai thanh ghi dch ca hai b truyn v nhn (Master v slave) c xem nh l mt thanh ghi dch vng 16 bit.V trong mt ln trao i d liu th d liu thanh ghi ca Master v slave trao i cho nhau.Mt bSIP lm ng thi c hai nhim v truyn v nhn nhng chng li ch c mt b m khi truyn c hai b m khi nhn.Nh vy c ngha l d liu truyn i s khng c ghi ln thanh ghi d liu truyn nu nh byte trc cha c truyn xong (hay c SPIF cha c bt).V khi nhn d liu cng vy d liu cn phi c c trc khi d liu mi c nhn xong.41


n Mn Hc I in T Bng cu hnh chn:


9.TWI Two Wire InterfaceTwo Wire Interface l mt si dy kt ni bus 2 chiu ,m n ph hp vi IC v SMBus. Mt thit b c kt ni n mt bus phi hnh ng nh l mt ch hoc th cp.u master thc hin giai on u cho s vn chuyn d liu vi u salve trn bus,v hi xem n c mun vn chuy hay nhn d liu hay khng.Mt bus c th c nhiu master,v mt b x l iu phi u tin ,nu hai hoc nhiu master c gng vn chuyn cng mt thi m.

Module TWi bao gm bus ch logic m n c th thu thp thng tin tm cc iu kin ngng v bt u ,bus b ng v bus b li .iu ny c th c s dng xc nh ch bus (chy khng ,ch, ,bn hoc khng bit) trong kiu master .Bus ch logic tip tc hot ng trong tt c cc ch ngh bao gm ch ngun gim. Thut ngTWI The following definitions are frequently encountered in this section.

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n Mn Hc I in T


10.B so snh tng t(Alalog Comparator)B so snh tng t ca AVR c u vo l hai chn PB2 v PB3 (nh hnh v). Vi chn PB2 c ni vo cc dng ca b so snh v PB3 c ni vo cc m ca b so snh.N to ra hai mc logic nu V+>V- th tn hiu ra l 1 v ngc li l 0.

iu khin v qua st trng thi ca b so snh tng t ta c mt thanh ghi l thanh ghi ACSR.Trc khi tm hiu v nguyn tc hot ng ca n ta s gii thiu v thanh ghi ny. Thanh ghi ACSR l mt thanh ghi 8 bit c a ch trong cc thanh ghi I/O l 0x08 v c a ch trong khng gian b nh SRAM l 0x28.Trong 8 bit th c 7 bit c nh ngha v bit 6 khng c nh ngha.N ch c th c v lun c gi tr logic l 0. 1.Bit 7-ACD:Analog comparator disable y l bit iu khin. Bit ny ttrc tip iu khin hot ng ca AC(b so snh tng t). Nu nh bit ny c set ln 1 th ngun cung cp cho AC hot ng b tt (turn off) v ng ngha vi vic n khng hot ng.V nu n c xa th AC c cp ngun v hot ng bnh thng.Ch :Ta c th thay i gi tr logic ca bit ny lc no cng c ngng hot ng ca chng hoc cho chng hot ng tr li nhng khi thay i gha tr logic ca n th ngt (ngt ca AC)cn b cm nu khng n s sinh ra mt ngt (C th l bit ACIE cn b xa). 2.Bit 5-ACO:Analog comparator output y l bit trng thi. Bit ny c ni trc tip vi u ra ca b so snh tng t. 3.Bit 4-ACI:Analog comparator interrupt flag y l bit trng thi. C bo ngt ca b so sanh tng t.Nu nh c ny c set v cc ngt c php th mt chng trnh phc v ngt c gi v chng c xa bng phn cng khi chng trinh bo ngt c phc v. Cc trng hp lm thay i trng thi c ny ngoi vic thay i bit ACD s c ni ti trong cc bt o v 1. 4.Bit 3-ACIE:AC interrupt enable y l bit iu khin. Nu bit ny c set th ngt ny c php v ngc li. 5.Bit 2ACIC:Analog comparator input Capture Enable y l bit iu khin. Khi bit ny c set ln 1 th u ra ca AC c ni trc tip vo u vo ca chc nng bt s kin ca Timer/counter 1.( c thm timer/counter1). 6.Bit ACIS1 v ACIS0 :Ac interrupt mode select y l hai bit iu khin.

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n Mn Hc I in T ACIS1 0 0 1 1

GVHD: Thy Nguyn Ng Lm ACIS0 0 1 0 1 Ch ngt Theo mc Dnh ring(cha dng n) Sn xung Sn ln

Ch : Cc bit ny cng c th c thay i bt c khi no. Nhng khi thay i th ngt ca n phi b cm. Ta c th s dng lnh SBI hoc CBIU thay i trng thi cc bit trn thanh ghi ny tr bit ACI. Bit ny sau khi c c cng s b xa (nu n c set). Thit lp port u vo cho b so snh tng t: Hai chn PB2 v PB3 ny cn c thit lp l u vo b in tr treo. lp trnh cho AC ta bt u cc bc sau: Bc 1: Thit lp cc chn u vo cho AC. Bc 2: Chn cc ch cho AC v nh dng ngt Bc 3: Khi ng AC bng cch xa bit ACD.

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11.USART ( Universal asynchronous receiver/transmitter )11.1 c im B truyn nhn ni tip ng b v bt ng b l mt thit truyn thng ni tip c cc chc nng chnh nh sau: Hot ng song cng (cc thanh ghi truyn v nhn ni tip c lp vi nhau). Hot ng ng b hoc bt ng b B to tc baud c chnh xc cao H tr khung truyn ni tip vi 5, 6, 7, 8, hoc 9 bit d liu v 1 hoc 2 bit stop Kim tra chn l Pht hin trn d liu Pht hin li khung Lc nhiu, bao gm pht hin bit start li v b lc thng thp s Ngt khi kt thc truyn, thanh ghi truyn ht d liu v kt thc nhn Ch truyn thng a vi x l Ch truyn ng b tc cao S khi ca b USART nh sau:

S khi b USART45


USART bao gm 3 phn chnh: b to xung clock, b truyn v b nhn. Cc thanh ghi iu khin c s dng chung gia cc phn ny.

11.2 To xung clockB to xung clock to ra xung ng h cn bn cho b truyn v b nhn. USART h tr 4 ch hot ng xung clock: bt ng b, bt ng b tc cao, truyn ng b master v truyn ng b slave. S khi ca b to xung clock nh sau:

Hnh 6.2. n v to xung clock . txclk: xung ng h b truyn rxclk: xung ng h b nhn xcki: tn hiu vo t chn XCK, s dng cho hot ng truyn ng b master xcko: tn hiu xung clock ng ra ti chn XCK, s dng cho hot ng truyn ng b slave fosc: tn s t chn XTAL 11.3 nh dng khung truyn USART chp nhn tt c 30 t hp ca cc nh dng khung truyn sau y: 1 bit start 5, 6, 7, 8, hoc 9 bit d liu C hoc khng c bit chn l 1 hoc 2 bit stop Mt khung truyn bt u vi mt bit start, theo sau l bit c trng s thp nht (LSB) ca d liu (c th ln ti 9 bit), kt thc bng bit c trng s ln nht (MSB) v bit stop.

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nh dng khung truyn St: bit start (mc thp) (n): bit d liu (0 n 8) P: bit chn l Sp: bit stop (mc cao) IDLE: khng c d liu truyn (mc cao trong sut thi gian idle) 11.4 Khi to USART Qu trnh khi to USART bao gm vic thit lp tc baud, thit lp nh dng khung v kch hot b truyn v b nhn. V d di y thit lp hot ng truyn bt ng b s dng polling (khng dng ngt) v nh dng khung truyn l c nh. Tc baud l mt tham s ca hm. void USART_Init( unsigned int baud ) { /* Set baud rate */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1Text); sp->Write(so,0,1); so[1] = Convert::ToByte(txtq->Text); sp->Write(so,1,1); so[2] = Convert::ToByte(txtdc->Text); sp->Write(so,2,1); } private: System::Void button3_Click(System::Object^ System::EventArgs^ e) { x=!x; if(x) { tm->Stop(); button3->Text="OK"; txtd->Enabled=true; txtq->Enabled=true; txtdc->Enabled=true; btndk->Enabled=false; } else { button3->Text="cai dat nhiet do tu may tinh"; txtd->Enabled=false; txtq->Enabled=false; txtdc->Enabled=false; array ^ so; so = gcnew array (3); so[0] = Convert::ToByte(txtd->Text); so[1] = Convert::ToByte(txtq->Text); so[2] = Convert::ToByte(txtdc->Text); sp->Write(so,0,3); btndk->Enabled=true; tm->Start(); } } sender,

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private: System::Void Form1_Load(System::Object^ e) { sp->Open(); tm->Start(); tm2->Start(); txtd->Enabled=false; txtq->Enabled=false; txtdc->Enabled=false; txtdk->Enabled=false; btnok->Enabled=false;

sender, System::EventArgs^

} private: System::Void tm_Tick(System::Object^ sender, System::EventArgs^ { tm->Stop(); Stringâ1; Stringâ2; unsigned int den; unsigned int quat; unsigned int dongco; unsigned int m; unsigned int ndo; m=sp->BytesToRead; if(m==0) lbnd->Text="khong co du lieu"; else { a1=sp->ReadExisting(); array^b1; b1=a1->Split(';'); a2=Convert::ToString(b1[1]); array^b2; b2=a2->Split('r'); lbnd->Text=b2[1]; ndo=Convert::ToInt32(b2[1]); den=Convert::ToInt32(txtd->Text); quat=Convert::ToInt32(txtq->Text); dongco=Convert::ToInt32(txtdc->Text); if(ndo>=den) lbdd->BackColor=Color::Red; else lbdd->BackColor=Color::Blue; if(ndo>=quat) lbq->BackColor=Color::Red; else lbq->BackColor=Color::Blue; if(ndo>=dongco) lbdc->BackColor=Color::Red; else lbdc->BackColor=Color::Blue; }

e)

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tm->Start();

} private: System::Void tm1_Tick(System::Object^ sender, System::EventArgs^ e) { tm1->Stop(); Stringâ1; Stringâ2; unsigned int m; m=sp->BytesToRead; if(m==0) lbnd->Text="Khong Co Du Lieu"; else { a1=sp->ReadExisting(); array^b1; b1=a1->Split(';'); a2=Convert::ToString(b1[1]); array^b2; b2=a2->Split('r'); txtdk->Text=b2[0]; } tm1->Start(); } private: System::Void btndk_Click(System::Object^ e) { tm->Stop(); y=!y; if(y) { tm1->Start(); btndk->Text="OK"; lbtb->Text="DEN"; txtdk->Enabled=true; btnok->Enabled=true; button3->Enabled=false; } else { btndk->Text="Cai Dat Nhiet Do Tu Vi Dieu Khien"; btnok->Enabled=false; lbtb->Text="Thiet Bi"; txtdk->Text=" "; txtdk->Enabled=false; array ^ so; so = gcnew array (3); so[0] = Convert::ToByte(txtd->Text); so[1] = Convert::ToByte(txtq->Text); so[2] = Convert::ToByte(txtdc->Text); sp->Write(so,0,3); sender, System::EventArgs^

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button3->Enabled=true; tm1->Stop(); tm->Start(); } } private: System::Void btnok_Click(System::Object^ sender, System::EventArgs^ e) { i++; if(i==1) { lbtb->Text="Quat"; txtd->Text=txtdk->Text; } if(i==2) { lbtb->Text="D.CO"; txtq->Text=txtdk->Text; } if(i==3) { lbtb->Text="DEN"; txtdc->Text=txtdk->Text; i=0; } } private: System::Void lb_Click(System::Object^ sender, System::EventArgs^ e) { } private: System::Void tm2_Tick(System::Object^ sender, System::EventArgs^ e) { lbht->Text="CHUONG TRINH DO NHIET DO VA DIEU KHIEN THIET BI "; lbht1->Text="HIEN THUC SINH VIEN DAO THANH MAI+ NGUYEN DUC DAI"; j--; k++; lbht->Location=Point(j,9); lbht1->Location=Point(k,38); if(j==(-650)) j=450; if(k==450) k=-650; } }; }

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3.Kt Qu:

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Phn V1. Hn ch: ng dng ca Atmega8 mi ch dung li 1 d n nh o nhit ,chng ta cn c th lm c tt nhiu ng dng ln hn na. Qu trnh lm n ny a phn ti liu t ting anh nn gp kh nhiu kh khn v thi gian v s chnh xc. chnh xc ca mch o cn cha chnh xc do linh kin(LM35) v board(hn,chn tip xc). Kh khn ng k na l thi gian kh gp( ri vo ma thi )nn nhiu mt ca n khng trnh khi nhng sai st. Trong qu trnh lm nhm vn cha c thng nht vi nhau.

2. Kt qu t c: o c nhit tng ng kh chnh xc. Tm hiu v bit ng dng v Atmega8. Tm hiu v bit v ADC0809,LM35,COM c th phc v tt cho nhng n tip theo. Rn luyn k nng c v dch ti liu ting anh. C kh nng tm kim v lc thng tin trn mng internet,th vin 3. HNG PHT TRIN N : V y trng tm n l em nghin cu cc ng dng ca ATmega 8 . v lm trn bo mch th nghim . hiu v bit cc chc nng ca Atmega8 Hng pht trin c th lm mt bo mch th nghim phc v cho vic ging dy v vi iu khin AVR m in hnh l ATmega 8 Nu pht trin thnh b kit th nghim th c nhng ng dng sau : Board mch c 2 led mu cho php vit bi th nghim led blinky, ngoi ra 2 led ny c ni vi 2 chn to xung cho php thc hin bi th nghim PWM (dng Pulse Width Modulation iu khin sng ca led). Board mch c 4 nt nhn, cc nt ny kt ni vi cc chn Interrupts INT0, INT1 v ng vo m T0, T1 ca Timer; nn cho php d dng lm cc bi th nghim v ngt ngoi v lp trnh b m xung. -Mt bin tr ngoi cho php th nghim ADC. -C header cho php kt ni vi module wireless RF FSK. - Module RS232 giao tip vi my tnh qua cng COM97


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Modele USB TO TTL RS232 giao tip vi my tnh qua cng USB ca laptop -C header SPI interface cho php giao tip SPI hoc kt ni vi module SPI 8 led 7 on ca CLB. -C header I2C interface cho php kt ni vi IC nh 24XX hoc IC thi gian thc giao tip I2C. Module giao tip vi LED LCD V cn nhiu ng dng na

4.Ti liu tham kho :o lng v iu khin my tnh : Ng Din Tp o lng iu khin my tnh : Nguyn c Thnh Datasheet ATMEGA8,COM,LM35,ADC0809 Website:Dientuvietnam.net,internet

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