DMODELING OF FUZZY LOGIC CONTROL S/M FOR CONTROLLING HOMOGENCITY OF LIGHT INTENSITY FROM LEDoc

8/12/2019 DMODELING OF FUZZY LOGIC CONTROL S/M FOR CONTROLLING HOMOGENCITY OF LIGHT INTENSITY FROM LEDoc

1/47

MODELING OF FUZZY LOGIC CONTROL S/M FOR

CONTROLLING HOMOGENCITY OF LIGHT INTENSITY

FROM LEDCHAPTER 1

INTRODUCTION

The project is aimed at developing a simple low cost, low parts number, using easy to find

components) and compact flashlight, using ultra-low power capabilities of the MCU.The circuit is powered by a single cylindrical NiMH AA/AAA battery.The MCU is powered from a small step-up (1.2V is too low to power up the MCU). When

no light is emitted system will be in impressively low-power mode (MCU off, icc ~ 1.5uA)=>

shelf life = 78 years for a AAA 1000mAh (of course not achievable, limited to batterys shelf

life). When light is generated, MCU will mostly stay in LPM0 and wake up from time to time to

check user switches and current limiter.Light is generated by 1 super-bright (>20000 mcd) white LED (SBWLED). This LED is

powered from a step-up DC-DC converter (boost topology) controlled by the MCU with PWM.

The current is sensed through 0.5R using SD16 ADC and upper-limited to avoid LEDsmelting.

Protection is added in case of led failure by open. The user will have two switches UP (to start or to increase luminosity) and DOWN

(decrease luminosity or to stop). Software de-bouncing is implemented for both.


2/47

1.1Organization of the Thesis

In view of the proposed thesis work explanation of theoretical aspects and algorithms used in thiswork are presented as per the sequence described below.Chapter 1 describes a brief review of the objectives and goals of the work.

Chapter 2 discusses the existing technologies and the study of various technologies in detail.Chapter 3 describes the Block diagram, Circuit diagram of the project and its description. The

construction and description of various modules used for the application are described in detail.Chapter 4 description of ATMEGA8Chapter 5 description of PWM

Chapter 6 POTENTIOMETER DescriptionChapter 7 explains the Software tools required for the project, the Code developed for the design.

Chapter 8 presents the results, overall conclusions of the study

Chapter 9 proposes possible improvements and directions of future research work.Chapter 10 presents references.


3/47

Chapter 2OVERVIEW OF THE TECHNOLOGIES USED

Embedded Systems:An embedded system can be defined as a computing device that does a specific focused

job. Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine,

mobile phone etc. are examples of embedded systems. Each of these appliances will have a

processor and special hardware to meet the specific requirement of the application along with the

embedded software that is executed by the processor for meeting that specific requirement.

The embedded software is also called firm ware. The desktop/laptop computer is a

general purpose computer. You can use it for a variety of applications such as playing games,

word processing, accounting, software development and soon.

In contrast, the software in the embedded systems is always fixed listed below:Embedded systems do a very specific task; they cannot be programmed to do different

things. Embedded systems have very limited resources, particularly the memory. Generally, they

do not have secondary storage devices such as the CDROM or the floppy disk. Embedded

systems have to work against some deadlines. A specific job has to be completed within aspecific time. In some embedded systems, called real-time systems, the deadlines are stringent.

Missing a deadline may cause a catastrophe-loss of life or damage to property. Embedded

systems are constrained for power. As many embedded systems operate through a battery, the

power consumption has to be very low. Some embedded systems have to operate in extreme

environmental conditions such as very high temperatures and humidity. Following are the advantages of Embedded Systems:1. They are designed to do a specific task and have real time performance constraints which

must be met.

2. They allow the system hardware to be simplified so costs are reduced.

3. They are usually in the form of small computerized parts in larger devices which serve a

general purpose.

4. The program instructions for embedded systems run with limited computer hardware


4/47

resources, little memory and small or even non-existent keyboard or screen.

Chapter 3Hardware Implementation of the Project

This chapter briefly explains about the Hardware Implementation of the project. It

discusses the design and working of the design with the help of block diagram and circuit

diagram and explanation of circuit diagram in detail. It explains the features, general purpose

input output (GPIO) configuring as input of atmega8 microcontroller. It also explains the various

modules used in this project.

3.1 Project Design

The implementation of the project design can be divided in two parts. Hardware implementation Firmware implementation

Hardware implementation deals in drawing the schematic on the plane paper according to

the application, testing the schematic design over the breadboard using the various ICs to find if

the design meets the objective, carrying out the PCB layout of the schematic tested on

breadboard, finally preparing the board and testing the-designed hardware.

The firmware part deals in programming the microcontroller so that it can control the

operation of the ICs used in the implementation. In the present work, we have used the kicad

design software for PCB circuit design, the AVR STUDIO software development tool to write

and compile the source code, which has been written in the C language. The PROGISP

programmer has been used to write this compile code into the microcontroller. The firmware

implementation is explained in the next chapter. The project design and principle are explained in this chapter using the block diagram

and circuit diagram. The block diagram discusses about the required components of the design

and working condition is explained using circuit diagram and system wiring diagram.


5/47

BLOCK DIAGRAMThe block diagram of the project is as shown in the figure 3.1

Fig 3.1: block diagram

Brief explanation of functioning of each block of the system is given below the detailed

is given in next chapters.

3.2 Power Supply:The input to the circuit is applied from the regulated power supply. The a.c. input i.e.,

230V from the mains supply is step down by the transformer to 12V and is fed to a rectifier. The

output obtained from the rectifier is a pulsating d.c voltage. So in order to get a pure d.c voltage,

the output voltage from the rectifier is fed to a filter to remove any a.c components present even

after rectification. Now, this voltage is given to a voltage regulator to obtain a pure constant dc

voltage. The block diagram of regulated power supply is shown in the figure 3.2


6/47

Fig 3.2 components of power supplyTransformer:

Usually, DC voltages are required to operate various electronic equipment and these

voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus the a.c input

available at the mains supply i.e., 230V is to be brought down to the required voltage level. This

is done by a transformer. Thus, a step down transformer is employed to decrease the voltage to a

required level.Rectifier:

The output from the transformer is fed to the rectifier. It converts A.C. into pulsating

D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a bridge rectifier is

used because of its merits like good stability and full wave rectification.

Filter:Capacitive filter is used in this project. It removes the ripples from the output of rectifier

and smoothens the D.C. Output received from this filter is constant until the mains voltage and

load is maintained constant. However, if either of the two is varied, D.C. voltage received at this

point changes. Therefore a regulator is applied at the output stage.Voltage regulator:

As the name itself implies, it regulates the input applied to it. A voltage regulator is an

electrical regulator designed to automatically maintain a constant voltage level. In this project,


7/47

power supply of 5V and 12V are required. In order to obtain these voltage levels, 7805 and 7812

voltage regulators are to be used. The first number 78 represents positive supply and the numbers

05, 12 represent the required output voltage levels.

ATMEGA8

The AtmelAVR

core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction executed in one clock cycle. The

resulting architecture is more code efficient while achieving throughputs up to ten times faster

than conventional CISC microcontrollers. The ATmega8 provides the following features: 8

Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of

EEPROM, 1 Kbyte of SRAM, 23 general purpose I/O lines, 32 general purpose working

registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a

serial programmable USART, a byte oriented Two- wire Serial Interface, a 6-channel ADC

(eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable

Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power

saving modes. The Idle mode stops the CPU while allowing the SRAM; Timer/Counters, SPI

port, and interrupt system to continue functioning.

3.3 System wiring diagram and working procedure:


8/47

DIAGRAM HERE


9/47

Chapter 4Microcontroller

4.1 Definition of a MicrocontrollerMicrocontroller, as the name suggests, are small controllers. They are like single chip

computers that are often embedded into other systems to function as processing/controlling unit.

For example, the remote control you are using probably has microcontrollers inside that do

decoding and other controlling functions. They are also used in automobiles, washing machines,

microwave ovens, toys ... etc, where automation is needed.

The key features of microcontrollers include:

High Integration of Functionality

Microcontrollers sometimes are called single-chip computers because they have on-chip

memory and I/O circuitry and other circuitries that enable them to function as small

standalone computers without other supporting circuitry.

Field Programmability, Flexibility

Microcontrollers often use EEPROM or EPROM as their storage device to allow field

programmability so they are flexible to use. Once the program is tested to be correct then

large quantities of microcontrollers can be programmed to be used in embedded systems.

Easy to Use

Assembly language is often used in microcontrollers and since they usually follow RISC

architecture, the instruction set is small. The development package of microcontrollers often

includes an assembler, a simulator, a programmer to "burn" the chip and a demonstration

board. Some packages include a high level language compiler such as a C compiler and more

sophisticated libraries.


10/47

Most microcontrollers will also combine other devices such as:

A Timer module to allow the microcontroller to perform tasks for certain time periods.

A serial I/O port to allow data to flow between the microcontroller and other devices such

as a PC or another microcontroller.

An ADC to allow the microcontroller to accept analogue input data for processing.

Figure 4.1 a typical microcontroller device and its different subunitsThe heart of the microcontroller is the CPU core. In the past this has traditionally been

based on an 8-bit microprocessor unit. Figure 4.1 above Shows a typical microcontroller device

and its different subunits4.2 Microcontrollers versus Microprocessors

Microcontroller differs from a microprocessor in many ways. First and the most

important is its functionality. In order for a microprocessor to be used, other components such as

memory, or components for receiving and sending data must be added to it. In short that means

that microprocessor is the very heart of the computer. On the other hand, microcontroller is

designed to be all of that in one. No other external components are needed for its application


11/47


12/47

flexible and cost-effective solution to many embedded control applications. The ATmega8 is

supported with a full suite of program and system development tools, including C compilers,

macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. The

high-performance AtmelAVR

ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. For a detailed description,4.3.1Key features

High-performance, Low-power AtmelAVR

8-bit Microcontroller.

Advanced RISC Architecture

130 Powerful InstructionsMost Single-clock Cycle Execution

32 8 General Purpose Working Registers

Fully Static Operation Up to 16MIPS Throughput at 16MHz On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments. 8Kbytes of In-System Self-programmable Flash program memory

512Bytes EEPROM, 1Kbyte Internal SRAM

Write/Erase Cycles: 10,000 Flash/100,000 EEPROM. Data retention: 20 years at 85C/100 years at 25C. Optional Boot Code Section with Independent Lock Bits. In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security Peripheral Features, Two 8-bit Timer/Counters with Separate Presale, one Compare

Mode One 16-bit Timer/Counter with Separate Pre scaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels

8-channel ADC in TQFP and QFN/MLF package Eight Channels 10-bit Accuracy.


13/47

6-channel ADC in PDIP package Six Channels 10-bit Accuracy Byte-oriented Two-wire Serial Interface. Programmable Serial USART.

Master/Slave SPI Serial Interface.

Programmable Watchdog Timer with Separate On-chip Oscillator. On-chip Analog Comparator Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby 23 Programmable I/O Lines, 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF. 2.7V - 5.5V (ATmega8L),4.5V - 5.5V (ATmega8)

Power Consumption at 4Mhz, 3V, 25C


14/47

Fig: 4.2Block diagram


15/47

The high-performance AtmelAVR

ALU operates in direct connection with all the 32 general

purpose working registers. Within a single clock cycle, arithmetic operations between general

purpose registers or between a register and an immediate are executed. The ALU operations are

divided into three main categoriesarithmetic, logical, and bit-functions. Some implementations

of the architecture also provide a powerful multiplier supporting both signed/unsigned

multiplication and fractional format. For a detailed description,The Status Register contains information about the result of the most recently executed arithme-

tic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations,Status Register

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software

Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the

RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the

application with the SEI and CLI instructions, as described in theInstruction Set Reference.
http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf


16/47

Bit Copy StorageThe Bit Copy instructions BLD (Bit Load) and BST (Bit Store) use the T-bit as source or

destination for the operated bit. A bit from a register in the Register File can be copied into T by

the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.Half Carry FlagThe Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful

in BCD arithmetic. See the Instruction Set Descriptionfor detailed informationTwos Complement Overflow FlagThe Twos Complement Overflow Flag V supports twos complement arithmetics. See theInstruction Set Descriptionfor detailed informationNegative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See theInstruction Set Descriptionfor detailed informationZero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the InstructionSet Descriptionfor detailed informatiCarry FlagThe Carry Flag C indicates a Carry in an arithmetic or logic operation. See the Instruction SetDescriptionfor detailed informationGeneral Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by
http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf


17/47

the Register File: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result inputAVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions As shown in Figure , each register is also assigned a

Data memory address, mapping them directly into the first 32 locations of the user Data Space.

Although not being physically implemented as SRAM locations, this memory organization

provides great flexibility in access of the registers, as the X-pointer, Y-pointer, and Z-pointer

Registers can be set to index any register in the file


18/47

MEMORYThis section describes the different memories in the Atmel AVR

ATmega8. The AVR

architecture has two main memory spaces, the Data memory and the Program Memory space. In

addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces

are linear and regular.Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions As shown in Figure, each register is also assigned a

Data memory address, mapping them directly into the first 32 locations of the user Data Space.

Although not being physically implemented as SRAM locations, this memory organization

provides great flexibility in access of the registers, as the X-pointer, Y-pointer, and Z-pointer

Registers can be set to index any register in the file.In-System Reprogrammable Flash memoryThe ATmega8 contains 8Kbytes On-chip In-System Reprogrammable Flash memory for pro-

gram storage. Since all AVR instructions are 16-bits or 32-bits wide, the Flash is organized as4K 16 bits. For software security, the Flash Program memory space is divided into two

sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8 Pro-

gram Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The

operation of Boot Program section and associated Boot Lock Bits for software protection are

described in detail in Boot Loader Support Read-While-Write Self-Programming

SRAM DATA MEMORY

The lower 1120 Data memory locations address the Register File, the I/O Memory, and the

internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the

next 1024 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with


19/47

Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the

Register File, registers R26 to R31 feature the indirect addressing pointer registers.The direct addressing reaches the entire data space.The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y-register or Z-register.When using registers indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y and Z are decremented or incrementedANALOG TO DIGITAL CONVERTERFeatures

10-bit Resolution 0.5 LSB Integral Non- Linearity. 2 LSB Absolute Accuracy 13s - 260s Conversion

Up to 15 kSPS at Maximum

Resolution 6 Multiplexed Single Ended Input

Channels

Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF

Package only) Optional Left Adjustment for ADC Result

Readout

0 - VCC

ADC Input Voltage Range Selectable 2.56V ADC Reference

Voltage

Free Running or Single Conversion

Mode Interrupt on ADC Conversion

Complete Sleep Mode Noise


20/47

Canceler

The ATmega8 features a 10-bit successive approximation ADC. The ADC is connected to an 8-

channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from

the pins of Port C. The single-ended voltage inputs refer to 0V (GND).The ADC contains a

Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant

level during conversion. A block diagram of the ADC is shown in fig. The ADC has a separate

analog supply voltage pin, AVCC. AVCC must not differ more than 0.3Vfrom V

CC. See the paragraph

ADC Noise Canceller how to connect this pin.Internal reference voltages of nominally 2.56V or AVCC are

provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a

capacitor for better noise performance.

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-


21/47

mation. The minimum value represents GND and the maximum value represents the voltage on

the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be

connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The

internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to

improve noise immunity.

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC

input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single

ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in

ADCSRA. Volt- age reference and input channel selections will not go into effect until ADEN

is set. The ADC does not consume power when ADEN is cleared, so it is recommended to

switch off the ADC before entering power saving sleep modes.The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.The ADC has its own interrupt which can be triggered when a conversion completes. When

ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the

interrupt will trigger even if the result is lost.A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.


22/47

In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register.

Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first

conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode

the ADC will perform successive conversions independently of whether the ADC Interrupt Flag,

ADIF is cleared or not.

By default, the successive approximation circuitry requires an input clock frequency between50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bitin ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is

continuously reset when ADEN is low.


23/47

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC

clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set)

takes 25 ADC clock cycles in order to initialize the analog circuitry.The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal

conversion and 13.5 ADC clock cycles after the start of an first conversion. When a

conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In

single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC

again, and a new conversion will be initiated on the first rising ADC clock edge.In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion timesADC Multiplexer Selection Register - ADMUX

Bit 7:6 REFS1:0: Reference SelectionThese bits select the voltage reference for the ADC, as shown in Table 74. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an

external reference voltage is being applied to the AREF pin.


24/47

REFS

1REFS

0Voltage Reference Selection

00AREF, Internal Vref turned off01AVCC with external capacitor at AREF pin10Reserved11Internal 2.56V Voltage Reference with external capacitor at

AREF pin

Bit 5 ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data

Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.

Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any

ongoing conversions. For a complete description of this bit, see The ADC Data Register

ADCL and ADCH on page 201. Bits 3:0 MUX3:0: Analog Channel Selection Bits

The value of these bits selects which analog inputs are connected to the ADC. See Table 75 for

details. If these bits are changed during a conversion, the change will not go in effect until this

conversion is complete (ADIF in ADCSRA is set).


25/47

MUX3..0Single Ended Input0000ADC00001ADC10010ADC20011ADC30100ADC40101ADC5

MUX3..0Single Ended Input0110ADC60111ADC710001001101010111100110111101.30V (VBG)


26/47

11110V (GND)

C

ADC CONTROL AND STATUS REGISTER (ACSRA)

Bit 7ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning

theADC off while a conversion is in progress, will terminate this conversion.

Bit 6ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running

mode, write this bit to one to start the first conversion. The first conversion after ADSC has

been written after the ADC has been enabled, or if ADSC is written at the same time as the

ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion

performs initializa- tion of the ADC.


27/47

ADSC will read as one as long as a conversion is in progress. When the conversion is

complete, it returns to zero. Writing zero to this bit has no effect.

Bit 5ADFR: ADC Free Running Select

When this bit is set (one) the ADC operates in Free Running mode. In this mode, the ADC

sam- ples and updates the Data Registers continuously. Clearing this bit (zero) will terminate

Free Running mode.

Bit 4ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt Handling Vector.

Alter- natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a

Read-Modify- Write on ADCSRA, a pending interrupt can be disabled. This also applies if the

SBI and CBI instructions are used.

Bit 3ADIE: ADC Interrupt EnableWhen this bit is written to one and the I-bit in SREG is set, the ADC Conversion

Complete Inter- rupt is activated.

Bits 2:0ADPS2:0: ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input

clock to the adc.


28/47

ADC prescalar bitsADPS2ADPS1ADPS0Division Factor

0002001201040118

100161013211064111128

ADC DATA REGISTER ADCL & ADCH


29/47


30/47

Phase correction PWM mode is preferred for motor controlling because dual- slope operation

provides symmetric wave generation. Duty cycle of pulse can be varied by writing the values to

OCRn register. The OCRn value can be calculate by the following formula:

For example: if duty cycle is 75% OCR value = (75100) 256

Frequency of PWM output will be

Objective : Generate PWM signal of duty cycle 75% from timer 0. Circuit description:The connection of ATmega8 is shown in circuit diagram. Since, Timer0 is used to generate

PWM wave then output is taken on OC0 pin, so pin no.4 is connected to C.R.O to observe the

waveform.

Programming steps:1. Select Phase Correct PWM mode by programming WGM0 [1:0] bit.2. Program COM0 [1:0] bit and select inverting or non-inverting mode .

3. Set OC0 pin as output pin.4. Set OCIE0 bit of TIMSK register.5. Enable global interrupt by sei() command.Output wave:Frequency calculation by formula:


31/47

Output frequency = Crystal frequency(Prescaler 510)= 12000000(1510)

= 23529.41 = 23.53KHzThe following picture shows the output wave form which is received on CRO. The measured

frequency of wave is 23.54 KHz.

Chapter-6


32/47

POTENTIOMETER

6.1 PotentiometerVariable resistors used as potentiometers have all three terminals connected. This

arrangement is normally used to vary voltage, for example to set the switching point of a circuit

with a sensor, or control the volume (loudness) in an amplifier circuit. If the terminals at the ends

of the track are connected across the power supply, then the wiper terminal will provide a

voltage which can be varied from zero up to the maximum of the supply.

Fig pot


33/47

Chapter 7Firmware Implementation of the project designThe firmware programmed in ATMEGA8 is designed to communicate with pot(adc &

pwm) and leds intensity varies accordingly. Therefore, the main firmware programmed can be

divided into three parts:1. Receive the Data from pot and processing and validating.

2. Intensity of leds various acc to pot.

7.1AVR STUDIO OverviewAVR Studio, the popular Software, combines Project Management, Source Code Editing,

Program Debugging, and Flash Programming in a single, powerful environment.

Project Management, Device Setup, and Tool Configuration.Editor facilities for Creating, Modifying, and Correcting ProgramsTarget Debugging or CPU & Peripheral Simulation.Open the AVR Studio from the start menu.


34/47


35/47

Creating a new Project

Click on the New Project button.

Selecting the compiler and creating the project name and click on the next button


36/47

Choose AVR simulator from the left list and controller from the right list and press finish.


37/47

Writing the source code


38/47

Save the program by pressing ctrl + S or choosing save from the file menu

ASSEMBLING:

To convert your program to machine language press F7 or select Build from the Build menu or

click the build icon in the toolbar.

See the Build window. The window shows if your program has syntax error or not. By looking at

the window, you can see the amount of memory which is used by your program.


39/47

7.3. Flash ProgrammingPROGISP is a way for, in system programming of micro controllers in controlled way.

Its development credit goes to Chi Feng Technology Co., Ltd, which engages in the design of

embedded systems products, sharing and free software developing. PROGISP ver1.68 supports for nearly 110 CPUs with on board by default fuse bits selection for

every controller. Friendly user interface with required graphics.Step 1:Open the tool


40/47

Step 2:Selecting the fuse bits and click on write button.

Step 3:Click on Erase


41/47

Step 4:Click on load flash

Step 5:Clink on write flash and verify flash in command mode


42/47

7.4.CODE:

Please paste u r code here


43/47

Chapter 8Results and Discussions

8.1 ResultsAssemble the circuit on the PCB as shown in Fig 5.1. After assembling the circuit on the

PCB, check it for proper connections before switching on the power supply.

The MODELING OF FUZZY LOGIC CONTROL S/M FOR CONTROLLING HOMOGENCITY OF

LIGHT INTENSITY FROM LEDconsists of a controller and LEDs both the units are working

independently and in collaboration with each other as well. The CU scans pot value and accordingly leds intensity varies .

In total, the complete system (including all the hardware components and software routines)

is working as per the initial specifications and requirements of our project. Because of the

creative nature of the design, and due to lack of time, some features could not be fine-tuned and

are not working properly. So certain aspects of the system can be modified as operational

experience is gained with it. As the users work with the system, they develop various new ideas

for the development and enhancement of the project


44/47

8.2 Conclusion

The implementation of MODELLIMG OF FUZZY LOGIC CONTROL S/M FOR

CONTROLLING HOMOGENCITY OF LIGHT INTENSITY FROM LED is done

successfully. The communication is properly done without any interference between different

modules in the design. Design is done to meet all the specifications and requirements. Software

tools like AVR STUDIO, PROGISP to dump the source code into the microcontroller, Proteus

Professional is used for the schematic diagram have been used to develop the software code

before realizing the hardware.

The performance of the system is more efficient. Reading the Data and verifying the

information and perform the specified task is the main job of the microcontroller. The

mechanism is controlled by the microcontroller.

Circuit is implemented in Proteus Professional and implemented on the microcontroller

board. The performance has been verified both in software simulator and hardware design. The

total circuit is completely verified functionally and is following the application software. It can

be concluded that the design implemented in the present work provide portability, flexibility and

the data transmission is also done with low power consumption.

8.3. Advantages Cost effective Low power consumption It is economical Less manpower required


45/47

8.4 Applications

This project can be used as security for POWER SAVING. Safety for our people. Easily detects temperature. Can also be used other types of system which requires high attention.


46/47

CHAPTER 9FUTURE SCOPE

Directly Displays the intensity value


47/47

CHAPTER 10REFERENCES

1. http://www.aimglobal.org/technologies/rfid/what_is_rfid.asp

2. http://www.rfidjournal.com/faq

3. http://www.technovelgy.com/ct/Technology-Article.asp

4. http://www.perada.eu/documents/articles-perspectives/an-introduction-to-rfid-

technology.pdf

5. http://csrc.nist.gov/publications/nistpubs/800-98/SP800-98_RFID-2007.pdf

6. www.ieee.org

7. http://www.zntu.edu.ua/base/lection/rpf/lib/zhzh03/8051_tutorial.pdf

8.

http://www.taltech.com/TALtech_web/resources/intro-sc.html

9. http://focus.ti.com/lit/ds/symlink/max232.pdf

10.http://www.kmitl.ac.th/~kswichit/89prog/index.html

11.http://www.microdigitaled.com/8051/Software
http://www.rfidjournal.com/faqhttp://www.rfidjournal.com/faqhttp://www.technovelgy.com/ct/Technology-Article.asphttp://www.technovelgy.com/ct/Technology-Article.asphttp://csrc.nist.gov/publications/nistpubs/800-98/SP800-98_RFID-2007.pdfhttp://csrc.nist.gov/publications/nistpubs/800-98/SP800-98_RFID-2007.pdfhttp://www.ieee.org/http://www.ieee.org/http://www.zntu.edu.ua/base/lection/rpf/lib/zhzh03/8051_tutorial.pdfhttp://www.zntu.edu.ua/base/lection/rpf/lib/zhzh03/8051_tutorial.pdfhttp://www.taltech.com/TALtech_web/resources/intro-sc.htmlhttp://www.taltech.com/TALtech_web/resources/intro-sc.htmlhttp://www.kmitl.ac.th/~kswichit/89prog/index.htmlhttp://www.kmitl.ac.th/~kswichit/89prog/index.htmlhttp://www.kmitl.ac.th/~kswichit/89prog/index.htmlhttp://www.kmitl.ac.th/~kswichit/89prog/index.htmlhttp://www.kmitl.ac.th/~kswichit/89prog/index.htmlhttp://www.taltech.com/TALtech_web/resources/intro-sc.htmlhttp://www.taltech.com/TALtech_web/resources/intro-sc.htmlhttp://www.zntu.edu.ua/base/lection/rpf/lib/zhzh03/8051_tutorial.pdfhttp://www.ieee.org/http://www.ieee.org/http://csrc.nist.gov/publications/nistpubs/800-98/SP800-98_RFID-2007.pdfhttp://csrc.nist.gov/publications/nistpubs/800-98/SP800-98_RFID-2007.pdfhttp://www.technovelgy.com/ct/Technology-Article.asphttp://www.technovelgy.com/ct/Technology-Article.asphttp://www.rfidjournal.com/faqhttp://www.rfidjournal.com/faq

Documents

DMODELING OF FUZZY LOGIC CONTROL S/M FOR CONTROLLING HOMOGENCITY OF LIGHT INTENSITY FROM LEDoc