DIVA System 110131

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DIVA ASICDIVA ASIC

TABLE OF CONTENT

ASIC Block Diagram ......................................................................................................................................................2

ASIC Detailed Block Diagram .......................................................................................................................................3

ASIC Pinout .....................................................................................................................................................................6

Data Link Layer and Microprocessor External Interfaces .........................................................................................7

About the NCR ................................................................................................................................................................8

Evaluation Board Block Diagram ............................................................................................................................... 10

Test Bed Block Diagram ...............................................................................................................................................11

DVB-RCS Operating Modes ........................................................................................................................................12

DVB-S2 Operating Modes ............................................................................................................................................14

Data Link Layer Considerations ................................................................................................................................. 15

Other Data .....................................................................................................................................................................16

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ASIC Block Diagram

DVB-S2

Physical Layer

(Receiver)

S2PLTest

DVB-RCS

Physical Layer

(Transmitter)

DVB-S2

Data Link Layer

ARM9 &Data/Prog Cache

32.768MHz

DVB-S2

DLCoProc

S2DLTest

DVB-RCS

Data Link LayerARM9 &

Data/Prog Cache

DualPort

Memory

Register

Bank

Register

Bank

Register

Bank

RxOut

Register

Bank

S2DLInpS2PLOut

SlaveMicro

Interface

RxInp

CKInp

TxInp

Memory

& I/F

M&C

Bus

S2DLOut

RCSDLOutRCSPLInp

TxOut

RCSPLTest RCSDLTest

Buffer

Memory

BufferMemory

DVB-RCSDLCoProc

Memory

& I/F

DIV

6

40.96MHzEN

ITCM

Boot PM

ITCM

Boot PM

ARMData Bus

ARMInstr Bus

ARM

Instr Bus

PLL

36/4

243MHz

DIV

9

NCRCKInp

27MHz

DIV

NCRCKOut

245.76MHz

Master Clock

JTAG1

JTAG2

ParPort

RCSDLInp

NCR

MicroProces

sor&USB

Interface

USB

Interface

Service

Clock

USB/Micro

SelectorPLL

16/10

RST

DIV

12

POR

393.216MHz

27.307MHz

ARMData Bus

ParPort

NCRTrig

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ASIC Detailed Block Diagram

ASIC

Top

ASIC PAD

Command

Manager

Clocks

Generator

28/ cm_addr

16 / cm_csb

cm_rdb

cm_wrb

cm_ata_outUSB

Controller

Micro

interface

28 / prog_addr

32 /prog_data_out

prog_rdb

prog_wrb

28/ mif_addr

16 / mif_csbmif_rdb

mif_wrb

mif_data_out

prog_dvb_s2_rx_data_out

POR

rstb ServiceClock

60 MHz

ADC

Clock245,76

CSb

Decoder16 / prog_csb

prog_dvb_rcs_tx_data_out

prog_dvb_s2_ll_data_out

prog_dvb_rcs_ll_data_out

prog_asic_data_out

USB

IF8+4

SlaveMicroIF16+4

USB/Micro Sel

NCR_ck inp

27 MHz

NCR_ckout

27,307MHz

prog_data_in

ASIC PAD level section

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DVB-S2

Receiver

TOP

ASIC Top RegisterAnalyzers

DVB-RCS

Transmitter

TOP

DVB-S2

DLL

(ARM)

DVB-RCS

DLL

(ARM)

TOP

S2_DL_Out 8+1+1 S2_DL_inp 8+1+1

Rx_inp

24x2

Tx_out24x2

Rcs_pl_inp 4+3

DVB-RCSDL CoPro

DVB-S2

DL CoPro

S 2_DL _t esl 8+ 3 S 2_D L_ out 8 +3

Memory

IF

RX

ou

t16+5

MemoryIF

T

Xinp8+4

Rcs_dl_out 4+3 Rcs_dl_test 4+3 Rcs_dl_inp 4+3

Jtag221

Jtag121

S2_DL_test 8+3

DVB-RCS

DLL

IF

Rcs_pl_test 8+3

prog_dvb_s2_ll_data_out

prog_dvb_rcs_ll_data_out

prog_dvb_rcs_tx_data_out

prog_dvb_s2_rx_data_out

32/prog_data_inprog_rdbprog_wrb

28 / prog_addr16 / prog_csb

DVB-S2

DLL TOP

DVB-RCS

DLL TOP

ASIC TOP level Section

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OutputInterface

DVB-S2Demodulator

DVB-S2Soft

Demodulator

DVB-S2LDPC

Decoder

DVB-S2BCH

Decoder

InternalFER

Meter

Rx_inp S2_pl_out

Analyzers

Registers

Clk_dem1

Clk_dem2

service_clock

To all

modules

Clk_soft_dem

Clk_ldpc_dec

Clk_bch_dec

ConfigurationROM (2kx8)

DVB-S2 Top level Section

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ASIC Pinout

Signal

Name

Number

of PinsProtocol

Frequenc

y

(MHz)

Function Notes

RXInp 48 Parallel Differential 245,760 I/Q ADC Input

S2PLTest 11 Parallel DVB-S2 Physical Layer Test Pins ASIC IOs to be used for debugging (Test MUX: 8 data, 3 cntr)

S2PLOut 10 Serial Framed 44,236 DVB-S2 Physical Layer Output ASIC Out to be used for replacing functions (8 data, Clock, Data Valid)

S2DLInp 10 Serial Framed 44,236 DVB-S2 Data Link Layer Input ASIC Inp to be used for replacing functions (8 data, Clock, Data Valid)

S2DLTest 11 Parallel DVB-S2 Data Link Layer Test Pins ASIC IOs to be used for debugging (Test MUX: 8 data, 3 cntr)

S2DLOut 10 Serial Framed 44,236 DVB-S2 Data Link Layer Output ASIC Out Synch (to drive an external slave: 8 data, Clock, Data Valid)

RXOut 22 Serial Framed 22,118 DVB-S2 Proprietary Receiver Output ASIC Out Async (to be read by an external processor: 16 data, 6 cntr)

MicroBus 20 Parallel ASIC Control & Monitoring ASIC Vs Microprocessor Interface (16 data, 4 cntr)

TxInp 12 Serial Framed 0,405 DVB-RCS Proprietary Transmitter InputASIC Inp Async ( to be written by external processor: 8 data to support DMA, 4 cntr)

RCSDLInp 10 Serial Framed 0,405 DVB-RCS Data Link Layer Input ASIC Inp Synch ( to drive an external slave for gett ing data: 8 data, Clock, Data Valid)

RCSDLTest 11 Parallel DVB-RCS Data Link Layer Test Pins ASIC IOs to be used for debugging (Test MUX: 8 data, 3 cntr)

RCSDLOut 4 Serial Framed 3,240 DVB-RCS Data Link Layer Output ASIC Out to be used for replacing functions (1 data, Clock, Data Valid, Busy)

RCSPLInp 4 Serial Framed 3,240 DVB-RCS Physical Layer Input ASIC Inp to be used for replacing functions (1 data, Clock, Data Valid, Busy)RCSPLTest 11 Parallel DVB-RCS Physical Layer Test Pins ASIC IOs to be used for debugging (Test MUX: 8 data, 3 cntr)

TXOut 24 Parallel Differential 245,760 Real DAC Output

TXOutImag 24 Parallel Differential 245,760 Imag DAC Output

RST 1 Single Line Reset

CKInp 2 Differential 245,760 Clock Input 245.76MHz Clock

NCRCKInp 1 Single Line 27,000 NCR Clock Input 27MHz External NCR Clock

NCRCKOut 1 Single Line 27,307 NCR Clock Output 27.307MHz Internal NCR Clock

JTAG1 21 Single Line JTAG i/f ARM9 #1

JTAG2 21 Single Line JTAG i/f ARM9 #2

USB 12 Parallel ASIC Control & Monitoring ASIC Vs USB Interface (8 data, 4 cntr)

CKSrv 1 Single Line 60,000 Service Clock for USB Interface

USBMSEL 1 Single Line USB/Micro Selector To be driven by an HW Jumper

NCRTrig 1 Single Line External NCR Trigger Substitutes the internal NCR comparator out in case of failure (configurable by ext proc)

Total 304

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Data Link Layer and Microprocessor External Interfaces(a seguito della riunione interna del 26.10.2010 e successive aggiornamenti)

S2DLOut: Master Output

Pins Direction Num of Bits Meaning

Data Output 8 Data Bus

CK Output 1 Clock

DV Output 1 Data Valid

RXOut: Slave Output (supporting DMA mode)

Pins Direction Num of Bits Meaning Comments

Data Output 16 Data Bus *) INT a fronte di una quantit di bytes programmata dallesterno

attraverso linterfaccia uP su un control register(che comunque deve essere caricato con un valore di default al reset)

**) in caso di overflow lARM interno deve segnalarlo su uno status register

leggibile attraverso linterfaccia uP;

lARM deve quindi scartare la frame in overflow (compresa la parte gi inserita nella FIFO);

CK Input 1 Clock

OE Input 1 Output Enable (3-state control)

RD Input 1 Read

EF Output 1 Empty Flag

INT Output 1 Interrupt Request

CS Input 1 Chip Select

MicroBus: Slave I/OPins Direction Num of Bits Meaning

Data Input/Output 16 Address/Data Bus


ALE Input 1 Address Latch Enable

RD Input 1 Read (3-state control)

WR Input 1 Write

RCSDLInp: Master Input

Pins Direction Num of Bits Meaning

Data Input 8 Data Bus

CK Output 1 Clock

DV Output 1 Data Valid

TXInp: Slave Input (supporting DMA mode)

Pins Direction Num of Bits Meaning Comments

Data Input 8 Data Bus *) FF disponibile in lettura allARM esterno su un registro

scritto dallARM interno;CK Input 1 Clock

WR Input 1 Write

EF Output 1 Full Flag


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About the NCR

NCR Re-Stamping (at GS side): As required by the standard the NCR value has to be inserted in the PCR field of a MPEG packet. This implies calculating the CRC of the packet after the NCR

insertion. In order to avoid the (i) de-capsulation; (ii) CRC re-computing; (iii) re-capsulation and (iv) CRC insertion in the next MPEG packet (as suggested by the standard) at Physical Layer level

this insertion has to be made at Data Link Layer level. The mechanism shall be based on the following steps:

(i) the Physical Layer (DVB-S2 Transmitter) provides a SOF signal back to its Data Link Layer; the SOF is obtained at a level of the transmitting chain where the signal is free of timing

jitter;(ii) the SOF signal continuously samples the master clock (a counter clocked at 27MHz), located in the Data Link Layer, making available to the encapsulator a value each frame;

(iii) an interrupt generator, located at the Data Link Layer, provides an interrupt approximately each 40ms (NCR transmission rate);

(iv) at each interrupt the encapsulator inserts the NCR in the PCR field of the current MPEG packet unless the packet is already filled without room for this value; in this last case the

NCR is inserted in the next MPEG packet, at its end, exploiting the most recent value sampled by the SOF; this guarantees that the NCR value is inserted always exactly after two

frames compared with the frame which had generated the SOF (this delay constant and it is due to the physical layer processing);(v) if no current packet is in the queue, the Data Link Layer creates a dedicated MPEG packet only containing the NCR information;

(vi) the extension to the multiple stream case is obtained inserting a NCR value in the first MPEG packet belonging to different streams sent after a given 40msec interrupt; if a givenstream has no packet to transmit a dedicated packet for that stream is created to sent the NCR;

SOF

DetectorConstantDelay Proc

To DACDVB-S2

Phy-Layer

DVB-S2

Encaps

NCR

Master

Counter

27MHz

Register

Register

FIFO

40ms

Interrupt

Generator

From

Scheduler

Data Link Layer Physical Layer

NCR Extraction (at UT side): The MPEG packet containing the NCR value is extracted by the Data Link Layer of the DVB-S2 Receiver at the UT side and provided to the DVB-RCS

Transmitter together with a double correction: (i) a on-line estimation of the computation delay required to process the incoming frame measured from the correlator up to the write commandtoward the local clock accommodated into the DVB-RCS Transmitter; (ii) a off-line compensation, programmable from outside (e.g. external microprocessor) to adjust the offset of the

computational delay. The Mechanism is shown in the next figure.

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Output

Interface

DVB-S2

Demodulator

DVB-S2

Soft

Demodulator

DVB-S2

LDPC

Decoder

DVB-S2

BCH

Decoder

Internal

FER

Meter

From

ADC

To

UpperLayer

DelayCounter

FIFO

Start_of_frame

Counter value

wr

Data

in

NCR

Field

extractor

rd

Data

out+

NCR Delay

+

Static

Delay

Compensation

table

NCR Delay

NCR delay compensator

DVB-S2 receiver

Mod cod

NCR clock

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Evaluation Board Block Diagram

Note: the 18.01.11 it has been decided (Rossini, Cecili, Chiassarini) to reduce the complexity of the EVB collapsing: (i) two Physical Layer FPGAs into a single

device (FPGA Altera); (ii) two Data Link Layer FPGAs into a single device (FPGA Xilinx); (iii) two ARMs into a single device. It has also been decided to

remove the second DAC.

USB I/F

Ethernet

I/F #1

Ethernet

I/F #4

ADC

I/QS

amples

@24

5.76MHz

OSC

245.76

MHz

I/QL band

to BB

Converter

DVB-S2 RX

Physical Layer

( Altera FPGA)

S2 RX DLink Layer

RCS RX Phy Layer( Xilinx FPGA)(with PowerPC)

PLL

RCS DLink Layer

( Xilinx FPGA)(with PowerPC)

DVB-RCS TX

or DVB-S2 TX

Physical Layer

( Altera FPGA)

DACBB to

L Band

Converter

PLL

RealorI/QSamples

@2

45.76MHz

AnalogueFrontEnd

ASIC

S2PLTest

S2DLTest

RxOut

S2DLInp

S2PLOut

Slave MicroInterface

RxInp

CKInp

TxInp

S2DLOut

RCSDLOut

RCSPLInp

Tx

Out

RCSPLTest

RCSDLTest

NCRCKInp

NCRCKOut

JTAG2

JTAG1

RCSDLInp

Test MUXConnector

JTAG

Conn D

ecodingLogic&

ARMsDataExchangeMemory

(LowCostFP

GA#2)

ARM&

Memories

JT

AG

Conn

Ethernet

I/F #2

Ethernet

I/F #3

DataSwitching

Logic&

RST/CKManager

(LowCostFP

GA#1)

ADCI/Q

L band to BB

Converter

I/Q

PLL

DVB-RCS

RF Inp

DVB-S2

RF Inp

DVB-RCS

RF Out

USB/MicroSel

USB

CKSrv

Jmpr

Test MUXConnector

OtherFPGAs

OtherFPGAs

OtherFPGAs

OtherFPGAs

RST

NCRTrig

(LowCost

FPGA #2)

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Test Bed Block Diagram

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DVB-RCS Operating Modes

OperatingMode

Packet

Length C

oding

Rates

CodedP

acket

Length

Numo

f

Packets P

ayload

Bits

Bitsper

Symb P

ayloa

d

Symb P

re-amble

Symb P

ost-am

ble

Symb

PilotSymb

PartialT

otal

Symb

GardSymb

ExtraSymb

Total

Symb

BurstDuratio

n

at128Ksps

BurstDuration

at512Ksps

BurstDuration

at2048Ksp

s

BitRateat

128Ksps

BitRateat

512Ksps

BitRateat

2048Ksps

Burstsp

erFrame

at128Ksps

Burstsp

erFrame

at512Ksps

BurstsperFrame

at2048Ksps

Overhead

PilotsGap

bits bits bits bits sym sym sym sym sym sym sym sym msec msec msec bps bps bps % sym

MPEG #1 1504 1/2 3008 1 3008 2 1504 195 0 0 1699 6 32 1737 13.570 3.393 0.8481.11E+0

5

4.43E+0

5

1.77E+0

6 2 8 32 13.42

MPEG #2 1504 3/4 2006 1 2006 2 1003 1 45 0 0 1148 6 4 1158 9.047 2.262 0.5651.66E+0

5

6.65E+0

5

2.66E+0

6 3 12 48 13.39

MPEG #3 1504 4/5 1880 1 1880 2 940 1 45 0 0 1085 6 67 1158 9.047 2.262 0.5651.66E+0

56.65E+0

52.66E+0

6 3 12 48 18.83

MPEG #4 1504 6/7 1756 1 1756 2 878 145 0 0 1023 6 129 1158 9.047 2.262 0.5651.66E+0

5

6.65E+0

5

2.66E+0

6 3 12 48 24.18

ATM1 #1 424 1/2 848 1 848 2 424 85 0 0 509 6 31 546 4.266 1.066 0.2679.94E+0

4

3.98E+0

5

1.59E+0

6 2 8 32 22.35

ATM1 #2 424 3/4 566 1 566 2 283 70 0 0 353 6 5 364 2.844 0.711 0.1781.49E+0

5

5.96E+0

5

2.39E+0

6 3 12 48 22.26

ATM1 #3 424 4/5 530 1 530 2 265 70 0 0 335 6 23 364 2.844 0.711 0.1781.49E+0

5

5.96E+0

5

2.39E+0

6 3 12 48 27.20

ATM1 #4 424 6/7 496 1 496 2 248 70 0 0 318 6 40 364 2.844 0.711 0.1781.49E+0

5

5.96E+0

5

2.39E+0

6 3 12 48 31.87

ATM4 #1 424 1/2 848 4 3392 2 1696 215 0 0 1911 6 48 1965 15.352 3.838 0.9591.10E+0

5

4.42E+0

5

1.77E+0

6 2 8 32 13.69

ATM4 #2 424 3/4 566 4 2264 2 1132 155 0 0 1287 6 17 1310 10.234 2.559 0.6401.66E+0

5

6.63E+0

5

2.65E+0

6 3 12 48 13.59

ATM4 #3 424 4/5 530 4 2120 2 1060 155 0 0 1215 6 89 1310 10.234 2.559 0.6401.66E+0

5

6.63E+0

5

2.65E+0

6 3 12 48 19.09

ATM4 #4 424 6/7 496 4 1984 2 992 155 0 0 1147 6 157 1310 10.234 2.559 0.6401.66E+0

5

6.63E+0

5

2.65E+0

6 3 12 48 24.28

ENH-S2 488 1/2 976 1 976 2 488 40 5 54 587 6 7 600 4.688 1.172 0.2931.04E+0

5

4.16E+0

5

1.67E+0

6 6 24 96 18.67 9 .17

ENH-S3 656 2/3 984 1 984 2 492 40 5 54 591 6 3 600 4.688 1.172 0.2931.40E+0

5

5.60E+0

5

2.24E+0

6 6 24 96 18.00 9 .17

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ENH-S4 736 3/4 982 1 982 2 491 40 5 54 590 6 4 600 4.688 1.172 0.2931.57E+0

5

6.28E+0

5

2.51E+0

6 6 24 96 18.17 9 .17

ENH-S6 880 6/7 1028 1 1028 2 5 14 40 5 35 5 94 6 0 6 00 4 .688 1.172 0.2931.88E+0

5

7.51E+0

5

3.00E+0

6 6 24 96 14.34 14.69

ENH-S7-8PSK 928 2/3 1392 1 1392 3 464 40 5 51 560 6 34 6 00 4 .688 1.172 0.2931.98E+0

5

7.92E+0

5

3.17E+0

6 6 24 96 22.67 9 .77

ENH-L2 1568 1/2 3136 1 3136 2 1568 40 5 174 1787 6 7 1800 14.063 3.516 0.8791.12E+0

5

4.46E+0

5

1.78E+0

6 2 8 32 12.89 9.06

ENH-L3 2096 2/3 3144 1 3144 2 1572 40 5 174 1791 6 3 1800 14.063 3.516 0.8791.49E+0

5

5.96E+0

5

2.38E+0

6 2 8 32 12.67 9.06

ENH-L4 2360 3/4 3148 1 3148 2 1574 40 5 174 1793 6 1 1800 14.063 3.516 0.8791.68E+0

5

6.71E+0

5

2.69E+0

6 2 8 32 12.56 9.06

ENH-L6 2712 6/7 3164 1 3164 2 1582 40 5 158 1785 6 9 1800 14.063 3.516 0.8791.93E+0

5

7.71E+0

5

3.09E+0

6 2 8 32 12.12 10.07

ENH-L7-8PSK 2848 2/3 4272 1 4272 3 1424 40 5 158 1627 6 167 1800 14.063 3.516 0.8792.03E+0

5

8.10E+0

5

3.24E+0

6 2 8 32 20.89 10.07

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DVB-S2 Operating Modes

Clock (MHz) 393.216

OperatingMode

MappingFactor

CodeRate

SpectralEfficiency

Max AllowedBaud Rate

Max AllowedBit Rate(Mbps)

QPSK 1/4 2 0.25 0.50 100.00 50.00

QPSK 1/3 2 0.33 0.67 100.00 66.67

QPSK 2/5 2 0.40 0.80 100.00 80.00

QPSK 1/2 2 0.50 1.00 100.00 100.00

QPSK 3/5 2 0.60 1.20 100.00 120.00

QPSK 2/3 2 0.67 1.33 100.00 133.33

QPSK 3/4 2 0.75 1.50 100.00 150.00

QPSK 4/5 2 0.80 1.60 100.00 160.00

QPSK 5/6 2 0.83 1.67 100.00 166.67

QPSK 8/9 2 0.89 1.78 100.00 177.78

QPSK 9/10 2 0.90 1.80 100.00 180.00

8PSK 3/5 3 0.60 1.80 100.00 180.008PSK 2/3 3 0.67 2.00 100.00 200.00

8PSK 3/4 3 0.75 2.25 100.00 225.00

8PSK 5/6 3 0.83 2.50 100.00 250.00

8PSK 8/9 3 0.89 2.67 100.00 266.67

8PSK 9/10 3 0.90 2.70 100.00 270.00

16APSK 2/3 4 0.67 2.67 98.30 262.14

16APSK 3/4 4 0.75 3.00 98.30 294.91

16APSK 4/5 4 0.80 3.20 98.30 314.57

16APSK 5/6 4 0.83 3.33 98.30 327.68

16APSK 8/9 4 0.89 3.56 98.30 349.53

16APSK 9/10 4 0.90 3.60 98.30 353.89

32APSK 3/4 5 0.75 3.75 78.64 294.91

32APSK 4/5 5 0.80 4.00 78.64 314.57

32APSK 5/6 5 0.83 4.17 78.64 327.68

32APSK 8/9 5 0.89 4.44 78.64 349.53

32APSK 9/10 5 0.90 4.50 78.64 353.89

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Data Link Layer Considerations

Embedded Processors: The comparison has been made on the basis of a benchmark achieved through measuring the performances of the processors in terms of DMIPS (i.e. "Dhrystone VAX

MIPs"). The industry adopted the VAX 11/780 as the reference 1 MIP machine. The benchmark is calculated by measuring the number of Dhrystones per second for the system, and then dividing

that figure by the number of Dhrystones per second achieved by the reference machine. So "80 MIPS" means "80 Dhrystone VAX MIPS", which means 80 times faster than a VAX 11/780.The reason for comparing against a reference machine is that it avoids the need to argue about differences in instruction sets. RISC processors tend to have lots of simple instructions. CISC

machines like x86 and VAX tend to have fewer, more complex instructions. If you just counted the number of instructions per second of a machine directly, then machines with simple instructions

would get higher instructions-per-second results, even though it would not be telling you whether it gets the job done any faster. By comparing how fast a machine gets a given piece of work done

against how fast other machines get that piece of work done, the question of the different instruction sets is avoided. There are two different versions of the Dhrystone benchmark commonly

quoted (i) Dhrystone 1.1 and (ii) Dhrystone 2.1.

Processor Processor Type Device Family Speed (MHz) DMIPS DMIPS/MHz Source References

ARM922T Hard Excalibur 200 210 1.05 (1) (1) Bryan H. Fletcher (Memec):

FPGA Embedded Processors

Revealing True System PerformanceSan Diego, Californiawww.memec.com

(2) ARM Limited: AN93

Benchmarking with ARMulator

March 2002

(3) Virtex-5 Family Data Sheet

NIOS Soft Stratix-II 180 Not Reported - (1)

Nios II Soft Stratix-II Not Reported 200 - (1)

Nios II Soft Cyclone-II Not Reported 100 - (1)

PowerPC 405 Hard Virtex-4 450 680 1.51 (1)

MicroBlaze Soft Virtex-II Pro 150 123 0.82 (1)

MicroBlaze Soft Spartan-3 85 65 0.76 (1)

PowerPC 440 Hard Virtex-5 550 1000 1.82 (3)

ARM7 Hard - Not Reported Not Reported 0.90 (2)

ARM9 Hard - Not Reported Not Reported 1.10 (2)

DVB-S2: The upper layer worst case for 100Mbaud is given for the operating mode 16APSK with code rate 5/6. In this case the demodulated bit rate is:

100( ) 4( 16) 5 / 6( ) 333.33 Rb Mbaud APSK CodeRate Mbps= =

The current implementation of the DVB-S2 Data Link Layer (Decapsulator) is based on a XILINX PowerPC working at 200MHz to process 150Mbps with the same operating mode and code rate.The required processing capability is then C=200/150=1.33Hz/bit. Therefore the clock speed required to implement a 100Mbaud receiver on the same processor is:

61.33 333.33 10 443.33CPU bClock C R MHz = = =

Since a Dhrystone benchmark for the XILINX PowerPC and for the ARM9 devices provides almost the same performances (1.1DMIPS), the same clock is also necessary for the ARM9 processor.

This clock is not available on the ASIC. The system performances shall be reduced to 50Mbps which requires half clock speed:

100 167 222CPU Rs Mbaud Rb Mbps Clock MHz = = =

A possible solution to face the 100Mbaud mode is to select the PIDs belonging to the wanted used and to elaborate only them. This is not simple being the PID information encapsulated andtherefore it is necessary to decapsulate before. A suitable HW algorithm shall be studied to achieve this selection before the decapsulator.

DVB-RCS: The current implementation of the data link layer (scheduler and encapsulator) is based on two XILINX PowerPC working at 300MHz and sharing a bus working at 100MHz. Their

overall efficiency is therefore limited by the bus frequency and can be considered less than 300MHz.
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Other Data

Evaluation Board

The ALTERA FPGA used for the DVB-S2 receiver is: EP4SGX230. The Evaluation Board can accommodate two of these FPGA for the two physical layers.

The XILINX FPGA, candidate for the EV is the XC5VFX100T (or 130, or 200) which accommodate two power PC to be used for the upper layers.

The monitoring and command interface (test multiplexers and configuration) can be done connecting the EV to and external PC through USB ports. These ports can be implemented on the EV

using the FTDI devices like FT2232 which manage the USB protocols providing internally a parallel interface.

ASIC Prices

From Chiassarini phone call to ST/Sanfilippo

Wafer: 5Keuro (about 200 devices, => 25euro/device)

For quantities (e.g. 1000 pieces): 5..10euro/device

Packaging: 3..5euro

Total: 8..15euro/packageddevice

Documents

DIVA System 110131