Distributed Power System SB3000 ... - Rockwell Automation · Distributed Power System Overview S-3005 Distributed Power System Universal Drive Controller Module S-3007 Distributed

Instruction Manual

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The information in this users manual is subject to change without notice.

Ethernet™ is a trademark of Xerox Corporation.AutoMax™ is a trademark of Rockwell Automation©1998 Rockwell International Corporation

Throughout this manual, the following notes are used to alert you to safety considerations:

Important: Identifies information that is critical for successful application and understanding of the product.

!ATTENTION: Identifies information about practices or circumstances that can lead to personal injury or death, property damage, or economic loss.

!ATTENTION: Only qualified personnel familiar with the construction and operation of this equipment and the hazards involved should install, adjust, operate, or service this equipment. Read and understand this manual and other applicable manuals in their entirety before proceeding. Failure to observe this precaution could result in severe bodily injury or loss of life.

ATTENTION: DC bus capacitors retain hazardous voltages after input power has been disconnected. After disconnecting input power, wait ten (10) minutes for the DC bus capacitors to discharge. Open the cabinet doors and check the voltage across the DC bus bars, 347/1247 A,B,C (+ bus) and 345/1145 A,B,C (- bus), with an external voltmeter to ensure the DC bus capacitors are discharged before touching any internal components. Failure to observe this precaution could result in severe bodily injury or loss of life.

ATTENTION: Do not use the run permissive input on the Resolver & Drive I/O module as a means of shutting off the SB300 synchronous Rectifier. Turning this input off only stops power devices from firing. Residual voltage on the bus capacitors will continue to feed the load inverters until the voltage dissipates. Failure to observe this precaution could result in bodily injury.

ATTENTION: Only qualified Rockwell personnel or other trained personnel who understand the potential hazards involved may make modifications to the rack configuration, variable configuration, and application tasks. Any modifications may result in uncontrolled machine operation. Failure to observe this precaution could result in damage to equipment and bodily injury.

ATTENTION: Registers and bits in the UDC module that are described as “read only” or for “system use only” must not be written to by the user. Writing to these registers and bits may result in improper system operation. Failure to observe this precaution could result in bodily injury.

ATTENTION: The pre-charge contactor for the SB3000 must be closed and the voltage loop must be on (register 200/1200, bit 0) before any load inverters can be put into run. If the SB3000 pre-charge contactor is not closed, running a load inverter will burn up the pre-charge resistors. Failure to observe this precaution could result in damage to, or destruction of, the equipment.

Table of Contents I

CONTENTS

Chapter 1 Introduction

Chapter 2 Configuring the UDC Module, Regulator Type, and Parameters2.1 Adding a UDC Module..................................................................................... 2-12.2 Entering the Drive Parameters ........................................................................ 2-2

2.2.1 Power Module Parameter Entry ............................................................ 2-42.2.2 PMI Meter Port Selection ...................................................................... 2-6

2.3 Generating the Drive Parameter Files and Printing Drive Parameters ............ 2-8

Chapter 3 Configuring the UDC Module’s Registers3.1 Register and Bit Reference Conventions Used in this Manual ........................ 3-33.2 Rail I/O Port Registers (Registers 0-23) .......................................................... 3-63.3 UDC/PMI Communication Status Registers (Registers 80-89/1080-1089) ..... 3-93.4 Command Registers (Registers 100-199/1100-1199)................................... 3-173.5 Feedback Registers (Registers 200-299/1200-1299).................................... 3-223.6 Application Registers (Registers 300-599, Every Scan)

(Registers 1300-1599, Every Nth Scan)........................................................ 3-483.7 UDC Module Test I/O Registers (Registers 1000-1017) ............................... 3-51

3.7.1 UDC Module Test Switch Inputs Register (Register 1000) ................. 3-513.7.2 UDC Module Meter Port Setup Registers (Registers 1000-1017)....... 3-53

3.7.2.1 Resolution of Meter Port Data............................................... 3-543.8 Interrupt Status and Control Registers (Registers 2000-2047) ..................... 3-59

Chapter 4 Application Programming for DPS Drive Control4.1 AutoMax Tasks................................................................................................ 4-14.2 UDC Tasks ...................................................................................................... 4-1

4.2.1 Typical Structure of a UDC Task........................................................... 4-34.2.2 Local Tunable Variables........................................................................ 4-6

4.2.2.1 Calculating Local Tunable Values........................................... 4-74.2.3 UDC/PMI Task Communication ............................................................ 4-7

4.3 AutoMax Processor Task and UDC Task Coordination .................................. 4-9

Chapter 5 On-Line Operation5.1 Loading the UDC Module’s Operating System................................................ 5-15.2 Loading the Drive Parameters and UDC Tasks .............................................. 5-15.3 Running, Stopping, and Deleting UDC Application Tasks............................... 5-25.4 UDC Information Log and Error Log................................................................ 5-3

II SB3000 Drive Configuration and Programming

Appendix A SB3000 Drive Register Reference ........................................................................... A-1

Appendix B SB3000 Local Tunable Variables............................................................................. B-1

Appendix C SB3000 Control Algorithm........................................................................................ C-1

Appendix D Status of Data in the AutoMax Rack Aftera STOP_ALL Command or STOP_ALL Fault .......................................................... D-1

Appendix E SB3000 Pre-Charge Sequencing............................................................................. E-1

Appendix F Enabling the Voltage Loop ....................................................................................... F-1

Appendix G Performing the Bridge Test ......................................................................................G-1

Appendix H Discharging the DC Bus........................................................................................... H-1

Index ........................................................................................................................... Index-1

Table of Contents III

List of Figures

Figure 2.1 – Power Module Parameter Entry Screen............................................... 2-4Figure 2.2 – PMI Meter Port Selection Screen ......................................................... 2-6

Figure 3.1 – UDC Task Scan.................................................................................. 3-48Figure 3.2 – Nth Scan Interrupts............................................................................. 3-50

Figure 4.1 – UDC Task Scan.................................................................................... 4-2Figure 4.2 – Recommended Run Permissive Logic ................................................. 4-9Figure 4.3 – Data/Time Flow for UDC Module and PMI ......................................... 4-10

IV SB3000 Drive Configuration and Programming

Table of Contents V

List of Tables

Table 1.1 – Related Publications .............................................................................. 1-1

Table 2.1 – Restricted Drive Type Combinations ..................................................... 2-2Table 2.2 – Supported SB3000 Power Modules....................................................... 2-5Table 2.3 – PMI Meter Port Parameters ................................................................... 2-7

Table 3.1 – UDC Module Configuration Views and Registers .................................. 3-4Table 3.2 – UDC Module Dual Port Memory Register Organization. ....................... 3-5Table 3.3 – Rail I/O Port Registers ........................................................................... 3-7Table 3.4 – Fault Register and Check Bit Fault Counter Register

Usage for a Digital I/O Rail or 4-Output Analog Rail Module ................ 3-7Table 3.5 – Fault Register and Check Bit Fault Counter Register

Usage for a Digital I/O Rail or 4-Input Analog Rail Module................... 3-8Table 3.6 – Fault Register and Check Bit Fault Counter Register

Usage for a 2-Output/2-Input Analog Rail Module ................................ 3-8Table 3.7 – UDC Module Meter Port Setup Registers............................................ 3-53

VI SB3000 Drive Configuration and Programming

Introduction 1-1

CHAPTER 1Introduction

This manual describes the configuration and programming necessary to control the SB3000 Synchronous Rectifier. SB3000 Rectifiers operate within the AutoMax™ Distributed Power System (DPS) environment. They are controlled through coordination among:

• Tasks written by the programmer for the AutoMax Processor.

• Tasks written by the programmer for the Universal Drive Controller (UDC) module.

• The control algorithm and a number of software routines executed by the Power Module Interface (PMI) regulator.

The data and commands required by the PMI operating system to carry out its functions are provided by the programmer through the AutoMax rack configuration and the UDC task. The programmer provides this information by:

• Entering the drive parameters.

• Configuring the registers in the UDC module.

• Defining the values of the pre-defined local tunables.

The AutoMax Programming Executive V3.4 (M/N 57C345, 57C346, 57C395, and 57C397) or later is required to support the SB3000 Rectifier. Beginning with V3.5 Executive software, drive regulators are sold separately. The AutoMax Programming Executive instruction manual describes the Programming Executive in detail.

This instruction manual assumes that the user is familiar with the AutoMax Programming Executive software and makes reference to it throughout. This manual does not describe specific applications of the standard hardware and software.

The user must be familiar with the other instruction manuals that describe using the SB3000 Synchronous Rectifier as part of a Distributed Power System drive. Refer to the instruction manuals listed in table 1.1 as needed.

Table 1.1 – Related Publications

DocumentDocument Part

Number

AutoMax Programming Executive J2-3102

AutoMax Executive Software Loading Instructions J2-3103

Distributed Power System Overview S-3005

Distributed Power System Universal Drive Controller Module S-3007

Distributed Power System Fiber-Optic Cabling S-3009

High Power SB3000 Power Modules (Rittal) S-3031

High Power SB3000 Power Modules (RCS) S-3043

1-2 SB3000 Drive Configuration and Programming

Additional information about using the SB3000 Synchronous Rectifier is found in the wiring diagrams, prints, and other documentation shipped with each drive system. Always consult the documentation shipped with your drive system for specific information about installing, operating, and maintaining your drive.

Configuring the UDC Module, Regulator Type, and Parameters 2-1

CHAPTER 2Configuring the UDC Module,

Regulator Type, and Parameters

The Rack Configurator application in the AutoMax Programming Executive is used to configure the modules in a rack. Using the Rack Configurator, you create a graphical representation of the actual modules in the rack. See the AutoMax Programming Executive instruction manual for more information on configuring racks.

You can access the Rack Configurator by selecting the Configure Rack option from the Rack menu of the System Configurator. An empty AutoMax rack will be displayed initially.

2.1 Adding a UDC Module

The UDC module may be placed in any slot in an AutoMax rack that contains at least one AutoMax processor module (M/N 57C430A, 57C431, or 57C435). Note that the UDC module cannot be used in a remote I/O rack. The rack does not require a Common Memory module (M/N 57C413 or 57C423) unless more than one AutoMax Processor is being used. A rack may contain up to ten UDC modules.

Some AutoMax modules, e.g., the Common Memory module and the Ethernet™ Interface module, may have an effect on the slot allocation in the rack that limits where other modules may be inserted. See the appropriate instruction manual for additional information. A UDC module may also be placed in a rack containing a set of the AutoMax drive controller modules (B/M57401, 57405, 57406, and 57408).

Use the following procedure to add a UDC module to a rack:

Step 1. Select an empty slot in the rack.

Step 2. Select Add from the Configure menu. A dialog box listing the available modules will be displayed on the screen.

Step 3. Select the UDC module.


ATTENTION: Only qualified Rockwell personnel or other trained personnel who understand the potential hazards involved may make modifications to the rack configuration. Any modifications may result in uncontrolled machine operation. Failure to observe this precaution may result in damage to equipment and bodily injury.


Step 4. Select a product type and a regulator (control) type for both drive A and drive B. See the following section for regulator selection rules. The remainder of this chapter assumes that you have selected an SB3000 voltage regulator.

Step 5. Select OK to add the UDC module to the rack and return to the Rack Configuration screen.

Rules for Configuring/Selecting Drives for the UDC Module

1. The SB3000 Synchronous Rectifier can be configured in drive A or in drive B in combination with a DPS AC drive (SA500, SA3000, or SA3100) or with no PMI attached.

2. The A and B drives do not both have to be used. You can configure only one.

3. If you select an SA3000 Parallel Inverters drive, an SD3000 (12-Pulse) drive, or an SF3000 drive for either drive A or drive B, you are restricted to the drive type combinations shown in table 2.1.

4. All other drive type combinations are allowed.

2.2 Entering the Drive Parameters

Drive parameters are application-specific data that describe your installation’s Power Modules, feedback devices, and motors. This information is loaded to the UDC module, which in turn automatically downloads it to the PMI when the two are first connected over the fiber-optic link. This information is also stored off-line with the Programming Executive. Note that the drive parameters will be retained by the UDC module during a STOP ALL fault or command to the rack.

Once a UDC module has been added to the rack, use the Zoom In command to begin entering the drive parameters. See the AutoMax Programming Executive instruction manual for more information on Zooming in and out.

Use the following procedure to enter the drive parameters. Section 2.3 describes how to load the drive parameter files when you are finished. Note that if you enter drive parameter data that is unexpected or out of range, a “warning” or “error” message will appear on the screen. A warning message indicates that the data you have just entered will be accepted by the Programming Executive, and you will be able to generate drive parameter files; however, you may experience degradation of drive performance. An error message indicates that the data you have just entered is unacceptable, and you will not be able to generate drive parameter files.

Table 2.1 – Restricted Drive Type Combinations

If you choose for Drive A . . . Then your choices for Drive B are . . .

SA3000 Parallel Inverters SA3000 Parallel Inverters Auxiliary

SD3000 (12-Pulse) SD3000 12-Pulse Auxiliary

SF3000 No PMI AttachedSD3000 (6-Pulse)SF3000


Step 1. Zoom into the UDC module. The Power Module Interface (PMI) screen will be displayed. You can also access this screen directly by double-clicking the UDC module.

This screen shows either one or two PMI diagrams, depending upon the information you previously entered. One diagram will be shown for drive A and one for drive B, if used.

Each PMI diagram will show a Flex I/O port (Port 0) and the analog or digital Flex I/O modules that are connected to the PMI. Initially, no Flex I/O is connected.

Only one drive can be selected at a time when two drives are shown on the screen:

• the Drive A option will make drive A the selected drive.

• the drive B option will make drive B the selected drive.

Entered commands will only affect the selected drive.

Step 2. If a rail is to be connected to the PMI’s rail ports, click the appropriate rail port, either 0 or 1. Select Add under the Configure menu to add the rail to the rail ports.

You can choose from the following rail devices:

The Location field can be used to identify the physical location of the I/O.

Click OK and the device will be added to the screen. If you are adding a digital I/O rail, you will need to configure the I/O modules that the rail contains. Double-click the rail to display the expanded digital I/O rail screen. To add an I/O module, select the module’s slot by moving the cursor to it and clicking it. Select the Add option from the Configure menu for a list of the available modules. Select the appropriate module and click OK. Zoom out to return to the PMI screen (Rack Configurator).

Note that you cannot attach a Local I/O Head to the PMI’s rail ports. You can, however, mix input and output modules in a Digital I/O Rail. You can also mix rail types, i.e., add both a Digital I/O Rail and an Analog Rail (rail mode only) to a PMI.

Select the Configure Variables option from the Configure menu in order to configure the variables for the attached rails. Zoom out to return to the PMI screen.

• M/N 45C001 Digital I/O Rail (J-3012)

• M/N 45C630 4-Decade Thumbwheel Switch Input Module (J-3606)

• M/N 45C631 4-Digit LED Output Module (J-3606)

• M/N 61C345 4-Channel Analog Current Input Rail (J-3689)

• M/N 61C346 4-Channel Analog Voltage Input Rail (J-3688)

• M/N 61C350 2-Channel Analog Voltage Input/Output Rail (J-3672)

• M/N 61C351 2-Channel Analog Current Input/Output Rail (J-3673)

• M/N 61C365 4-Channel Analog Current Output Rail (J-3694)

• M/N 61C366 4-Channel Analog Voltage Output Rail (J-3695)


Step 3. Use the Configure parameters option to access the Parameter Entry screens. Assuming you are configuring an SB3000 Synchronous Rectifier, you can access two screens: Power Module Data and Meter Port selection. These screens are described in detail in the following sections.

Note that the AutoMax slot number of the UDC module is shown at the top of the screens. The screens prompt for specific information depending upon the item that is being configured.

Step 4. When you have made entries for the drive parameters on all of the parameter entry screens, you should select the “Verify” option displayed at the bottom of the screen. If any of the values you entered are invalid or out of range, the parameter that is invalid will be highlighted so that you can change the value. When you have finished entering drive parameters, select “Save” to save the values to the database.

2.2.1 Power Module Parameter Entry

The Power Module Parameter Entry screen allows entry of specific information about the power system configuration, the Power Module, and the motor. See figure 2.1.

Figure 2.1 – Power Module Parameter Entry Screen

Power System Configuration

• AC Line Voltage (Volts RMS) (Range: 200V to 500V)

The AC line voltage parameter is the nominal AC RMS voltage supplying the SB3000 Synchronous Rectifier and being converted to the DC bus voltage. There is no default value. You must enter a value within the specified range.


• AC Line Frequency (Hz) (Range: 25, 50, or 60, +/- 2%)

The AC line frequency parameter is the nominal frequency being supplied to the rectifier. There is no default value. You must select one of the three values from the list.

Power Module

• Part Number

The screen displays a list of the supported SB3000 Power Modules. Selection is made based upon the current rating of the Power Module being configured. The current ratings displayed are the rated RMS currents with no overload and 40° C ambient temperature. The Power Module may be selected by part number or by the corresponding wiring diagram number. There is no default selection. A Power Module must be chosen from the list.

• Current Limit (Amps RMS)

The current limit parameter will automatically default to the Power Module rated amps. The value may be changed to any number less than the rated value.

Motor Data

• Rated Motor Voltage (Volts RMS) (208V to 575V)

Enter the rated RMS voltage of the motor(s) being controlled by the load inverter. There is no default value. The value entered must be greater than the AC Line Voltage parameter. A warning will be generated if this condition is not met.

Table 2.2 – Supported SB3000 Power Modules

Current Rating Part Number Wiring Diagram

445 Amps 101165-190S (445A @ 4KHz) W/D 30495-11 (445A @ 4KHz)

890 Amps 101165-190T (890A @ 4KHz) W/D 30495-12 (890A @ 4KHz)

1335 Amps 101165-190V (1335A @ 4KHz) W/D 30495-13 (1335A @ 4KHz)


2.2.2 PMI Meter Port Selection

PMI Meter ports 1 and 2 are dedicated to driving two standard meters supplied with the SB3000 Rectifier. Meter port 1 drives the DC bus output current meter. Meter port 2 drives the AC input current meter. Meter ports 3 and 4 are not used on standard SB3000 systems, but can be programmed to operate custom display meters. See figure 2.2.

A DC bus voltmeter is hardwired directly to the SB3000 DC bus output terminals.

Figure 2.2 – PMI Meter Port Selection Screen


The following variables are available for output on the PMI D/A ports:

Table 2.3 – PMI Meter Port Parameters

Port Not Used Vq Command (Counts)

DC Bus Voltage Reference ( Volts ) Phase Period ( Micro seconds )

DC Bus Voltage Feedback ( Volts ) Phase Error ( Counts ) (360 degrees = 1024 counts)

DC Bus Current Feedback ( Amps * 10 ) Phase Angle ( Counts ) (360 degrees = 1024 counts)

Ground Current (Amps * 10 ) User Analog Input (Counts)

AC Input Voltage Feedback ( Volts ) UDC Data Register 106)

AC Input Current Feedback (Amps * 10) Rail Port 0 Channel 0 (Counts)

VAR Feedback (Volt Amps / 1000 ) Rail Port 0 Channel 1 (Counts)

Id Command Current ( Amps * 10 ) Rail Port 0 Channel 2 (Counts)

Id Feedback Current ( Amps * 10 ) Rail Port 0 Channel 3 (Counts)

Iq Command Current ( Amps * 10 ) Rail Port 1 Channel 0 (Counts)

Iq Feedback Current ( Amps * 10 ) Rail Port 1 Channel 1 (Counts)

Derivative Component ( Volts ) Rail Port 1 Channel 2 (Counts)

Feed Forward Component ( Amps * 10 ) Rail Port 1 Channel 3 (Counts)

Vd Command (Counts )


2.3 Generating the Drive Parameter Filesand Printing Drive Parameters

When you have completed all of the drive parameter screens, you can select “Close” to leave the Parameter Entry Screens and return to the master rack diagram with the UDC module selected. Zoom out or select the Exit command from the Configure menu to return to the System Configurator.

You can generate the drive parameter files by using the steps that follow.

Step 1. From the System Configurator, access the Task Manager by selecting the Manage Tasks command from the Rack menu.

Step 2. Select the Generate Configuration command from the Commands menu.

Step 3. Check the Generate Drive Parameter Files option in the Generate Files dialog box, and then select OK.

A file containing the newly-entered drive parameters will be created. The file will be named PARAMxx.POB, where xx is the slot number of the UDC module. Note that the drive parameter files must be loaded to the rack before (or at the same time as) the UDC application tasks are loaded to the rack. Refer to the AutoMax Programming Executive instruction manual for more detailed information.

You can print the drive parameters for a UDC module you specify by using the Print command from the Rack menu in the System Configurator. Refer to the AutoMax Programming Executive instruction manual for step-by-step instructions.

Configuring the UDC Module’s Registers 3-1

CHAPTER 3Configuring the UDC Module’s Registers

The Variable Configurator application in the AutoMax Programming Executive is used to assign common variable names to the dual port memory registers on the UDC module. You can access these variable names by declaring them using the BASIC statement COMMON. The dual port memory has 2048 16-bit registers that are available to the AutoMax Processor and to the tasks that run on the UDC module.

The drive A and drive B registers that are assigned variable names will be latched into internal memory at the beginning of every scan of the UDC task to provide for a consistent context for evaluation. The UDC tasks (A and B) may be started and stopped independently of each other. At the end of the scan, the variables that have changed will be written back to the dual port memory.

Note that the dual port memory on the UDC module is treated like I/O data in terms of how the data is affected by Stop All commands and power cycling.

You can access the Variable Configurator by selecting Configure Variables from the Configure menu in the Rack Configurator. Refer to the AutoMax Programming Executive instruction manual for the procedures used to configure variables.

The sections that follow describe the registers you can configure in each view:

• The Rail I/O Port 0 and Port 1 views are used to configure the registers assigned to the hardware that is attached to the PMI Rail ports. (These registers can also be accessed by double-clicking the PMI view.)

• The Command Registers view is used to configure pre-defined drive control registers that are written to either by an AutoMax application task or by a UDC application task and then sent to the PMI.


ATTENTION: Only qualified Rockwell personnel or other trained personnel who understand the potential hazards involved may make modifications to the variable configuration. Any modifications may result in uncontrolled machine operation. Failure to observe this precaution could result in damage to equipment and bodily injury.

ATTENTION: Registers and bits in the UDC module that are described as “read only” or for “system use only” must not be written to by the user. Writing to these registers and bits may result in improper system operation. Failure to observe this precaution could result in bodily injury.


• The Feedback Registers view is used to configure the feedback registers that display the current status of the drive. These registers are written to by the PMI.

• The Application Registers Updated Every Scan view is used to configure the application registers that are used for the passing of application-specific control and status data between an AutoMax Processor and the UDC module on every scan. This register range is shared by drive A and drive B.

• The Application Registers Updated Every Nth Scan view is used to configure the application registers that are used for the passing of application-specific control and status data between an AutoMax Processor and the UDC module on every Nth scan, where “N” is defined in register 2001. This register range is shared by drive A and drive B.

• The UDC Module Test I/O Register view is used to configure the register that displays the status of the UDC module’s test switches and LED indicators. This view is also used to configure the UDC module’s D/A meter ports.

• The Interrupt Status and Control Registers view is used to configure the registers that control a user-defined interrupt to an AutoMax task and enable the CCLK signal on the backplane.

The Gain Data values that are used by the PMI are NOT mapped to the UDC module’s dual port registers. The gain values are held in local tunables with reserved names which must be defined in the UDC task for the drive (A or B). The programmer must use the pre-assigned local tunable reserved names described in Appendix B of this manual.

Note that register values are generally in the appropriate engineering units and that the variable names provided here are suggestions only; your variable names may be different. Duplicate common variable names are not permitted within any one rack.

Table 3.1 on page 3-4 lists the configuration views in the AutoMax Programming Executive, the registers to be configured in each, and the section of this instruction manual in which the registers are discussed.

Table 3.2 on page 3-5 lists the UDC dual port registers in numerical order.


3.1 Register and Bit Reference ConventionsUsed in this Manual

Register numbers are shown using the convention A/B, where A is the drive A register number and B is the drive B register number. Note that the Interrupt Status Control registers and the Application registers are the same for both drive A and drive B.

Register descriptions are shown in the following format:

• Register Name: Functional name of the register (e.g., Torque Reference Register).

• Register Numbers: Memory addresses of registers A and B.

• Sug. Var. Name: Suggested variable name for the register (e.g., TRQ_REF%).

• Units: Scaling unit applied to the value stored in the register (e.g., counts, amps ∗10, etc.).

• Range: The upper and lower limits of the value, where applicable (e.g. -4095 to +4095).

• Access: The level of access by the application task (Read, Write, or Read/Write).

Throughout this manual, bit descriptions are shown in the following format:

• Bit Name: Functional name of the bit (e.g., DC Bus Over Voltage Fault).

• Bit Number: The specific bit location within the register (e.g., Bit 0).

• Hex Value: The position within the 16 bit register (e.g., Bit Number 4 = 0010H)

• Sug. Var. Name: Suggested variable name for this bit (e.g., FLT_OV@).

• Access: The level of access by the application task (e.g., Read/Write).

• UDC Error Code: A drive fault’s corresponding error code (e.g. 1018). This is reported in the log for the task in which the error occurred.

• LED: The corresponding status LED, where applicable (e.g., EXT FLT on the PMI Regulator).

Register Name Register Numbers

[Functional description] Sug. Var. Name:Units:Range:Access:

[Additional descriptive details, if required]

Bit Name Bit Number

[Functional description] Hex Value:Sug. Var. Name:Access:UDC Error Code:LED:

[Additional descriptive details, if required]


Table 3.1 – UDC Module Configuration Views and Registers

View Register RangeDescribed in Section:

Rail I/O Drive A: 0- 11Drive B: 12-23

3.2

UDC/PMI Communication Status Registers Drive A: 80-89Drive B: 1080-1089

3.3

Command Registers Drive A: 100-108Drive B: 1100-1108

3.4

Feedback Registers Drive A: 200-222Drive B: 1200-1222

3.5

Application Registers Updated Every Scan 300-599 3.6

Application Registers Updated Every Nth Scan 1300-1599 3.6

UDC Module Test I/O Registers 1000-1017 3.7

ISCR Data Registers 2000-2001 3.8


Note that registers designated System Use Only are read only and may not be changed by the user.

Table 3.2 – UDC Module Dual Port Memory Register Organization.

Registers Function

0 - 23 Rail I/O registers

24-79 System Use Only

80-89 UDC/PMI communication status registers for drive A(monitor only)


100-108 Command registers for drive A


200-222 Feedback registers for drive A


300-599 Application registers updated every scan for drives A and B


1000 UDC module test switch register

1001-1017 UDC module meter port setup registers


1080-1089 UDC/PMI communication status registers for drive B(monitor only)


1100-1108 Command registers for drive B


1200-1222 Feedback registers for drive B


1300-1599 Application registers updated every Nth scan for drives A and B


2000-2010 Interrupt Status and Control registers for drives A and B



3.2 Rail I/O Port Registers (Registers 0-23)

The Rail I/O Port 0 and Port 1 views are used to assign variable names to the rail ports on the PMI. If you have no hardware attached to these ports, do not configure these registers. All of the Rail data for PMI A and PMI B is combined into one section of the dual port memory. Refer to table 3.3. Note that the usage of each register is a function of the type of Rail that is configured. After a STOP ALL, outputs are reset to zero and inputs continue to be updated.

The appropriate variable configuration screen will be displayed based on the hardware that you have specified to be connected to the port.

The following types of hardware can be connected to these ports. The instruction manual for the hardware listed is shown in parenthesis.

Each Rail I/O port has a set of bits that display any errors that may occur and a fault counter that is incremented each time a bad communication check bit is detected. The user’s application program must regularly examine these bits and registers. Refer to tables 3.4, 3.5, and 3.6. The check bit fault counter is reset to zero when a warning reset signal (register 100/1100, bit 9) is generated through the UDC module from the application program.

Table on the following page lists the Rail I/O port registers.

• M/N 45C001A Digital I/O Rail (J-3012)

• M/N 45C630 4-Decade Thumbwheel Switch Input Module (J-3654)

• M/N 45C631 4-Digit LED Output Module (J-3655)

• M/N 61C345 4-Channel Analog Current Input Rail (J-3689)

• M/N 61C346 4-Channel Analog Voltage Input Rail (J-3688)

• M/N 61C350 2-Channel Analog Voltage Input/Output Rail (J-3672)

• M/N 61C351 2-Channel Analog Current Input/Output Rail (J-3673)

• M/N 61C365 4-Channel Analog Current Output Rail (J-3694)

• M/N 61C366 4-Channel Analog Voltage Output Rail (J-3695)


Table 3.3 – Rail I/O Port Registers

Drive A Registers

Drive B Registers Port and Channel

Rail Type and Signal

4 Output 1 4 Input 22 Input 3

2 OutputDigital

I/O4

0 12 Port 0 - Channel 0 Output 0 Input 0 Output 0 Digital

1 13 Port 0 - Channel 1 Output 1 Input 1 Output 1 N/A

2 14 Port 0 - Channel 2 Output 2 Input 2 Input 2 N/A


4 16 Port 0 - Fault Register (Tables 3.4 - 3.6)

5 17 Port 0 - Check Bit Fault Count Register (Tables 3.4 - 3.6)

6 18 Port 1 - Channel 0 Output 0 Input 0 Output 0 Digital

7 19 Port 1 - Channel 1 Output 1 Input 1 Output 1 N/A



10 22 Port 1 - Fault Register (Tables 3.4 - 3.6)

11 23 Port 1 - Check Bit Fault Count Register (Tables 3.4 - 3.6)

1. 4-Output Analog Rail Module (M/N 61C365, 61C366)2. 4-Input Analog Rail Module (M/N 61C345, 61C346)3. 2-Output/2-Input Analog Rail Module (M/N 61C350, 61C351)4. Digital I/O Rail (M/N 45C1), Thumbwheel Switch Input Module (M/N 45C630), or LED Output Module (M/N 45C631

Table 3.4 – Fault Register and Check Bit Fault Counter RegisterUsage for a Digital I/O Rail or 4-Output Analog Rail Module

Drive A Registers

Drive B Registers Description

4 16 Port 0 Fault Register


Bit 8: No device plugged into a configured port

Bit 9: Bad ID code: device other than a rail plugged into the port

Bit 10: Bad rail communication check bits received

Bit 11: PMI interface is not ready

5 17 Port 0 Check Bit Fault Counter Register


These registers can be reset by setting bit 9 of the Drive Control register (100/1100)


Table 3.5 – Fault Register and Check Bit Fault Counter RegisterUsage for a Digital I/O Rail or 4-Input Analog Rail Module

Drive A Registers




Bit 0: Analog Channel 0 Input Over-Range

Bit 1: Analog Channel 0 Input Under-Range








Bit 9: Bad ID code: device other than rail plugged into port


Bit 11: PMI interface not ready



These registers can be reset by setting bit 9 of the Drive Control register (100/1100)

Table 3.6 – Fault Register and Check Bit Fault Counter RegisterUsage for a 2-Output/2-Input Analog Rail Module

Drive A Registers









Bit 9: Bad ID code: device other than rail plugged into port


Bit 11: PMI interface is not ready



The register can be reset by setting bit 9 of the Drive Control register (100/1100)


3.3 UDC/PMI Communication Status Registers(Registers 80-89/1080-1089)

The UDC/PMI Communication Status Registers display the status of the fiber-optic communications between the UDC module and the PMI. Two consecutive errors will be indicated by a communication fault, and the drive will stop. Refer to register 202/1202, bit 15, for more information. Note that the communication status registers are for system use only and can only be monitored. They cannot be defined during configuration for access within the application task. The status of these registers will be retained after a Stop All.

UDC Module Communication Status Register 80/1080

The UDC Module Communication Status register contains bits which describe any errors or warnings reported on the UDC module related to UDC/PMI communication. These bits are latched when set and will remain set until a fault reset or warning reset is issued.

Invalid Receive Interrupt Bit 0

The Invalid Receive Interrupt bit is set if the interrupt generated by the Universal Serial Controller (USC) is not properly marked.

Hex Value: 0001HSug. Var. Name: N/AAccess: Read onlyUDC Error Code: N/ALED: N/A

No End of Frame Status Received Bit 1

The No End of Frame Status Received bit is set if the USC does not report an End of Frame condition when the receive interrupt is generated.


CRC/Framing Error Bit 2

The CRC/Framing Error bit is set if the USC reports a CRC or Framing error on the last frame (message) received.


Overrun Error Bit 3

The Overrun Error bit is set if the USC reports a receive first-in, first-out overrun.



UDC Module Communication Status Register (Continued) 80/1080

DMA Format Error Bit 4

The DMA Format Error bit is set if the length of the received message does not match the length encoded in the message itself.


Transmitter Underrun Bit 5

The Transmitter Underrun bit is set if the USC reports a transmit first-in, first-out underrun.


CCLK Communication Synchronization Error Bit 6

The CCLK Communication Synchronization Error bit is set if two or more CCLK counter ticks occur and no message is received.

Hex Value: 0040HSug. Var. Name: N/AAccess: Read onlySug. Var. Name: VDC_RUN@UDC Error Code: N/ALED: N/A

External Loopback Data Error Bit 7

The External Loopback Data Error bit is set during the UDC module loopback test if the transmit message does not match the receive message. This test is performed only at power up or after a reset.


Missed Gains Bit 8

The Missed Gains bit is set if gain data from the PMI could not be written because memory was being written to when the gain values were received.



UDC Module Communication Status Register (Continued) 80/1080

Multiplexed Data Verification Failure Bit 9

The Multiplexed Data Verification Failure bit is set if data which is multiplexed into command/feedback messages does not verify correctly.


No Matching PMI Operating System Present Bit 10

The No Matching PMI Operating System Present bit is set if the correct PMI operating system is not present in the UDC module’s operating system and the PMI is requesting an operating system.


This condition will cause the loading of the PMI operating system to fail. However, the UDC module and the PMI will continue to retry loading the PMI operating system.

Invalid PMI Operating System Header Bit 11

The Invalid PMI Operating System Header bit is set if the UDC module cannot locate a valid PMI operating system header when attempting to load an operating system to a PMI.



Incompatible PMI Hardware Bit 12

The Incompatible PMI Hardware bit is set if the PMI hardware is not compatible with the PMI operating systems in the UDC operating system.


UDC Module Receive Count Register 81/1081

This register contains the number of messages received by the UDC module from the PMI. This is a 16-bit value that rolls over when it reaches its maximum.

Sug. Var. Name: N/AUnits: CountsRange: 0-32000Access: Read only


UDC Module CRC Error Count Register 82/1082

This register contains the number of messages with CRC errors received by the UDC module from the PMI.

Sug. Var. Name: N/AUnits: CountsRange: N/AAccess: Read only

UDC Module Format Error Count Register 83/1083

This register contains the number of messages with format errors received by the UDC module from the PMI.


PMI Communication Status Register 84/1084

The PMI Communication Status register contains bits which describe any errors or warnings reported by the PMI related to UDC/PMI communication. These bits are latched when set and will remain set until a fault reset or warning reset is issued.

Invalid Receive Interrupt Bit 0

The Invalid Receive Interrupt bit is set if the interrupt generated by the Universal Serial Controller (USC) is not properly marked.


No End of Frame Status Received Bit 1

The No End of Frame Status Received bit is set if the USC does not report an End of Frame condition when the receive interrupt is generated.


CRC/Framing Error Bit 2

The CRC/Framing Error bit is set if the USC reports a CRC or Framing error on the last frame (message) received.



PMI Communication Status Register (Continued) 84/1084

Overrun Error Bit 3

The Overrun Error bit is set if the USC reports a receive first-in, first-out overrun.


DMA Format Error Bit 4

The DMA Format Error bit is set if the length of the received message does not match the length encoded in the message itself.


Transmitter Underrun Bit 5

The Transmitter Underrun bit is set if the USC reports a transmit first-in, first-out underrun.


CCLK Communication Synchronization Error Bit 6

The CCLK Communication Synchronization Error bit is set if two or more CCLK counter ticks occur and no message is received.


UDC CCLK Communication Synchronization Error Bit 8

The UDC CCLK Communication Synchronization Error bit is set if two UDC CCLK counter ticks occur and no message is received from the PMI.




Multiplexed Data Verification Failure Bit 9

The Multiplexed Data Verification Failure bit is set if data multiplexed into command/feedback messages does not verify.


Invalid PMI Start Operating System Address Bit 12

The Invalid PMI Start Operating System Address bit is set by the PMI if the operating system is not within the allocated operating system address area.



Insufficient PMI Memory to Load the PMI Operating System Bit 13

The Insufficient PMI Memory to Load the PMI Operating System bit is set by the PMI if there is insufficient memory for loading the operating system.



Invalid PMI Load Address Bit 14

The Invalid PMI Load Address bit is set by the PMI if the address at which it is to load the operating system is invalid.





PMI Operating System Overflow into Stack Memory Bit 15

The PMI Operating System Overflow into Stack Memory bit is set by the PMI if the loading of the PMI operating system will overrun the PMI stack memory area.



PMI Receive Count Register 85/1085

The PMI Receive Count Register contains the number of messages received by the PMI. This is a 16-bit value that rolls over when it reaches its maximum.


PMI CRC Error Count Register 86/1086

This register contains the number of messages with CRC errors received by the PMI.


PMI Format Error Count Register 87/1087

This register contains the number of messages with format errors received by the PMI.



UDC Module Fiber-Optic Link Status Register 88/1088

This register shows the current operating state of the fiber-optic link to the PMI. The lower byte (bits 0-7) shows the actual link status while the upper byte (bits 8-15) shows whether the communication taking place is synchronized or not.

Sug. Var. Name: N/AUnits: N/ARange: N/AAccess: Read only

If the lower byte is equal to:

xx01H:the UDC module is waiting for a request from the PMI for an operating system.

xx02H:the UDC module is downloading an operating system to the PMI.

xx03H:the UDC module and the PMI are exchanging data.

xx06H:the external loopback test is being conducted on the fiber-optic link.

If the upper byte is equal to:

01xxH:the communication between the UDC module and the PMI is synchronized.

02xxH:the communication between the UDC module and the PMI is not synchronized.

UDC Module Transmitted Message Count Register 89/1089

This register contains the number of messages transmitted by the UDC module.



3.4 Command Registers (Registers 100-199/1100-1199)

The Command Registers view is used to configure command registers. These registers are used for command data sent to the PMI by the UDC module at the end of every scan of the UDC Processor. Note that the bits in these registers (except bit 15 in register 100/1100) are used to command action only and do not indicate the status of the action commanded. The feedback registers (registers 200/1200 to 299/1299) are provided for this purpose. The status of the command registers is not retained after a Stop All.The status of the command registers is not retained after a Stop All.

Drive Control Register 100/1100

The Drive Control Register contains the bits that control the operation of the SB3000 Synchronous Rectifier. The SB3000 Rectifier can operate in one of three modes: idle, voltage loop run, or bridge test. The default operating mode is idle. The other two modes are selected using this register. (See Appendices F and G for detailed information on the voltage loop run and bridge test modes.)

All bits in this register (except bit 15) can only be written to by a task on an AutoMax Processor. They cannot be written to by a task on a UDC module. All read/write bits in this register are edge-sensitive and must be maintained to assert the command.

Voltage Loop Run Bit 0

The Voltage Loop Run bit is set by the application task to enable the voltage loop in the PMI Processor. See F for more information.

Hex Value: 0001HSug. Var. Name: VDC_RUN@Access: Read/WriteUDC Error Code: N/ALED: N/A

!ATTENTION: The pre-charge contactor for the SB3000 must be closed and the voltage loop must be on (register 200/1200, bit 0) before any load inverters can be put into run. If the SB3000 pre-charge contactor is not closed, running a load inverter will burn up the pre-charge resistors. Failure to observe this precaution could result in damage to, or destruction of, the equipment.

Bridge Test Enable Bit 2

The Bridge Test Enable bit is set to close the pre-charge contactor and enable the bridge test procedure.

Hex Value: 0004HSug. Var. Name: BRG_TST@Access: Read/WriteUDC Error Code: N/ALED: N/A

The bridge test turns on individual or sets of power devices in a power module in order to verify the gate cable connections and power device operation. The value in the Bridge Test Code register (105/1105) is used to select which power devices to turn on. Refer to G for further information on performing the bridge test.

Note that this test is normally performed at the factory and should not have to be performed again unless the power devices are replaced.


Drive Control Register (Continued) 100/1100

!ATTENTION: The motor must be disconnected before the bridge test is run. Failure to observe this precaution could result in damage to, or destruction of, the equipment.

Fault Reset Bit 8

The Fault Reset bit is set and reset to clear the Drive Fault register, 202/1202. After a drive fault is latched, the Drive Fault register must be cleared before the drive can be re-started.

Hex Value: 0100HSug. Var. Name: FLT_RST@Access: Read/WriteUDC Error Code: N/ALED: N/A

To clear the Drive Fault register any command bits that have been set in the Drive Control register (100/1100) must first be turned off. Once the cause of the fault has been corrected, the Fault Reset bit must be turned on and then off again. The Fault Reset bit will clear the entire Drive Fault register. Then the desired command bits may be turned on again.

The Fault Reset bit is edge-sensitive, i.e., leaving it set will not clear the fault register continuously. Note that if the fault condition still exists after register 202/1202 is cleared, it will continue to trigger drive faults until the problem has been corrected.

Warning Reset Bit 9

The Warning Reset bit is set and reset to clear the Drive Warning register 203/1203. This bit is edge-sensitive, i.e., leaving it set will not clear the warning register continuously.

Hex Value: 0200HSug. Var. Name: WRN_RST@Access: Read/WriteUDC Error Code: N/ALED: N/A

Enable Parallel Power Module A Bit 10

This bit is set to enable the bridge test in the first power module in a parallel power module configuration. Bit 2 in this register must be set first and the pre-charge contactor must close before this bit can be set.

Hex Value: 0400HSug. Var. Name: PPM_ENA@Access: Read onlyUDC Error Code: N/ALED: N/A

See the description of bit 2 above and G for more information about performing the bridge test.


Drive Control Register (Continued) 100/1100

Enable Parallel Power Module B Bit 11

This bit is set to enable the bridge test in the second power module in a parallel power module configuration. Bit 2 in this register must be set first and the pre-charge contactor must close before this bit can be set.

Hex Value: 0800HSug. Var. Name: PPM_ENB@Access: Read onlyUDC Error Code: N/ALED: N/A


Enable Parallel Power Module C Bit 12

This bit is set to enable the bridge test in the third power module in a parallel power module configuration. Bit 2 in this register must be set first and the pre-charge contactor must close before this bit can be set.

Hex Value: 1000HSug. Var. Name: PPM_ENC@Access: Read onlyUDC Error Code: N/ALED: N/A


UDC Task Running Bit 15

The UDC Task Running bit is a status bit that indicates that the UDC task is running. This bit is used by the PMI Regulator to prevent the minor loop from running if the UDC task is not running.

Hex Value: 8000HSug. Var. Name: UDC_RUN@Access: Read onlyUDC Error Code: N/ALED: N/A

This bit must NOT be written to by the user. This is a status bit that must only be written to by the operating system.


I/O Control Register 101/1101

The I/O Control Register contains the bits that control the EXT FLT LED on the PMI Processor, the auxiliary output on the Resolver & Drive I/O module, and the loopback test.

External Fault LED Bit 2

The External Fault LED command bit is set by the application task to turn on the EXT FLT LED on the PMI Processor.

Hex Value: 0004HSug. Var. Name: EXT_FLT@Access: Read/WriteUDC Error Code: N/ALED: EXT FLT

Auxiliary Output Bit 4

The Auxiliary Output bit is set to turn on the auxiliary output on the Resolver & Drive I/O module in the PMI rack.

Hex Value: 0010HSug. Var. Name: AUX_OUT@Access: Read/WriteUDC Error Code: N/ALED: AUX OUT

UDC Module External Loopback Bit 15

The UDC Module External Loopback bit is set to enable the external loopback test on the UDC module's fiber-optic ports.

Hex Value: 8000HSug. Var. Name: UDC_LB@Access: Read/WriteUDC Error Code: N/ALED: N/A

Register 101, bit 15, controls the COMM A test while register 1101, bit 15, controls the COMM B test. Note that this bit must be reset to 0 before the loopback connector is removed from the UDC module's fiber-optic ports. Refer to the Fiber-Optic Cabling instruction manual for specific instructions on performing the loopback test.


Voltage Reference Register 102/1102

The value in the Voltage Reference register is the desired DC bus voltage. This value is the main input into the voltage loop on the PMI Processor. The loop is enabled in register 100/1100, bit 0.

Sug. Var. Name: VDC_REF%Units: VoltsRange: See textAccess: Read/Write

The minimum value is 1.414 times the RMS value of the AC line voltage plus 10%. The maximum value is 875V. If the value is outside this range, register 203/1203, bit 4 (WRN_RIL@) will be set.

Power Factor Current Reference Register 103/1103

The value in this register is the reference to the leading power factor logic in the voltage regulator. If there is extra leading power factor capacity, the SB3000 Rectifier can compensate for other machines on the AC line that produce lagging power factors.

Sug. Var. Name: IPF_REF%Units: RMS Amps ∗ 10Range: Limited by

rectifier capacityAccess: Read/Write

This value selects the minimum RMS current that will be commanded independent of load. A value of 0 disables the power factor correction. The maximum current that can be commanded is a function of input voltage, load requirements, and rectifier capacity. If the DC bus current is high, the reactive current will be limited and register 203/1203, bit 3 will be set.

The value is entered in RMS Amps times 10. For example, 60.0 amps is entered as 600.

Refer also to the description of VAR feedback register 211/1211. The VAR Feedback register contains the VARS (volt-amperes reactive) produced by the Rectifier in response to the reference in register 103/1103.

Test Code Register 105/1105

The value entered in this register is used as data for the built-in bridge test procedures commanded by the Drive Control register (100/1100). See Appendix G for detailed information on performing the bridge test.

Sug. Var. Name: TST_CODE%Units: See textRange: N/AAccess: Read/Write

PMI D/A Output Register 106/1106

The value in the PMI D/A Output register is used to pass a variable in the UDC to the PMI Processor to be displayed on one of the four PMI meter ports. See section 3.7.2.

Sug. Var. Name: PMI_DA%Units: See textRange: See textAccess: Read/Write

This register can be used to display any variable in the AutoMax system as long as it is a 16-bit integer. Double-integer or floating point values cannot be displayed on the PMI Processor’s D/A meter ports. The desired value must be copied into this register by an application task. The value in the register is transmitted to the PMI Regulator at the end of every scan.


3.5 Feedback Registers (Registers 200-299/1200-1299)

The Feedback Registers view is used to configure the feedback registers that display the current status of the drive. These registers are updated by the PMI Processor and sent to the UDC module over the fiber-optic link before every scan of the UDC task. The status of these registers is retained after a Stop All.

Drive Status Register 200/1200

The bits in the Drive Status register indicate the current state of the Synchronous Rectifier. They reflect the status of the activity initiated through the Drive Control Register (register 100/1100). All the bits in this register are written to by the PMI Processor.

Voltage Loop On Bit 0

The PMI Processor sets the Voltage Loop On bit in response to the VDC_RUN@ command after all of the interlock tests are passed. VDC_ON@ indicates that the voltage minor loop is running and the bus is energized.

Hex Value: 0001HSug. Var. Name: VDC_ON@Access: Read onlyUDC Error Code: N/ALED: N/A

Voltage Loop Standby Bit 1

The PMI Processor sets the Voltage Minor Loop Standby bit to indicate that the Rectifier is performing a power-dip ride through. This will occur if input power is lost while the voltage control loop is running.

Hex Value: 0002HSug. Var. Name: VDC_SB@Access: Read onlyUDC Error Code: N/ALED: N/A

If any fault occurs while the Rectifier is in standby mode, it will shut down and not start up again until all faults are reset. Refer to the description of register 203/1203, bit 10 for an explanation of the power dip ride through warning.

In Current Limit Bit 2

The In Current Limit bit is set if the total rectifier current is being limited to the configured value.

Hex Value: 0004HSug. Var. Name: IN_LMT@Access: Read onlyUDC Error Code: N/ALED: N/A


Drive Status Register (Continued) 200/1200

Power Factor Current In Limit Bit 3

The Power Factor Current in Limit bit is set if the power factor current is being limited by the PMI to keep the current minor loop from saturating.

Hex Value: 0008HSug. Var. Name: IPF_LMT@Access: Read onlyUDC Error Code: N/ALED: N/A

Line Synchronized Bit 7

The Line Synchronized bit is set when the PMI Processor is synchronized to the AC line. This bit is valid when the Rectifier has input power, whether the voltage control loop is on or not.

Hex Value: 0080HSug. Var. Name: LIN_SYN@Access: Read onlyUDC Error Code: N/ALED: N/A

If this bit is not on when VDC_RUN@ is commanded, an Interlock failure will occur. See the description of the IC_SYN@ bit (register 205/1205, bit 6).

Fault Detected Bit 8

The Fault Detected bit is set if any fault is detected in the Rectifier. This bit is reset by bit 8 of register 100/1100.

Hex Value: 0100HSug. Var. Name: FLT@Access: Read onlyUDC Error Code: N/ALED: N/A

See the description of the Drive Fault register (202/1202) for more information.

Warning Detected Bit 9

The Warning Detected bit is set if any warning is detected in the Rectifier. This bit is reset by bit 9 of register 100/1100.

Hex Value: 0200HSug. Var. Name: WRN@Access: Read onlyUDC Error Code: N/ALED: N/A

See the description of the Drive Warning register (203/1203) for more information.

Rail Data Ready Bit 13

The Rail Data Ready bit is set when the PMI Processor rail data is valid.

Hex Value: 2000HSug. Var. Name: RAIL_OK@Access: Read onlyUDC Error Code: N/ALED: N/A


Drive Status Register (Continued) 200/1200

CCLK Synchronized Bit 14

The CCLK Synchronized bit is set when the CCLK in the UDC module is synchronized with CCLK in the Rectifier’s PMI Processor.

Hex Value: 4000HSug. Var. Name: CCLK_OK@Access: Read onlyUDC Error Code: N/ALED: N/A

This bit is equal to zero if CCLK is not turned on in the AutoMax rack or if there have been two consecutive instances when CCLK is not synchronized after the application task has turned CCLK on. In this case, the feedback data from the PMI is not current.

This bit should normally be used only in the start permissive logic for the Rectifier (which must be true only once to start the Rectifier). It does not have to be used in the run permissive logic for the Rectifier (which must be true during the entire execution of the task.

Refer to the Communication Lost Fault bit description (register 202/1202, bit 15) for more information.

PMI Operating System Loaded Bit 15

The PMI Processor sets the PMI Operating System Loaded bit when the operating system has been successfully downloaded from the UDC module to the PMI Processor after power-up.

Hex Value: 8000HSug. Var. Name: PMI_OK@Access: Read onlyUDC Error Code: N/ALED: N/A

I/O Status Register 201/1201

The bits in the I/O Status register indicate the current state of the inputs on the Rectifier’s Resolver & Drive I/O module.

Run Permissive Input Bit 0

The Run Permissive Input bit displays the status of the Run Permissive Input signal to the Rectifier. This signal is brought in through the Resolver & Drive I/O module in the Rectifier’s PMI rack.

Hex Value: 0001HSug. Var. Name: RPI@Access: Read onlyUDC Error Code: N/ALED: RPI on Resolver

Module

This bit is on if voltage is present at the Run Permissive input. If this bit is on, the Rectifier is permitted to fire its IGBT power devices. If this bit is off, the Rectifier is prohibited from firing its power devices.

Note that turning off RPI does not disable output voltage. If AC input power is on, the emitter-collector diodes in the IGBTs supply rectified line voltage to the output terminals, independent of the state of RPI.


I/O Status Register (Continued) 201/1201

!ATTENTION: Do not use the RPI input on the SB3000 Rectifier’s Resolver & Drive I/O module as a method of shutting off the Rectifier. Turning this input off stops the Rectifier’s power devices from firing. However, the emitter-collector diodes in these power devices will still conduct and will continue to feed the load inverter if input power is on. Failure to observe this precaution could result in damage to, or destruction of, the equipment.

115 VAC Auxiliary Input 1 Bit 1

The Auxiliary Input 1 bit reflects the status of the 115 VAC auxiliary input 1 on the Resolver & Drive I/O module in the Rectifier’s PMI rack. When the input signal is present, this bit is set.

Hex Value: 0002HSug. Var. Name: AUX_IN1@Access: Read onlyUDC Error Code: N/ALED: AUX IN1on

Resolver module



Hex Value: 0004HSug. Var. Name: AUX_INX2@Access: Read onlyUDC Error Code: N/ALED: AUX IN2 on

Resolver module



Hex Value: 0008HSug. Var. Name: AUX_IN3@Access: Read onlyUDC Error Code: N/ALED: AUX IN3 on

Resolver module




Resolver module


I/O Status Register (Continued) 201/1201




Resolver module

Pre-Charge Feedback Bit 12

The Pre-charge Feedback bit reflects the status of the Rectifier’s pre-charge contactor. The PMI sets this bit when the contactor is closed.

Hex Value: 1000HSug. Var. Name: CHG_FB@Access: Read onlyUDC Error Code: N/ALED: N/A

This bit must be used by the inverter application tasks. The load inverters must not be allowed to operate if the Rectifier’s pre-charge contactor is open.

Drive Fault Register 202/1202

The bits in the Drive Fault register indicate the cause of a Rectifier shutdown. The bits in this register are latched until they are reset by setting the Fault Reset bit of the Drive Control register (100/1100, bit 8). After turning the Fault Reset bit on, the Rectifier may be re-started after turning the desired command bit in register 100/1100 off and then back on again. If the fault condition still exists, the identifying bit in this register will immediately be set again.

The fault conditions reported in this register result only in the Rectifier shutting down. The UDC task is not stopped automatically if a Rectifier fault occurs unless it is specifically instructed to in an application task. The user must ensure that the AutoMax application task tests register 202/1202 and takes appropriate action if a fault occurs.

Note that the status of this register is also reported in the error log for the task in which the error occurred. Most faults reported in this register are also indicated by the EXT FLT or P.M. FLT LEDs on the Rectifier’s PMI Processor.

DC Bus Overvoltage Fault Bit 0

The DC Bus Overvoltage Fault bit is set if hardware detects that DC bus voltage exceeds the maximum of 900 volts.

Hex Value: 0001HSug. Var. Name: FLT_OV@Access: Read onlyUDC Error Code: 1018LED: P.M. FLT


Drive Fault Register (Continued) 202/1202

DC Bus Overcurrent Fault Bit 1

The DC Bus Overcurrent Fault bit is set if DC bus current exceeds 125% of the Rectifier’s rated DC bus current.

Hex Value: 0002HSug. Var. Name: FLT_DCI@Access: Read onlyUDC Error Code: 1020LED: P.M. FLT

Instantaneous Overcurrent Fault Bit 3

The Instantaneous Overcurrent Fault bit is set if a power device overcurrent or shoot-through fault occurs.

Hex Value: 0008HSug. Var. Name: FLT_IOC@Access: Read onlyUDC Error Code: 1017LED: P.M. FLT

Power Device Status registers 204/1204, 220/1220, and 221/1221 indicate faults in Power Modules A, B, or C, respectively. If a single power module is used, only register 204/1204 is valid.

Bits 0 - 5 in the appropriate status register are set to indicate which power devices produced the fault. In the event of a shoot-through fault, bit 6 is set as well. Refer the descriptions of these registers for further information.

Local Power Interface Fault Bit 4

The Local Power Interface fault bit is set if the power supply for the LPI module is not operating within tolerance.

Hex Value: 0010HSug. Var. Name: FLT_LPI@Access: Read onlyUDC Error Code: 1022LED: P.M. FLT

Gate Driver Interface Fault Bit 5

The Gate Driver Interface Fault bit is set if the power supply on the Gate Driver Interface (GDI) module is not operating within tolerance.

Hex Value: 0020HSug. Var. Name: FLT_GDI@Access: Read onlyUDC Error Code: 1023LED: OK on GDI

module

If power modules are connected in parallel, bit 7 in register 204/1204, 220/1220, or 221/1221 is set to indicate which GDI module is affected.



Charge Fault Bit 6

The Charge Fault bit is set if either of the following has occurred:

Hex Value: 0040HSug. Var. Name: FLT_CHG@Access: Read onlyUDC Error Code: 1024LED: EXT FLT and

P.M. FLT

• the pre-charge contactor did not close when commanded to by the PMI Processor, or

• the contactor opened without being commanded to do so.

Overtemperature Fault Bit 7

The Overtemperature Fault bit is set if the fault level thermal switch in the power module opens.

Hex Value: 0080HSug. Var. Name: FLT_OT@Access: Read onlyUDC Error Code: 1016LED: P.M. FLT

If power modules are connected in parallel, bit 12 is set in register 204/1204, 220/1220, or 221/1221 to indicate which GDI detected the fault.

Power Loss Fault Bit 10

The Power Loss Fault bit is set if the AC input voltage is less than 75%, or more than 125%, of the configured value for more than ten seconds while the Rectifier is running.

Hex Value: 0400HSug. Var. Name: FLT_PWR@Access: Read onlyUDC Error Code: 1025LED: EXT FLT

A drive warning (WRN_PWR@) will be issued, and the power dip ride-through feature of the SB3000 will be enabled, for ten seconds prior to the drive fault. See the description of register 203/1203, bit 10, for further information.

This bit will also be set if one phase of the AC line is lost or if line synchronization is lost.

Power Technology Fault Bit 11

The Power Technology Fault bit is set if the Rectifier’s AC Power Technology module fails.

Hex Value: 0800HSug. Var. Name: FLT_PTM@Access: Read onlyUDC Error Code: 1011LED: OK on PWR

TECH Module

Register 222/1222 provides additional diagnostics if this fault occurs.



PMI Power Supply Fault Bit 12

The PMI Power Supply Fault bit is set if the power supply for the Rectifier’s PMI rack is not operating properly.

Hex Value: 1000HSug. Var. Name: FLT_PS@Access: Read onlyUDC Error Code: 1012LED: PWR OK on

Power Supply module

PMI Read/Write Fault Bit 13

The PMI Read/Write Fault bit is set if a PMI Processor read or write operation fails.

Hex Value: 2000HSug. Var. Name: FLT_RW@Access: Read onlyUDC Error Code: 1013LED: N/A

UDC Run Fault Bit 14

The UDC Run Fault bit is set if the UDC task stops while the voltage loop is running in the PMI Regulator.

Hex Value: 4000HSug. Var. Name: FLT_RUN@Access: Read onlyUDC Error Code: 1014LED: N/A

Communication Lost Fault Bit 15

The Communication Lost Fault bit is set if the fiber-optic communication between the Rectifier’s PMI Processor and the UDC module is lost due to two consecutive errors of any type.

Hex Value: 8000HSug. Var. Name: FLT_COM@Access: Read onlyUDC Error Code: 1015LED: COMM OK

This bit is set only after communication between the PMI Regulator and UDC module has been established. This bit should be used in the run permissive logic for the Rectifier. Also refer to the CCLK Synchronized bit (register 200/1200, bit 14).


Drive Warning Register 203/1203

The warnings indicated by the Drive Warning register cause no action by themselves. Any resulting action is determined by the application task. The user must ensure that the AutoMax application task monitors register 203/1203 and takes appropriate action if any of these conditions occurs. If a warning condition is detected, the corresponding bit is latched until the Warning Reset bit (bit 9) of the Drive Control register (register 100/1100) is set.

DC Bus Overvoltage Warning Bit 0

The DC Bus Overvoltage Warning bit is set if the DC bus voltage rises above the overvoltage threshold value stored in local tunable OVT_E0%.

Hex Value: 0001HSug. Var. Name: WRN_OV@Access: Read onlyUDC Error Code: N/ALED: N/A

DC Bus Undervoltage Warning Bit 1

The DC Bus Undervoltage Warning bit is set if the DC bus voltage drops below the undervoltage threshold stored in local tunable UVT_E0%.

Hex Value: 0002HSug. Var. Name: WRN_UV@Access: Read onlyUDC Error Code: N/ALED: N/A

Ground Current Warning Bit 2

The Ground Current Warning bit is set if ground current exceeds the ground current level stored in local tunable GIT_E1%.

Hex Value: 0004HSug. Var. Name: WRN_GND@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase Loss Warning Bit 3

The Phase Loss Warning bit is set if a phase loss occurs in the AC line. Note that the phase loss diagnostic cannot detect a phase loss if there is no load current.

Hex Value: 0008HSug. Var. Name: WRN_PL@Access: Read onlyUDC Error Code: N/ALED: N/A


Drive Warning Register (Continued) 203/1203

Reference In Limit Warning Bit 4

The Reference in Limit Warning bit is set if the VDC reference (register 102/1102).is less than the minimum or greater than the maximum allowed, where:

Minimum = 1.1 * 1.414 * AC line VRMSMaximum = 875 volts

Hex Value: 0010HSug. Var. Name: WRN_RIL@Access: Read onlyUDC Error Code: N/ALED: N/A

In Bridge Test mode, this bit is used by the bridge test to indicate an illegal test code. Refer to the Bridge Test Enable bit (register 100/1100, bit 2) and to Appendix G for additional information on the bridge test.

Load Sharing Warning Bit 6

The Load Sharing Warning is set if a problem occurs with current sharing between parallel power modules.

Hex Value: 0040HSug. Var. Name: WRN_SHR@Access: Read onlyUDC Error Code: N/ALED: N/A

Bits 13, 14, or 15 in registers 204/1204, 220/1220, or 221/1221 will be set to indicate the phase and the power module affected. Refer to the descriptions of these registers for details.

Overtemperature Warning Bit 7

The Overtemperature Warning bit is set if the warning level thermal switch in the power module opens.

Hex Value: 0080HSug. Var. Name: WRN_OT@Access: Read onlyUDC Error Code: N/ALED: N/A

If power modules are connected in parallel, bit 12 is set in register 204/1204, 220/1220, or 221/1221 to indicate which power module is affected.

Bad Gain Data Warning Bit 8

The Bad Gain warning bit is set if a tunable variable is changed to an illegal value while the UDC task is running. The value will be restored to its previous valid value by the PMI Processor.

Hex Value: 0100HSug. Var. Name: WRN_BGD@Access: Read onlyUDC Error Code: N/ALED: N/A

For a description of the tunable variables, refer to Appendix B.



Power Module Overload Warning Bit 9

The Power Module Overload Warning bit is set if the continuous current rating of the Rectifier is exceeded for a period of approximately 5 minutes and does not decrease and maintain the continuous rating for at least 45 minutes.

Hex Value: 0200HSug. Var. Name: WRN_OL@Access: Read onlyUDC Error Code: N/ALED: N/A

Note that when operating at 4 KHz, SB3000 Synchronous Rectifiers have a continuous rating and an overload rating. If the overload rating is reached and maintained for approximately 5 minutes, the current must decrease to the continuous rating level for a minimum of 45 minutes to avoid this warning.

Power Lost Warning Bit 10

The Power Lost Warning bit is set to indicate that the power dip ride-through feature of the SB3000 has been enabled. This will occur if the PMI Processor detects that the AC input voltage is less than 75% or more than 125% of the configured value.

Hex Value: 0200HSug. Var. Name: WRN_PWR@Access: Read onlyUDC Error Code: N/ALED: N/A

When WRN_PWR@ is set the PMI Processor disables the firing of the IGBTs. If power is restored to the correct range within 10 seconds, the PMI will resynchronize and resume operation. If correct power is not restored within 10 seconds, bit 10 in Fault Code register 202/1202 will set, and the Rectifier will shut down.

While the Rectifier is performing the power dip ride through, bit 1 of register 200/1200 is set to indicate that the voltage loop is in standby. This allows the UDC application task to take some action, such as stopping or decelerating the machine and allowing the inertia in the machine to maintain the DC bus voltage until power comes back or the machine is stopped.

PMI Fan Loss Warning Bit 12

The PMI Fan Loss Warning bit is set if air flow through the SB3000 PMI rack is not sensed.

Hex Value: 1000HSug. Var. Name: WRN_FAN@Access: Read onlyUDC Error Code: N/ALED: N/A



Rail Communication Warning Bit 13

The Rail Communication Warning bit is set if a rail communication problem occurs and is logged in registers 4, 10, 16, or 22.

Hex Value: 2000HSug. Var. Name: WRN_RAL@Access: Read onlyUDC Error Code: N/ALED: I/O FLT

Refer to tables 3.4, 3.5, and 3.6 for further information.

CCLK Not Synchronized Warning Bit 14

The CCLK Not Synchronized Warning bit is set if the CCLK counters in the Rectifier’s PMI Processor and the UDC module are momentarily unsynchronized.

Hex Value: 4000HSug. Var. Name: WRN_CLK@Access: Read onlyUDC Error Code: N/ALED: N/A

PMI Communication Warning Bit 15

The PMI Communication Warning bit is set if a fiber-optic communication error is detected between the Rectifier’s PMI Processor module and the UDC module.

Hex Value: 8000HSug. Var. Name: WRN_COM@Access: Read onlyUDC Error Code: N/ALED: N/A

Communication errors in two consecutive messages will result in a drive fault.


Power Device Status Register 204/1204

The bits in the Power Device Status register indicate the status of the power devices in Power Module A (the Rectifier’s main power module). When multiple power modules are connected in parallel, status registers 220/1220 and 221/1221 are used for Power Modules B and C, respectively.

If an IOC (overcurrent) fault is detected, the associated phase upper and lower status bits are set. If a phase DSAT (shoot-through) fault is detected, the associated phase status bits are set and the Intelligent Power Module bit, IPUA@, is set.

Phase U-Upper IOC A Bit 0

The Phase U-Upper IOC A status bit is set if an IOC or DSAT fault occurs in Power Module A’s phase U, upper power device.

Hex Value: 0001HSug. Var. Name: U_UPA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V-Upper IOC A Bit 1

The Phase V-Upper A status bit is set if an IOC or DSAT fault occurs in Power Module A’s phase V, upper power device.

Hex Value: 0002HSug. Var. Name: V_UPA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase W-Upper IOC A Bit 2

The Phase W-Upper A status bit is set if an IOC or DSAT fault occurs in Power Module A’s phase W, upper power device.

Hex Value: 0004HSug. Var. Name: W_UPA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase U-Lower IOC A Bit 3

The Phase U-Lower A status bit is set if an IOC or DSAT fault occurs in Power Module A’s phase U, lower power device.

Hex Value: 0008HSug. Var. Name: U_LOA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V-Lower IOC A Bit 4

The Phase V-Lower A status bit is set if an IOC or DSAT fault occurs in Power Module A’s phase V, lower power device.

Hex Value: 0010HSug. Var. Name: V_LOA@Access: Read onlyUDC Error Code: N/ALED: N/A


Power Device Status Register (Continued) 204/1204

Phase W-Lower IOC A Bit 5

The Phase W-Lower A status bit is set if an IOC or DSAT fault occurs in Power Module A’s phase W, lower power device.

Hex Value: 0020HSug. Var. Name: W_LOA@Access: Read onlyUDC Error Code: N/ALED: N/A

Intelligent Power Module A Bit 6

The Intelligent Power Module A bit is set to indicate that a DSAT (shoot-through) fault has occurred in Power Module A. Bits 0 - 5 should be checked to identify the device in which the fault occurred.

Hex Value: 0040HSug. Var. Name: IPMA@Access: Read onlyUDC Error Code: N/ALED: N/A

GDI Fault A Bit 7

The GDI Fault A bit is set if a problem is detected with the power supply of Power Module A’s Gate Driver Interface module.

Hex Value: 0080HSug. Var. Name: GDIA@Access: Read onlyUDC Error Code: N/ALED: N/A

Charge Fault Bit 8

The Charge Fault A bit is set if a charge bus time-out fault occurs in Power Module A. (refer also to register 202/1202, bit 6).

Hex Value: 0100HSug. Var. Name: CHGA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase U Loss Bit 9

The Phase U Loss bit is set if AC line phase U is lost.

Hex Value: 0200HSug. Var. Name: U_PL@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V Loss Bit 10

The Phase V Loss bit is set if AC line phase V is lost.

Hex Value: 0400HSug. Var. Name: V_PL@Access: Read onlyUDC Error Code: N/ALED: N/A


Power Device Status Register (Continued) 204/1204

Phase W Loss Bit 11

The Phase W Loss bit is set if AC line phase W is lost.

Hex Value: 0400HSug. Var. Name: W_PL@Access: Read onlyUDC Error Code: N/ALED: N/A

Over Temperature A Bit 12

The Over Temperature A bit is set if an over temperature fault or warning occurs in Power Module A.

Hex Value: 1000HSug. Var. Name: OTA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase U Current Sharing A Bit 13

The Phase U Current Sharing A bit is set if Power Module A is not carrying its share of the phase U current.

Hex Value: 2000HSug. Var. Name: U_SHRA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V Current Sharing A Bit 14

The Phase V Current Sharing A bit is set if Power Module A is not carrying its share of the phase V current.

Hex Value: 4000HSug. Var. Name: V_SHRA@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase W Current Sharing A Bit 15

The Phase W Current Sharing A bit is set if Power Module A is not carrying its share of the phase W current.

Hex Value: 8000HSug. Var. Name: W_SHRA@Access: Read onlyUDC Error Code: N/ALED: N/A


Interlock Register 205/1205

The Interlock tests are executed whenever bit 0 or bit 2 of register 100/1100 is set. The first problem detected will cause the corresponding bit in the Interlock Register to set. If any of these bits are set, it will prevent the voltage loop from running.

Configuration Parameters Not Loaded Bit 0

The Configuration Parameters Not Loaded bit is set if the configuration parameters have not been downloaded into the UDC module from the Programming Executive or if the parameters are outside of acceptable limits.

Hex Value: 0001HSug. Var. Name: IC_CNF@Access: Read onlyUDC Error Code: N/ALED: N/A

Gains Not Loaded Bit 1

The Gains Not Loaded bit is set if the following pre-defined local tunables are zero or if a UDC task containing these variables has not been loaded to the PMI:

Hex Value: 0002HSug. Var. Name: IC_GAIN@Access: Read onlyUDC Error Code: N/ALED: N/A

C_E6%GIT_E1%VDC_A% L_E6%IST_E1%VDC_FF%OVT_E0%VDC_KD%UVT_E0%VDC_WCO%.

See Appendix B for a description of these variables.

RPI Missing Bit 2

The RPI Missing bit is set if the Run Permissive input on the Rectifier’s Resolver & Drive I/O module is not on.

Hex Value: 0004HSug. Var. Name: IC_RPI@Access: Read onlyUDC Error Code: N/ALED: N/A

See register 201/1201, bit 0 for further information.

Faults Need Reset Bit 3

The Faults Need Reset bit is set if previous faults (register 202/1202) have not been cleared.

Hex Value: 0008HSug. Var. Name: IC_FLT@Access: Read onlyUDC Error Code: N/ALED: N/A


Interlock Register (Continued) 205/1205

Rising Edge Required Bit 4

The Rising Edge Required bit is set if a rising edge is not detected on a command bit in register 100/1100.

Hex Value: 0010HSug. Var. Name: IC_RISE@Access: Read onlyUDC Error Code: N/ALED: N/A

This interlock bit will be set if the application task has set the Fault Reset bit (register 100/1100, bit 8) but has not cleared and then re-enabled any command bits.

More Than One Request Bit 5

The More Than One Request bit is set if more than one operating mode is requested at a time in register 100/1100 (bits 0, 1, 2).

Hex Value: 0020HSug. Var. Name: IC_MORE@Access: Read onlyUDC Error Code: N/ALED: N/A

Pre-charge Not Closed Bit 6

The Pre-charge Not Closed bit is set if VDC_RUN@ (100/1100, bit 0) is set but the pre-charge contactor has not been closed by the PMI Processor.

Hex Value: 0040HSug. Var. Name: IC_PCHG@Access: Read onlyUDC Error Code: N/ALED: N/A

GDI Mismatch Bit 8

The GDI Mismatch bit is set if, when turning on the Rectifier, the number of Gate Driver Interface (GDI) modules in the rack does not match the number configured or the GDI modules have been placed incorrectly in the rack.

Hex Value: 0100HSug. Var. Name: IC_GDI@Access: Read onlyUDC Error Code: N/ALED: N/A

The GDI Mismatch bit is also set if, when turning on the bridge test, a power module has not been selected for the test (bit 10, 11, or 12 in register 100/1100) or the incorrect power module has been selected. (e.g., Power Module C has been selected, but the Rectifier contains only two power modules.)

Refer to the PMI Rack instruction manual for the correct module placement.

Incompatible PMI Backplane Bit 9

The Incompatible PMI Backplane bit is set if the PMI rack contains an incorrect backplane (e.g., B/M O-60003).

Hex Value: 0200HSug. Var. Name: IC_IPBP@Access: Read onlyUDC Error Code: N/ALED: N/A


Interlock Register (Continued) 205/1205

VDC Not Allowed Bit 11

The VDC Not Allowed bit is set if the bridge test is requested and VDC is greater than 10V.

Hex Value: 0800HSug. Var. Name: IC_VDC@Access: Read onlyUDC Error Code: N/ALED: N/A

DC Bus Voltage (Volts) Register 206/1206

The DC Bus Voltage register contains the measured DC bus voltage. The displayed value is scaled in volts.

Sug. Var. Name: VDC_FB%Units: VoltsRange: N/AAccess: Read only

DC Bus Current (Amps) Register 207/1207

The DC Bus Current (Amps) register contains the measured current in the DC bus. The value is scaled in amps times 10. For example, 50.1 amps is represented as 501.

Sug. Var. Name: IDC_FB%Units: Amps ∗ 10Range: N/AAccess: Read only

Ground Current Feedback (Amps) Register 208/1208

The Ground Current Feedback (Amps) register contains the measured RMS ground current. This value is scaled in amps times 10. For example, 50.1 amps is represented as 501.

Sug. Var. Name: GI_FB%Units: Amps ∗ 10Range: N/AAccess: Read only

This value can be used to determine at what level to set the ground current warning threshold (tunable variable GIT_E1%).

Voltage Feedback (Volts RMS) Register 209/1209

The AC Voltage Feedback register contains the RMS line voltage. The value is scaled in RMS volts.

Sug. Var. Name: VAC_FB%Units: RMS voltsRange: N/AAccess: Read only

AC Current Feedback (Amps RMS) Register 210/1210

The AC Current Feedback (Amps RMS) register contains the measured RMS motor current. The value is scaled in amps times 10. For example, 50.1 amps would be represented as 501.

Sug. Var. Name: IAC_FB%Units: Amps ∗ 10Range: N/AAccess: Read only

The current may be flowing from the AC line (motoring quadrants) or flowing to the AC line (regenerating quadrants).


VAR Feedback (Volts * Amps) Register 211/1211

The VAR Feedback register contains the volt-amperes reactive (VARS) produced by the Rectifier in response to the reference in register 103/1103. The value is scaled in VARS divided by 1000. For example, 10,000 VARS (10 KVARS) is displayed as 10.

Sug. Var. Name: VAR_FB%Units: VARS/1000Range: N/AAccess: Read only

Iq Feedback (Amps) Register 212/1212

The Iq Feedback register contains the Iq component of the current feedback. Iq is the current that supplies the DC bus. The value is normalized to the configured current limit parameter (i.e., 4095 = current limit).

Sug. Var. Name: IQ_FB%Units: CountsRange: +/-4095Access: Read only

Id Feedback (Amps) Register 213/1213

The Id Feedback register contains the Id component of the current feedback. Id is the reactive current component that can be used to produce a leading power factor. The value is normalized to the configured current limit parameter (i.e., 4095 = current limit).

Sug. Var. Name: ID_FB%Units: CountsRange: +/- 4095Access: Read only

User Analog Input Register 214/1214

The User Analog Input register contains the DC bus current as measured from the Resolver Feedback connector on the Resolver & Drive I/O module. It is scaled as follows:

Sug. Var. Name: ANA_IN%Units: Counts (Volts)Range: -2048 to +2047

(-10V to +10V)Access: Read only

• Single Power Module:2047 counts = 641 Amps (319 counts / 100 amps)

• Double Power Module:2047 counts = 1282 Amps (160 counts / 100 amps)

• Triple Power Module:2047 counts = 1923 Amps (106 counts / 100 amps)

Selected Variable Register 219/1219

The Selected Variable register contains the value of the actual variable that is selected for display on PMI meter port 4. This allows monitoring of data in the UDC module that is normally only available in the PMI rack.

Sug. Var. Name: SEL_VAR%Units: N/ARange: N/AAccess: Read only

Refer to chapter 2 for more information on displaying variables on the PMI Processor’s meter ports.


Parallel Power Module B Status Register 220/1220

The bits in the Parallel Power Module B Status register indicate the status of the power devices in Power Module B. This register is used only when two or more power modules are connected in parallel.

If an IOC (overcurrent) fault is detected, the associated phase upper and lower status bits are set. If a phase DSAT (shoot-through) fault is detected, the associated phase status bits are set and the Intelligent Power Module bit, IPUB@, is set.

Phase U-Upper IOC B Bit 0

The Phase U-Upper B status bit is set if an IOC or DSAT fault occurs in Power Module B’s phase U, upper power device.

Hex Value: 0002HSug. Var. Name: U_UPB@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V-Upper IOC B Bit 1

The Phase V-Upper IOC B bit is set if an IOC or DSAT fault occurs in Power Module B’s phase V, upper power device.

Hex Value: 0002HSug. Var. Name: V_UPB@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase W-Upper IOC B Bit 2

The Phase W-Upper B status bit is set if an IOC or DSAT fault occurs in Power Module B’s phase W, upper power device.

Hex Value: 0004HSug. Var. Name: W_UPB@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase U-Lower IOC B Bit 3

The Phase U-Lower IOC B status bit is set if an IOC or DSAT fault occurs in Power Module B’s phase U, lower power device.

Hex Value: 0008HSug. Var. Name: U_LOB@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V-Lower IOC B Bit 4

The Phase V-Lower B status bit is set if an IOC or DSAT fault occurs in Power Module B’s phase V, lower power device.

Hex Value: 0010HSug. Var. Name: V_LOB@Access: Read onlyUDC Error Code: N/ALED: N/A


Parallel Power Module B Status Register (Continued) 220/1220

Phase W-Lower IOC B Bit 5

The Phase W-Lower B status bit is set if an IOC or DSAT fault occurs in Power Module B’s phase W, lower power device.

Hex Value: 0020HSug. Var. Name: W_LOB@Access: Read onlyUDC Error Code: N/ALED: N/A

Intelligent Power Module B Bit 6

The Intelligent Power Module B bit is set to indicate that a DSAT (shoot-through) fault has occurred in Power Module B.

Hex Value: 0040HSug. Var. Name: IPUB@Access: Read onlyUDC Error Code: N/ALED: N/A

Bits 0 - 5 of this register should be checked to identify the device in which the fault occurred.

GDI Fault B Bit 7

The GDI Fault B bit is set if a fault is detected in the power supply of Power Module B’s Gate Driver Interface module.

Hex Value: 0080HSug. Var. Name: GDIB@Access: Read onlyUDC Error Code: N/ALED: N/A

Charge Fault B Bit 8

The Charge Fault B bit is set if a charge bus time-out fault occurs in Power Module B (refer also to register 202/1202, bit 6).

Hex Value: 0100HSug. Var. Name: CHGB@Access: Read onlyUDC Error Code: N/ALED: N/A

Over Temperature B Bit 12

The Over Temperature B bit is set if an over temperature fault or warning occurs in Power Module B.

Hex Value: 1000HSug. Var. Name: OTB@Access: Read onlyUDC Error Code: N/ALED: N/A


Parallel Power Module B Status Register (Continued) 220/1220

Phase U Current Sharing B Bit 13

The Phase U Current Sharing B bit is set if a Power Module B is not carrying its share of the phase U current.

Hex Value: 2000HSug. Var. Name: U_SHRB@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V Current Sharing B Bit 14

The Phase V Current Sharing B bit is set if Power Module B is not carrying its share of the phase V current.

Hex Value: 4000HSug. Var. Name: V_SHRB@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase W Current Sharing B Bit 15

The Phase W Current Sharing B bit is set if Power Module B is not carrying its share of the phase W current.

Hex Value: 8000HSug. Var. Name: W_SHRB@Access: Read onlyUDC Error Code: N/ALED: N/A

Parallel Power Module C Status Register 221/1221

The bits in the Parallel Power Module C Status register indicate the status of the power devices in power Module C. This register is used only when two or more power Modules are connected in parallel.

If an IOC (overcurrent) fault is detected, the associated phase upper and lower status bits are set. If a phase DSAT (shoot-through) fault is detected, the associated phase status bits are set and the Intelligent Power Module bit, IPUC@, is set.

Phase U-Upper IOC C Bit 0

The Phase U-Upper C status bit is set if an IOC or DSAT fault occurs in Power Module C’s phase U, upper power device.

Hex Value: 0002HSug. Var. Name: U_UPC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V-Upper IOC C Bit 1

The Phase V-Upper IOC C bit is set if an IOC or DSAT fault occurs in Power Module C’s phase V, upper power device.

Hex Value: 0002HSug. Var. Name: V_UPC@Access: Read onlyUDC Error Code: N/ALED: N/A


Parallel Power Module C Status Register (Continued) 221/1221

Phase W-Upper IOC C Bit 2

The Phase W-Upper C status bit is set if an IOC or DSAT fault occurs in Power Module C’s phase W, upper power device.

Hex Value: 0004HSug. Var. Name: W_UPC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase U-Lower IOC C Bit 3

The Phase U-Lower IOC CC status bit is set if an IOC or DSAT fault occurs in Power Module C’s phase U, lower power device.

Hex Value: 0008HSug. Var. Name: U_LOC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V-Lower IOC C Bit 4

The Phase V-Lower C status bit is set if an IOC or DSAT fault occurs in Power Module C’s phase V, lower power device.

Hex Value: 0010HSug. Var. Name: V_LOC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase W-Lower IOC C Bit 5

The Phase W-Lower C status bit is set if an IOC or DSAT fault occurs in Power Module C’s phase W, lower power device.

Hex Value: 0020HSug. Var. Name: W_LOC@Access: Read onlyUDC Error Code: N/ALED: N/A

Intelligent Power Module C Bit 6

The Intelligent Power Module C bit is set to indicate that a DSAT (shoot-through) fault has occurred in Power Module C.

Hex Value: 0040HSug. Var. Name: IPUC@Access: Read onlyUDC Error Code: N/ALED: N/A

Bits 0 - 5 of this register should be checked to identify the device in which the fault occurred.


Parallel Power Module C Status Register (Continued) 221/1221

GDI Fault C Bit 7

The GDI Fault C bit is set if a fault is detected in the power supply of Power Module C’s Gate Driver Interface module.

Hex Value: 0080HSug. Var. Name: GDIC@Access: Read onlyUDC Error Code: N/ALED: N/A

Charge Fault C Bit 8

The Charge Fault C bit is set if a charge bus time-out fault occurs in Power Module C (refer also to register 202/1202, bit 6).

Hex Value: 0100HSug. Var. Name: CHGC@Access: Read onlyUDC Error Code: N/ALED: N/A

Over Temperature C Bit 12

The Over Temperature C bit is set if an over temperature fault or warning occurs in Power Module C.

Hex Value: 1000HSug. Var. Name: OTC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase U Current Sharing C Bit 13

The Phase U Current Sharing C bit is set if a Power Module C is not carrying its share of the phase U current.

Hex Value: 2000HSug. Var. Name: U_SHRC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase V Current Sharing C Bit 14

The Phase V Current Sharing C bit is set if Power Module C is not carrying its share of the phase V current.

Hex Value: 4000HSug. Var. Name: V_SHRC@Access: Read onlyUDC Error Code: N/ALED: N/A

Phase W Current Sharing C Bit 15

The Phase W Current Sharing C bit is set if Power Module C is not carrying its share of the phase W current.

Hex Value: 8000HSug. Var. Name: W_SHRC@Access: Read onlyUDC Error Code: N/ALED: N/A


Power-Up Self-Calibration Faults

,I DQ\ RI WKH SRZHU�XS VHOI�FDOLEUDWLRQ IDXOWV RFFXUV� UHSODFH WKH $& 3RZHU 7HFKQRORJ\PRGXOH LQ WKH 6%�� 5HFWLILHU©V 30, UDFN� 1RWH WKDW Uegister 202, bit 11 (FLT_PTM@) will also be set.

Run Time AC Power Technology Module Faults

Diagnostic Fault Code Register 222/1222

The Diagnostic Fault Code register displays an error code to help diagnose the cause of a problem reported in other registers.�

Note that this register is available for monitoring only. It cannot be referenced in an application task.

Sug. Var. Name: DIAG_FLT%Units: N/ARange: N/AAccess: Read only

Code Fault

1 D/A high voltage error (+10% out of tolerance)

2 D/A low voltage error (-10% out of tolerance)

3 Torque current loop proportional gain not within calibration limits

4 Flux current loop proportional gain not within calibration limits

5 Flux current loop integrator time constant not within calibrated limits

6 Torque current loop integrator time constant not within calibrated limits

7 Harmonic injection error

8 Harmonic DAC limit error

9 Harmonic DAC low error

10 Harmonic DAC range error

11 Programmable current limit fault

12 VAC integrator error

13 A/D converter interrupt error

14 Pulse Width Modulator frequency error

15 DC bus current not zero at power-up.

16 Phase U current not zero at power-up.

17 Phase W current not zero at power-up.

Code Fault Description/Action

20 Power supply monitor tripped Power supply level on the AC Power Technology module (ACPTM) out of tolerance.

Replace the ACPTM, PMI rack, and/or Power Supply.

21 AC power technology watchdog time-out

ACPTM watchdog timer has expired.



Run Time AC Power Technology Module Faults (Continued)

Charge Fault Diagnostics

Diagnostic Fault Code Register (Continued) 222/1222

Code Fault Description/Action

22 A/D interrupt overrun An interrupt from the ACPTM was detected before the previous interrupt was processed.


23 Gate power test 1 fault Gate power is on when the MCR is off and Gate Enable is on.

Replace the ACPTM.

24 Gate power test 2 fault Gate Power is on when MCR is off and Gate Enable is on.

Replace the Resolver Interface.

25 Gate power test 3 fault Gate power is on when the MCR is off and Gate Enable is on.

Replace the ACPTM.

26 Gate power loss Gate Power is off when MCR is on and Gate Enable is on. This test is done on a timed basis whenever the drive is on.

Replace the ACPTM.

Code Fault Description

100 Pre-charge closed The pre-charge is closed when commanded to be open.

101 Pre-charge did not close The pre-charge did not close when commanded.

102 Pre-charge opened (SW) Software has detected that the pre-charge opened when commanded to be closed.

103 Pre-charge did not open The pre-charge did not open when commanded.

104 Pre-charge opened (ACPTM) The AC Power Technology module detected that the pre-charge opened while in run.

105 Pre-charge Opened (GDI) The Gate Driver Interface module detected that the pre-charge opened while in run.


3.6 Application Registers (Registers 300-599, Every Scan) (Registers 1300-1599, Every Nth Scan)

The application registers are used to pass application-specific data between the AutoMax Processor and the UDC module.

Memory is allocated for a maximum of 600 application registers. There are 300 registers that can be used every scan (registers 300-599) and 300 registers that can be used every Nth scan (registers 1300-1599). “N” is defined in register 2001. Note that the status of application registers is not retained after a STOP ALL.

Application registers 300-599 can be used every scan of UDC tasks. Registers within this range written to by a UDC task are updated by the UDC operating system from its local memory to dual port memory after each task is run. Registers within this range written to by an AutoMax task are read by the UDC operating system from dual port memory and copied into the UDC local memory at the beginning of each scan in order to have a consistent context for evaluation. See figure 3.1.

Note that the same bits or registers must not be written to (and used as outputs) by both an AutoMax task and a UDC task.

Application registers 1300-1599 can be used every Nth scan of the UDC task. Nth scan registers should be used when it is necessary to synchronize one or more UDC tasks to an AutoMax task.

!ATTENTION: If you use double integer variables, you must implement a software handshake between the transmitter and the receiver to ensure that both the least significant and the most significant 16 bits have been transmitted before they are read by the receiving application program. Failure to observe this precaution could result in bodily injury or damage to equipment.

Figure 3.1 – UDC Task Scan

Input A Run A Output A Input B Run B Output B

UDC Scan*

Feedback F

rom P

MI

Com

mand to P

MI

*Task B can act on Task A outputs within a scan.

Latch “every scan”registers that areinputs to task B

Write “every scan”registers that areoutputs from task A

Latch “every scan”registers that areinputs to task A

Write “every scan”registers that areoutputs from task B


The registers within this range (1300-1599) that are written to by a UDC task are updated by the UDC operating system from its local memory to dual port memory at the end of the scan that occurs before the Nth scan (N-1). At that time, an interrupt will be generated by the UDC operating system to indicate that new data has been written to the dual port memory. Refer to the 2000-series registers for more information on interrupts. An AutoMax task must have defined a hardware EVENT in order to be able to respond to an interrupt from the UDC module. Registers within this range that are written to by an AutoMax task are read by the UDC operating system from dual port memory and copied into the UDC local memory at the beginning of the Nth scan. See figure 3.2.

The following data types can be defined in the application register area: boolean (bit), integer (16 bits), double integer (32 bits), and real (32 bits). Because of the way in which read and write operations occur in the UDC dual port memory, however, the programmer must assign boolean variables carefully within pairs of 16-bit registers.

The UDC operating system generally operates on the amount of memory called for by the data type, e.g., when it is requested to write to a 16-bit (integer) value, it writes only to those specific 16 bits. However, in the case of boolean variables, the UDC operating system always operates on 32 bits at a time. It is not possible for the operating system to write to only one bit within a register. The remaining 31 bits in the register pair will be written over as well, possibly resulting in corrupted data.

Within any pair of 16-bit registers beginning on an even number boundary, i.e., registers 300 and 301, 302 and 303 (but not registers 301 and 302), all boolean variables must be either inputs or outputs. If there are no bits assigned within a particular register pair, then one 16-bit register can be an output and the other 16-bit register can be an input, or both can be inputs or outputs. Alternatively, the entire register pair can be defined as a real or double integer value.

Note that if you are referencing a 32-bit value (real or double integer) in the UDC dual port from an AutoMax task, the operation is being performed by the AutoMax Processor, which operates on 16 bits of data at a time. In such a situation, you must employ some form of software handshaking in the AutoMax task to ensure that both the upper and lower order 16 bits represent the current value of the variable. This is required for 32-bit values in the “every” scan register range. It is possible to use software “flags” to indicate that data can be read. It is also possible to read the data multiple times (typically three times) and compare the values.


Figure 3.2 – Nth Scan Interrupts

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3.7 UDC Module Test I/O Registers (Registers 1000-1017)

This view is used to configure the UDC module’s Test Switch Inputs Register and the Meter Port Setup Registers.

3.7.1 UDC Module Test Switch Inputs Register (Register 1000)

This view is used to configure the register that displays the status of the test switches and LED indicators on the UDC module. Writing to this register will not change the state of the LEDs. The status of this register is retained during a Stop All.

UDC Test Switch Inputs Register 1000

Pushbutton Input Bit 0

The Pushbutton Input bit is on when the UDC’s pushbutton is pressed.

Hex Value: 0001HSug. Var. Name: UDC_PB@Access: Read onlyUDC Error Code: N/ALED: N/A

Switch Up Input Bit 1

The Switch Up Input bit is on when the test switch is in the up position.

Hex Value: 0002HSug. Var. Name: SWIT_UP@Access: Read onlyUDC Error Code: N/ALED: N/A

Switch Down Input Bit 2

The Switch Down Input bit is on when the test switch is in the up position.

Hex Value: 0004HSug. Var. Name: SWIT_DN@Access: Read onlyUDC Error Code: N/ALED: N/A

Operating System OK LED Bit 8

The Operating System OK LED bit shows the status of the Operating System OK LED on the UDC module ( 0 = OFF; 1 = ON).

Hex Value: 0100HSug. Var. Name: N/AAccess: Read onlyUDC Error Code: N/ALED: OS OK on UDC

module


UDC Test Switch Inputs Register (Continued) 1000

COMM A OK LED Bit 9

The COMM A OK LED bit shows the status of the COMM A OK LED on the UDC module ( 0 = OFF; 1 = ON).

Hex Value: 0200HSug. Var. Name: N/AAccess: Read onlyUDC Error Code: N/ALED: COMM A OK

on UDC module

Drive A Fault LED Bit 10

The Drive A Fault LED bit shows the status of the Drive A Fault LED on the UDC module ( 0 = OFF; 1 = ON).

Hex Value: 0400HSug. Var. Name: N/AAccess: Read onlyUDC Error Code: N/ALED: DRV A FLT

on UDC module

COMM B OK LED Bit 11

The COMM B OK LED bit shows the status of the COMM B OK LED on the UDC module ( 0 = OFF; 1 = ON).

Hex Value: 0800HSug. Var. Name: N/AAccess: Read onlyUDC Error Code: N/ALED: COMM B OK

on UDC module

Drive B Fault LED Bit 12

The Drive B Fault LED bit shows the status of the Drive B Fault LED on the UDC module ( 0 = OFF; 1 = ON).

Hex Value: 1000HSug. Var. Name: N/AAccess: Read onlyUDC Error Code: N/ALED: DRV B FLT

on UDC module


3.7.2 UDC Module Meter Port Setup Registers (Registers 1000-1017)

Registers 1001-1017 are used to configure the UDC module’s meter ports. This configuration determines what variables from the UDC module’s dual port memory are to be displayed on the meter ports at the end of the UDC scan. At system power-up, the output values of the ports are reset to zero.

To map a UDC variable to a specific meter port at power-up, refer to table 3.3 and use the following procedure. Note that the setup register configurations are retained during a Stop All.

For each meter port:

Step 1. Place the register number of the variable you wish to display in the appropriate Variable Register Number register.

Step 2. If an individual bit of the register is to be displayed, enter it in the Bit Number register as 100 (bit 00) to 115 (bit 15).

Step 3. Place the value (maximum 32767) that will represent +10V in the Maximum Value register.

Step 4. Place the value (minimum -32768) that will represent -10V in the Minimum Value register.

Step 5. Set register 1001 (Initiate Change in Setup) equal to a non-zero value to store the new setup register configurations in memory.

The UDC module’s meter ports are updated once per scan once the UDC task is running and CCLK is on. They are updated every 5 milliseconds when CCLK is off.

UDC meter ports can also be set up on-line using the “Setup UDC” selection from the Monitor menu as described in the AutoMax Programming Executive instruction manual. This setup is valid only until there is a power cycle, in which case the meter ports default to outputting zero voltage and the UDC Setup screen is cleared on power-up.

Refer to the UDC module instruction manual (S-3007) for more information about the UDC module’s meter ports.

Table 3.7 – UDC Module Meter Port Setup Registers

UDC Module Meter PortSetup Registers

MeterPort 1

MeterPort 2

MeterPort 3

MeterPort 4

Change Setup Register 1001 1001 1001 1001

Variable Register Number Register 1002 1006 1010 1014

Bit Number Register 1003 1007 1011 1015

Maximum Value Register 1004 1008 1012 1016

Minimum Value Register 1005 1009 1013 1017


3.7.2.1 Resolution of Meter Port Data

For meter ports, the output values will be clamped at the outside (+/-10V) limits. Note that if you select to display a data range that is narrower than the actual range of the data, your output values will not change until the value returns to within the range you selected to display. In other words, data is being updated at the rate described above, but the actual output voltage may not change.

If the actual data being sent to the meter port is significantly smaller than the upper and lower limits assigned by the programmer, the effective resolution of the 8-bit D/A circuit (1 part in 255) will degrade. To calculate the step change indicated on the meter port, calculate the sum or the absolute values of the upper and lower limits (the entire range of possible values) assigned to the port. Then scale this number by 255 in order to determine the minimum step change that will cause the D/A output to change.

For example, suppose the programmer sets the +10V and -10V limits at +4095 and -4095, respectively, but the actual value varies only between +1024 and -1024. Then:

8190/255 = 32 counts

This means that although the actual data is being updated, the meter port output will change only when the data changes by 32 or more counts. This level of granularity might be acceptable if the range of the data were actually 8190 counts, but might not be acceptable if the data range is only 4095 counts. If the programmer had assigned the limits +/- 1024, the D/A output step change would be only 8 counts: 2048/255 = 8.

Initiate Change in Setup Register 1001

Set this register equal to a non-zero value to store the new setup register configurations in UDC memory. You must use this register whether you are changing the meter port setup via an application task or via I/O Monitor.

Sug. Var. Name: N/AUnits: N/ARange: N/AAccess: Read/Write


Meter Port 1

UDC Module Meter Port 1 Register Number Register 1002

UDC register number (0 - 2044) to be mapped to meter port 1. Sug. Var. Name: N/AUnits: N/ARange: N/AAccess: Read/Write

UDC Module Meter Port 1 Bit Number Register 1003

Bit number of the UDC register specified in register 1002 that is to be mapped to port 1. Enter a value of 100 (bit 00) to 115 (bit 15) as required. Enter a value of zero if all of the register’s bits are to be displayed.


UDC Module Meter Port 1 Maximum Value Register 1004

Set this register to the number that will represent +10V. The maximum allowable value is 32767.


UDC Module Meter Port 1 Minimum Value Register 1005

Set this register equal to the number that will represent -10V. The minimum allowable value is -32768.



Meter Port 2













Meter Port 3













Meter Port 4













3.8 Interrupt Status and Control Registers (Registers 2000-2047)

This view is used to configure registers that control the operation of interrupts to a task on an AutoMax Processor in the rack and to enable CCLK in the rack. These registers are used for Drive A and B. Only one UDC task should write to these registers. Note that the status of these registers is not retained after a Stop All.

Interrupt Status Control Register 2000

The Interrupt Status Control register contains the following information. Only bit 6 can be written to by the user. All other bits are read only.

Sug. Var. Name: UDC_ISCR%Units: N/ARange: N/AAccess: See individual

bits

Interrupt Line Identification Bit 0


Interrupt Line Identification Bit 1


Interrupt Allocated Bit 2


Interrupt Generated This Scan Bit 4



Interrupt Status Control Registers (Continued) 2000

CCLK Counting Bit 5


Enable CCLK on the Multibus Backplane Bit 6

CCLK must be enabled in the rack for the UDC module to execute its task(s) and communicate synchronously with the PMI.

Hex Value: 0001HSug. Var. Name: N/AAccess: Read/WriteUDC Error Code: N/ALED: N/A

Only one module per rack should enable CCLK. If CCLK is enabled on multiple modules in the rack, an overlap error will result (error code 38). Other modules that can enable CCLK include the M/N 57C409, 57C421, and the 57C411.

The UDC module uses CCLK to determine when it should run its tasks. CCLK is also used as the time reference for all UDC modules in the rack so that they are all synchronized to start at specific time periods. If interrupts to the AutoMax Processor are required, register 2001 must be set to the desired value before CCLK is enabled.

Interrupt Enabled Bit 7

The Interrupt Enabled bit, when set by the operating system, indicates that a hardware EVENT has been defined in an AutoMax task.


No other programming is required for the UDC operating system to generate an interrupt in the interval defined in register 2001.

Interrupt Status Bit 15

The Interrupt Status bit is set to indicate that an interrupt is being generated at this time.



Scans Per Interrupt Register 2001

The Scans Per Interrupt register contains the number of times a UDC task is to be scanned between updates of the Nth scan application registers.

Sug. Var. Name: SPI%Units: N/ARange: See below.Access: Read/Write

Note that you must write the desired value to this register before you turn on CCLK. The default value is zero (i.e., not applicable because an interrupt is not being used but is updated each scan). One is a permissible value. If a hardware EVENT is defined in an AutoMax application task, this register will also specify when the interrupt occurs, i.e., every Nth scan. See chapter 4 for more information on interrupts.


Application Programming for DPS Drive Control 4-1

CHAPTER 4Application Programming

for DPS Drive Control

Distributed Power Drive products are sold only as part of engineered systems. The application programming required for each engineered system is developed in response to each customer’s specifications. Information in this chapter is general enough to apply to most engineered systems; however, implementation details may vary. Always refer to your wiring diagrams for specific information about your engineered system.

4.1 AutoMax Tasks

AutoMax tasks are used to implement safety interlocks, coordinate multiple UDCs, and collect data from UDC modules in the rack. They can access all common memory and I/O in the AutoMax rack, including the dual port memory in the UDC module. AutoMax drive control tasks are generally written in control blocks and PC/Ladder Logic language. Typically these tasks control the Drive Control register (100/1100) and the I/O Control register (101/1101). AutoMax tasks can access registers in the UDC’s dual port memory in the same way as tasks on the UDC module itself, i.e., by declaring them COMMON.

4.2 UDC Tasks

UDC tasks operate on registers in the UDC dual port memory described in chapter 3, as well as on local task-specific variables in order to control some application variable (e.g., speed) and to calculate the required reference values for the selected control algorithm. The UDC task is sometimes referred to as an “outer” or “major” control loop. Note, however, that there may be more than one outer loop per task. In this case the control loops are nested, or “cascaded,” within the UDC task.


ATTENTION: Only qualified Rockwell personnel or other trained personnel who understand the potential hazards involved may make modifications to the application tasks. Any modifications may result in uncontrolled machine operation. Failure to observe this precaution could result in damage to equipment and bodily injury.


UDC tasks must be written in the Control Block language, a language designed specifically for drive control. To differentiate them from Control Block tasks written for AutoMax Processors, they must be specified as UDC tasks in the Programming Executive software. Like Control Block tasks on AutoMax Processors, UDC tasks can include a number of BASIC language statements and functions; however, those that allow task suspension or delay are not supported.

UDC tasks are created, compiled, loaded, and monitored in the same way as Control Block tasks for AutoMax Processors. UDC task variables can be monitored, set, tuned, and forced like AutoMax task variables. Note that the UDC module is accessed for monitoring and loading through the serial port on the leftmost AutoMax Processor (or over the DCS-NET network), which is used for all connections to the rack.

Any UDC dual port register that is to be used in a UDC task must be defined as COMMON in the task. Recall that UDC dual port memory registers are either reserved for a specific use such as rail data or available for application-specific purposes to the programmer. Registers that are not specifically identified in one of these two ways in the Programming Executive software or in this instruction manual must not be written to by either the UDC or AutoMax tasks because they are being used by the operating system.

Generally, the common variables on the UDC module are either written to only by AutoMax tasks (“read only” to UDC tasks), or they are written to only by a UDC task (“read only” to AutoMax tasks). The former are typically variables that control an action, e.g., requesting the minor loop to run, and the latter are typically status variables, e.g., indicating the status of the fiber-optic communication link.

UDC tasks can access only the UDC module’s own dual port memory. They cannot access other variables in the rack unless an AutoMax task writes those variable values to the application-specific registers in the UDC dual port.

Figure 4.1 illustrates one UDC task scan..

Figure 4.1 – UDC Task Scan

Input A Run A Output A Input B Run B Output B

UDC Scan*

Feedback F

rom P

MI

Com

mand to P

MI

*Task B can act on Task A outputs within a scan.

Latch “every scan”registers that areinputs to task B

Write “every scan”registers that areoutputs from task A

Latch “every scan”registers that areinputs to task A

Write “every scan”registers that areoutputs from task B


All common input values for the UDC task are first read from the dual port memory and then stored in a local buffer in order to have a consistent context for evaluation. The task is then executed. After the task has been executed, the common output values from the UDC task are written from the local memory buffer to dual port memory.

The only exception to this pattern are the common variables in the “Nth” scan application register area. These registers are updated immediately before every “Nth” scan only, as defined by the user. See section 4.3 and figure 4.3 for more information on “Nth” scan interrupts. See section 4.2.3 for more information on the command and feedback messages.

4.2.1 Typical Structure of a UDC Task

They typical structure of a UDC task is described in the following paragraphs. The first part of the task, described in steps 1 to 4 below, is considered task initialization. This part of the task will only run on the initial scan of the task or on any subsequent re-start.

Step 1. Local and common variable definitions

This section of the task defines names for values internal to the task (LOCALs) and all UDC dual port memory registers used in the task (COMMONs).

Step 2. Pre-defined local tunable variable definitions

This section defines the variables that are used by the PMI for functions such as tuning the control algorithm and calibrating the resolver. The UDC task “skeleton” file in the Programming Executive software includes these local tunable definitions. See section 4.2 and Appendix B for more information.

Step 3. Initialization

a. UDC Meter port set-up: The registers whose values will be output on the UDC Meter Ports are defined here. These registers can also be defined on-line using the Programming Executive software (optional).

b. Scans per update definition: The scans-per-update register (2001 for both drive A and B) is defined to tell the UDC Processor when to update the Nth scan registers, and optionally, also when to interrupt an AutoMax Processor task that has defined a hardware EVENT tied to the UDC’s interrupt register. The AutoMax task can then read from and write to the UDC dual port memory registers, and coordinate with the other tasks in the system (optional).

c. Any other initialization required for the application.

This portion of the task (steps 1 to 3), before the SCAN_LOOP block, only executes the first time that the task is scanned, after a STOP ALL command and subsequent Run command, or after power is recycled to the rack.


Step 4. SCAN_LOOP block/Enabling CCLK

This control block tells the UDC operating system how often to execute the task based on the constant clock (CCLK) signal on the rack backplane. Note that the CCLK signal must be enabled by a task in the rack before any UDC tasks in the rack can b scanned beyond their SCAN_LOOP blocks. Note that CCLK must be enabled again after a STOP ALL in the rack. CCLK is enabled by setting the appropriate “CCLK enable” bit on certain modules in the rack, such as the UDC module, CCLK must be enabled on one module only. If CCLK is enabled on multiple modules in the rack, an overlap error will result (error code 38).

The UDC task runs based on “ticks;” one tick is equal to one 500 ) CCLK interval. The value can range from 1 to 20 ticks.

The programmer must specify how often the task should run in the TICKS parameter of the SCAN_LOOP block in the task itself. The TICKS value represents the number of 500 will occur. In order to calculate this value, both drive A and drive B tasks must be considered together because they execute one immediately following he other (A, then B). See figure 4.1 for more information.

When determining the value to enter, the programmer must consider how long it will take both tasks to actually run, allow some time for processing overhead, and use the resulting value to determine the TICKS value for the SCAN_LOOP block in both the drive A and drive B tasks. The AutoMax Control Block Language manual (J-3676) lists the execution times of the Control Blocks.

For example, if the programmer assigns UDC task A a TICKS parameter of 8 (4 msec), then UDC task B must also have TICKS defined at 8, and both tasks must be able to execute within an 8 tick window of time, or an overlap error will result and all tasks in the rack will stop. If the tick rates do not match, error code 956 will be reported for one or both tasks in the error log; and all tasks in the rack will be stopped.

Note that, unlike Control Block tasks on AutoMax Processors, UDC tasks cannot run on a hardware or software event basis. The EVENT parameter cannot be specified in the SCAN_LOOP block in UDC tasks. This means that there is no time-out for execution of the UDC tasks. If the UDC task is scanned to the SCAN_LOOP block and CCLK is not on, the task will simply wait without timing out.

Note that no other control blocks are permitted before the SCAN_LOOP block. BASIC statements, however, are permitted before the SCAN_LOOP block.

Step 5. Other Control Block and BASIC statements or functions

This portion of the task consists of the logic specifically required for the application. This portion of the UDC task (after the SCAN_LOOP block) is the only part of the task that executes after the initial scan of the task, after a STOP ALL command and subsequent Run command, or after power is cycled to the rack.


Step 6. Motor thermal overload protection

Electronic thermal overload protection for SA3100 drives is normally provided by the THERMAL OVERLOAD block. The following briefly describes how the THERMAL OVERLOAD block works, how to program the block, and what adjustments are possible. Each UDC task must contain a THERMAL OVERLOAD block, unless motor thermal overload protection is provided by a hardware device. See J-3676, the Control Block Language instruction manual, for the structure of the block.

The THERMAL OVERLOAD control block is used to create a model of the temperature in a single device, such as a motor or power module, controlled by a DPS drive and to turn on an alarm when an overload condition exists. The block calculates a rise in temperature based on current feedback. When operating above 100%, if the rise in temperature exceeds the programmed limit, the OVERLOAD output will turn on. After the overload condition is detected, the rise in temperature must return to the 100% or less condition before the drive will be allowed to turn on again.

The operation of the block is programmed through four block input parameters: LIM_BAR, THRESHOLD, TRIP_TIME, and I_FDBK. The value used for LIM_BAR must be the same value entered as the motor overload ratio during drive parameter configuration. The value used for THRESHOLD selects the percent of full load current at which overload is detected. The value used for TRIP_TIME selects the time, in seconds, within which the block must detect an overload after a step from 100% current to LIM_BAR. The main input to the THERMAL OVERLOAD block is I_FDBK. I_FDBK represents current feedback from the PMI in counts (register 211/1211), scaled so that LIM_BAR is 4095 counts.

The main output from the block is OVERLOAD. This boolean block will be turned on when a thermal overload is detected. The OVERLOAD output must be programmed in a Ladder Logic task to turn off the drive when the fault is detected. The block also has an output called CALC_RISE. Current feedback is squared, scaled, passed through a Lag filter, and then written to CALC_RISE.

!ATTENTION: Electronic motor overload protection must be provided for each motor in a Distributed Power Drive application to protect the motor against excessive heat caused by high currents. This protection can be provided by either the THERMAL OVERLOAD software block or an external hardware device. Applications in which a single power module is controlling multiple motors cannot use the THERMAL OVERLOAD software block and must use an external hardware device or devices to provide this protection. Failure to observe this precaution could result in damage to, or destruction of, the equipment.


Consider an example in which LIM_BAR is defined to be 150% of full load current, THRESHOLD is 114%, and TRIP_TIME is 60 seconds. When I_FDBK is at 100%, CALC_RISE will reach a steady state value of 1000

(1002 / 10). With THRESHOLD at 114%, the trip point for CALC_RISE will

be 1300 (1142 / 10). If I_FDBK is at steady state (100%) and then is stepped to 150%, CALC_RISE will integrate up to 1300 in 60 seconds and OVERLOAD will turn on. The OVERLOAD output will stay on until the rise decays to less than 1000. If I_FDBK remains less than 114%, CALC_RISE will remain less than 1300 and OVERLOAD will not turn on.

The rate at which the CALC_RISE block parameter counts up and down is calculated so that a step from 100% to LIM_BAR will turn on the OVERLOAD in TRIP_TIME seconds. If current feedback steps from 100% to a value less than current limit, it will take longer to detect the overload. If I_FDBK is stepped from zero to LIM_BAR, the block will take approximately four times the value of TRIP_TIME to detect the overload.

UL 508C section 56.1.3 specifies that when subjected to 200% of rated full load motor current, the overload protection must trip in at least eight (8) minutes. Because TRIP_TIME is calibrated from 100% to current limit, and TRIP_TIME from zero to current limit is approximately four times longer, the maximum trip time that is allowed is 2 minutes (120 seconds). To meet UL listing requirements, any value greater than 120 seconds is internally limited to 120 seconds.

The National Electric Code (430-32; 1993) requires that thermal overloads protecting motors having a 1.0 service factor trip at load currents no greater than 115% of full load. To meet NEC requirements, the THRESHOLD block parameter has a default value of 114% and should not be set higher.

4.2.2 Local Tunable Variables

A set of local tunable variables with reserved (pre-defined) names is used to store different types of values for use in drive control. For a description of the local tunable variables used in SA3100 drives, refer to Appendix B.

All pre-defined local tunables must be defined in each UDC task (using the BASIC language LOCAL statement) in order for the task to be loaded onto the UDC module. Although all of these variables are not necessarily used in the UDC task itself, they must be defined there in order to provide a mechanism for passing the values between the UDC module and the PMI. For convenience, all these variables are already defined in the UDC task “skeleton” file in the AutoMax Programming Executive, with “HIGH,” “LOW,” “STEP,” and “CURRENT” values.

Your application task must define these variables using the same “HIGH,” “LOW,” and “STEP” limit values as the ones found in the skeleton task. Note that you can only change the “CURRENT” value in the application task. If the UDC operating system needs to clamp a value at the higher or lower limit, it changes the actual value in the task and writes error code 958 into the error log for the task.

The local tunable values can be modified through the application task on the UDC module and by the operator using the Monitor function. See the BASIC language instruction manual, J-3675, for more information on local tunable variables and the WRITE_TUNE statement. Local tunable variables cannot be forced.


Like all tunable values in the AutoMax environment, the values of these UDC task tunables are retained through a power loss. Note that the programmer can also define other local tunable variables for application-specific purposes, but that the total number of all local tunables in a UDC task cannot exceed 127.

4.2.2.1 Calculating Local Tunable Values

Depending upon the type of local tunable variable, the “CURRENT” value, i.e., the value to be used for the next scan of the PMI, can be determined in one of the following ways:

1. Self Tune.

The programmer can request the PMI to generate the values for some of the variables. For example, the programmer can set the resolver calibration command bit in register 101/1101 to cause the PMI to adjust the resolver balance.

When the PMI has generated the values, it sends them to the UDC module over the fiber-optic link. The UDC module stores the values in the corresponding tunable variables. A copy of these values is maintained in the PMI for use in the execution of the control algorithm.

2. Tune values from the Programming Executive software and tasks.

The Monitor function in the Programming Executive allows all local tunables to be modified on-line within the limits defined in the LOCAL statement in the UDC task. Note that this is not recommended for the resolver calibration values because these values can be generated more precisely by the PMI during auto-tuning. At the end of the UDC task scan, the new values are sent to the PMI to be used in the execution of the control algorithm.

3. Enter the desired value into the “CURRENT” field for each LOCAL statement.

The programmer can choose to enter the desired values for local tunables in the “CURRENT” field of the corresponding LOCAL statement or leave them unchanged.

4.2.3 UDC/PMI Task Communication

Coordination between the two PMIs running their respective PMI tasks (drives A and B) and the UDC module running the corresponding UDC tasks is managed through the command and feedback messages sent over the fiber-optic link. The programmer does not control the operating system on the PMI. The timing of the PMI is based on the regulator selected.

A command message is sent to the PMI by the UDC module at the end of every scan of the UDC task. Each message contains the data in registers 100-106/1100-1106, rail data, and the values of the pre-defined local tunables that have changed. Note that some data may be sent over the course of several command messages.

A feedback message is sent to the UDC module by the PMI immediately before the beginning of every scan of the UDC task, i.e., immediately before the CCLK timer expires. Each message contains the data for registers 200-221/1200-1221, as well as any rail data that has changed from the last feedback message.


The exchange of command and feedback register data is synchronized through the use of the constant clock signal (CCLK) on the UDC module as described below. CCLK also enables the coordination of all UDCs in a rack because they will all use the same time base for task execution. Note that all UDC modules in a rack are not required to have the same value in the TICKS parameter of the SCAN_LOOP block in both their tasks. In other words, if the UDC module in slot 6 has TICKS = 10 in its tasks, and the UDC module in slot 7 has TICKS = 20 in its tasks, the tasks on the UDC module in slot 6 will execute twice as often as the tasks on the UDC module in slot 7, but they will execute on the same time basis, i.e., time zero is determined by CCLK timer expiration.

As soon as the UDC module and PMI are connected over the fiber-optic link, the PMI will request its operating system from the UDC module. Recall that the PMI operating system is part of the UDC operating system. As long as the UDC module has its own operating system and parameter object file, it will download to the PMI the correct operating system.

In order for the PMI and the UDC module to be synchronized, the UDC module must have its operating system, parameter object file, and configuration loaded. In addition, CCLK must be turned on in the AutoMax rack.

If the UDC tasks are already loaded onto the UDC module when the PMI requests its operating system, the UDC module will also send information about when the PMI should send feedback register data required by the UDC task(s). This ensures that the data is measured or calculated as close as possible to the time it is needed in order to ensure it is as current as possible for the next scan of the UDC task(s).

The UDC operating system determines the feedback register message timing required by examining the SCAN_LOOP block in each UDC task so that the feedback will arrive at the UDC module just before it is needed. For example, if the TICKS parameter value in the SCAN_LOOP block were 10, feedback data would be needed by the UDC module immediately before 10 x 500 µsec time expires.

At first, when the UDC module and PMI(s) are powered up and connected via the fiber-optic link, their system clocks are not synchronized. In order for the PMI and UDC module to be synchronized to the same clock signal for communicating command and feedback data on a regular and predictable basis, an AutoMax task must turn on the CCLK signal in the rack. Until CCLK is turned on, command and feedback messages are sent periodically, but not on a predictable basis.

CCLK can be turned on by setting the appropriate bit in UDC register 2000 (the interrupt status and control register for both A and B drive tasks), or by setting a bit in another module that can turn on CCLK. Only one module in the rack must turn on CCLK. Note that after a STOP ALL occurs in the rack, CCLK will be disabled and must be re-enabled again in order for UDC tasks to go into run. See figure 4.3 at the end of this chapter for the typical data flow between the UDC module and the PMI.

To verify that communication between the UDC module and the PMI is resulting in up-to-date feedback data, it is recommended that the drive’s run permissive logic include the CCLK synchronized status bit (register 200/1200, bit 14, CCLK_OK@) and the communication lost fault bit (register 202/1202, bit 15, FLT_COM@) as shown in figure 4.2.


Refer to the individual bit descriptions in this manual for more information.

4.3 AutoMax Processor Task and UDC Task Coordination

Recall that all tasks running on AutoMax Processors have access to the UDC dual port registers, but that UDC tasks can only access those common variables that represent registers in their own dual port memory. Task coordination between the UDC module and the AutoMax Processor is generally handled through periodic hardware interrupts generated by the UDC module. An AutoMax task needs to define a hardware “event” that will trigger some action by an AutoMax task, using the BASIC statement EVENT. The EVENT statement must reference the hardware interrupt status and control register ISCR% (register 2000 in the UDC dual port memory).

Although the UDC operating system itself actually causes the interrupt, a task in the rack (AutoMax or UDC) must write to the scans per update register in the UDC dual port (register 2001) in order to define the number of UDC task scans between updates of the Nth scan application registers (1300-1599), and between hardware interrupts. See figure 3.2 for more information.

Note that the register values being latched on every Nth scan provide a consistent context for evaluation of Control Block statements, but that BASIC statements in UDC tasks read and write data immediately: that is, they do not read from and write to a local buffer. Referencing the same common values in both Control Block and BASIC statements in one task can result in errors.

Figure 4.2 – Recommended Run Permissive Logic

CCLK_OK@ COM_FLT@ RUN_PERM@

RUN_PERM@

StartPermissive

Logic


Figure 4.3 – Data/Time Flow for UDC Module and PMI

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On-Line Operation 5-1

CHAPTER 5On-Line Operation

The ON LINE! command in the System Configurator and the Task Manager applications allows you to access options such as loading, running, and monitoring tasks in the AutoMax rack. All of the options are described in detail in the AutoMax Programming Executive instruction manual.

The following sections provide a summary of some of the options as applied to the UDC module and UDC tasks. Note that the operating systems must be loaded onto the Processor modules and UDC modules in the AutoMax rack before attempting to use any of the on-line options.

5.1 Loading the UDC Module’s Operating System

The UDC module requires an operating system as well as the AutoMax Processor. The operating system can be loaded to a UDC module by using the Load Operating System command from the Command menu in the System Configurator. Refer to the AutoMax Programming Executive instruction manual for the procedure. The operating system(s) must be loaded to the AutoMax Processor(s) at the same time or before loading the UDC module operating system.

The operating system may be loaded to the UDC module in a specified slot or to all UDC modules in the rack. It is possible to re-load a single UDC module’s operating system without having to re-load the operating systems to all of the UDC modules in the rack.

The leftmost AutoMax Processor in the rack will check for compatibility between the AutoMax operating system and the UDC operating system. If a UDC module is replaced with another UDC module that already contains an incompatible operating system, the new UDC module will be disabled and its “OS OK” LED will be turned off.

5.2 Loading the Drive Parameters and UDC Tasks

The drive parameters specified when the UDC module is configured can be thought of as the UDC configuration. In addition to the AutoMax Processor, the UDC module must have its configuration loaded before it can execute any tasks. The drive parameters and UDC tasks can be loaded to the UDC by selecting “L” for Load from the ON LINE Transfer menu. Several options, which are briefly described in the following paragraphs, will be displayed on the screen.



The option “A” for ALL will automatically load the rack (i.e., AutoMax Processor configuration, the drive parameters for all the UDC modules in the rack, and all tasks for the rack, including all UDC tasks).

The drive parameters may be loaded to the UDC module in a specified slot or to all UDC modules in the rack. When the drive parameters are loaded, the AutoMax Programming Executive will determine if the drive parameters are compatible with the existing rack configuration. If the drive parameters are not compatible, an error message will be displayed on the computer screen.

UDC tasks may also be loaded to the UDC modules in the rack. If this option is chosen, the Programming Executive will display a list of all the AutoMax tasks and UDC tasks for the system. Select the task to be loaded from the list. Note that the rack configuration and the drive parameters must be loaded before loading UDC tasks to a UDC module.

Refer to the AutoMax Programming Executive instruction manual for the complete Load procedure.

5.3 Running, Stopping, and Deleting UDC Application Tasks

Running UDC Tasks

A UDC application task is required in order to control a Distributed Power System drive. To control two drives, two UDC tasks are required. Once it is loaded to the UDC, a UDC application task is included in the on-line task list with the AutoMax Processor application tasks. It can be run, stopped, monitored, or deleted in the same way as any other application task. The priority field will be set to “N/A” for UDC application tasks. The task for drive A always executes first, followed by the task for drive B.

The Run All command will run all AutoMax and UDC tasks. The UDC module’s tasks can be run whether or not the following conditions are met:

• the PMI Regulator is communicating with the UDC module

• the PMI Regulator’s operating system has been loaded from the UDC module to the PMI Regulator (which happens automatically when the PMI Regulator is connected to the UDC module).

Stopping UDC Tasks

UDC application tasks (both tasks A and B together) must run at least every 10 milliseconds. Once the SCAN_LOOP statement is executed, the UDC module will cause a Stop All in the rack if the task does not complete its scan within 10 milliseconds.

!ATTENTION: Understand the application before starting a task. Outputs may change states, resulting in machine movement. Failure to observe this precaution could result in bodily injury.

ATTENTION: It is the responsibility of the user to ensure that the application process stops in a safe manner when the application tasks stop. Failure to observe this precaution could result in bodily injury.

On-Line Operation 5-3

Deleting UDC Tasks

When a UDC application task is deleted, any local variables which were forced are removed from the force table. The task’s error log is also cleared.

5.4 UDC Information Log and Error Log

The information log and error log for a UDC task can be displayed by selecting “I” for Info/Log from the ON LINE menu. Refer to the AutoMax Programming Executive instruction manual for the procedure.

The information log for a slot containing a UDC module will display the UDC operating system’s part number, the utilization of the CPU resources in the UDC module, and various memory and PMI rack statistics. Select “U” from the Info/Log menu to display the information log. Note that the UDC module’s CPU utilization should not exceed 75%.

Like AutoMax tasks, UDC tasks can access the error log by using the BASIC statement CLR_ERRLOG@ and BASIC function TST_ERRLOG@. The error log will display the first, second, and last errors and will maintain them until power is cycled.


SB3000 Drive Register Reference A-1

APPENDIX ASB3000 Drive Register Reference

REGISTER MAP

Registers Function 0-23 Analog ch. 0 input over-range

24-79 System Use Only 1

80-89 UDC/PMI comm. status registers for drive A


100-106 Command registers for drive A


200-222 Feedback registers for drive A


300-599 Application registers updated every scanfor drives A and B


1000 UDC module test switch register1001-1017 UDC module meter port setup registers


1080-1089 UDC/PMI comm. status registers for drive B


1100-1106 Command registers for drive B


1200-1221 Feedback registers for drive B


1300-1599 Application registers updated every scanfor drives A and B


2000-2010 Interrupt Status and Control registers fordrives A and B


(1) These registers cannot be written to by the user.

REGISTER/BIT DESCRIPTIONS

RAIL I/O PORT REGISTERS

A/B0 / 12 PMI port 0, channel 01 / 13 PMI port 0, channel 12 / 14 PMI port 0, channel 23 / 15 PMI port 0, channel 34 / 16 PMI port 0 faults (see below)5 / 17 PMI port 0 check bit fault counter6 / 18 PMI port 1, channel 07 / 19 PMI port 1, channel 18 / 20 PMI port 1, channel 29 / 21 PMI port 1, channel 3

10 / 22 PMI port 1 faults (see below)11 / 23 PMI port 1 check bit fault counter

Rail Fault Bits 0 Analog ch. 0 input over-range 1 Analog ch. 0 input under-range 2 Analog ch. 1 input over-range 3 Analog ch. 1 input under-range 4 Analog ch. 2 input over-range 5 Analog ch. 2 input under-range 6 Analog ch. 3 input over-range 7 Analog ch. 3 input under-range 8 No device plugged into configured port 9 Bad ID code10 Bad rail comm. check bits received11 PMI Processor interface not ready

UDC-PMI COMMUNICATION STATUS

A/B80 /1080 UDC Module port status

Bit0 Invalid rcr interrupt 1 No end of frame status 2 CRC/framing error 3 Overrun error 4 DMA format error 5 Transmitter underrun 6 CCLK comm sync error 7 Loopback data error 8 Missed gains 9 Multiplexed data verification error10 No matching PMI OS11 Invalid PMI OS header12 Incompatible PMI H/W

81 /1081 UDC module good msg. recvd. count82 /1082 UDC module CRC error count83 /1083 UDC module format error count

84 /1084 PMI port statusBit 0 Invalid rcr interrupt 1 No end of frame status 2 CRC/framing error 3 Overrun error 4 DMA format error 5 Transmitter underrun 6 CCLK comm sync error 8 UDC CCLK comm sync error 9 Multiplexed data verification error12 Invalid PMI start OS address13 Insuff. PMI memory to load PMI OS14 Invalid PMI load address15 PMI OS overflow

85 /1085 PMI good msg. recvd. count86 /1086 PMI CRC error count87 /1087 PMI format error count88 /1088 Comm/link status89 /1089 UDC transmitted msg. count

COMMAND REGISTERS

A/B100/1100Drive Control

Bit 0 Enable minor loop VDC_RUN@ 2 Enable bridge test BRG_TST@ 8 Fault reset FLT_RST@ 9 Warning reset WRN_RST@10 Enable parallel PU A PPM_EN1@11 Enable parallel PU B PPM_EN2@12 Enable parallel PU C PPM_EN3@15 UDC task running (status)* UDC_RUN@

101/1101I/O ControlBit 2 External fault LED EXT_FLT@ 4 Auxiliary output AUX_OUT@15 UDC port loopback test UDC_LB@

102/1102 Voltage reference VDC_REF%103/1103 Power factor current ref IPF_REF%105/1105 Test code TST_CODE%106/1106 PMI D/A output PMI_DA%

FEEDBACK REGISTERS

A/B200/1200 Drive status

Bit 0 Voltage loop on VDC_ON@ 1 Voltage loop standby VDC_SB@ 2 In current limit IN_LMT@ 3 Power factor current in limit IPF_LMT@ 7 Line synchronized LIN_SYN@ 8 Fault detected FLT@ 9 Warning detected WRN@13 Rail data ready RAIL_OK@14 CCLK synchronized CCLK_OK@15 PMI OS loaded PMI_OK@

201/1201 I/O statusBit 0 Run permissive input RPI@ 1 115 VAC auxiliary input 1 AUX_IN1@ 2 115 VAC auxiliary input 2 AUX_IN2@ 3 115 VAC auxiliary input 3 AUX_IN3@ 4 115 VAC auxiliary input 4 AUX_IN4@ 5 115 VAC auxiliary input 5 AUX_IN5@12 Pre-charge feedback CHG_FB@

202/1202 Drive faultBit 0 DC Bus overvoltage FLT_OV@ 1 DC bus overcurrent FLT_DCI@ 3 Instantaneous overcurrent FLT_IOC@ 4 LPI module fault FLT_LPI@ 5 GDI module fault FLT_GDI@ 6 Charge fault FLT_CHG@ 7 Overtemperature fault FLT_OT@10 Power loss fault FLT_PWR@11 Power technology fault FLT_PTM@12 PMI power supply fault FLT_PS@13 PMI read write fault FLT_RW@14 UDC run fault FLT_RUN@15 PMI communication lost FLT_COM@

203/1203Drive warningBit 0 DC bus overvoltage WRN_OV% 1 DC bus overcurrent WRN_UV% 2 Ground current warning WRN_GND% 3 Phase lost WRN_PL% 4 Reference in limit WRN_RIL% 6 Load sharing warning WRN_SHR% 7 Overtemperature warning WRN_OT% 8 Bad gain data WRN_BGD% 9 Power module overload WRN_OL%10 Power loss WRN_PWR%12 PMI fan loss WRN_FAN%13 Rail communication error WRN_RAL%14 CCLK not synchronized WRN_CLK%15 PMI communication error WRN_COM%

A-2 SB3000 Drive Configuration and Programming

FEEDBACK REGISTERS (CONTINUED)

A/B

204/1204 Power Device statusBit 0 Phase U -upper A U_UPA@ 1 Phase V -upper A V_UPA@ 2 Phase W -upper A W_UPA@ 3 Phase U -lower A U_LOA@ 4 Phase V -lower A V_LOA@ 5 Phase W -lower A W_LOA@ 6 Power Module A fault IPUA@ 7 GDI fault A GDIA@ 8 Bus charge time-out A CHGA@ 9 Phase U loss U_PL@10 Phase V loss V_PL@11 Phase W loss W_PL@12 Overtemperature A OTA@13 Phase U current sharing A U_SHRA@14 Phase V current sharing A V_SHRA@15 Phase W current sharing A W_SHRA@

205/1205 InterlockBit 0 Config param not loaded IC_CNF@ 1 Gains not loaded IC_GAIN@ 2 Run permissive missing IC_RPI@ 3 Faults need reset IC_FLT@ 4 Rising edge required IC_RISE@ 5 More than one request IC_MORE@ 6 AC sync not ready IC_SYN@ 7 Pre-charge not closed IC_PCHG@ 8 GDI mismatch IC_GDI@ 9 Incompatible PMI backplane IC_IPBP@11 VDC not allowed IC_VDC@

206/1206 DC bus voltage (volts) VDC_FB%

207/1207 DC bus current (amps * 10) IDC_FB%

208/1208 Ground current (amps * 10) GI_FB%

209/1209 AC voltage feedback (VRMS) VAC_FB%

210/1210 AC current feedback IAC_FB%

211/1211 VAR feedback VAR_FB%

212/1212 Iq feedback (amps * 10) IQ_FB%

213/1213 Id feedback (amps * 10) ID_FB%

214/1214 User analog input ANA_IN%

219/1219 Selected variable SEL_VAR%

FEEDBACK REGISTERS (CONTINUED)

A/B220/1220 Parallel Power Module B Status

Bit 0 Phase U - upper B U_UPB@ 1 Phase V - upper B V_UPB@ 2 Phase W - upper B W_UPB@ 3 Phase U - lower B U_LOB@ 4 Phase V - lower B V_LOB@ 5 Phase W - lower B W_LOB@ 6 Power module B fault IPUB@ 7 GDI fault B GDIB@ 8 Bus charge time-out B CHGB%12 Overtemperature B OTB@13 Phase U current sharing B U_SHRB@14 Phase V current sharing B V_SHRB@15 Phase W current sharing B W_SHRB@

221/1221 Parallel Power Module C StatusBit 0 Phase U - upper C U_UPC@ 1 Phase V - upper C V_UPC@ 2 Phase W - upper C W_UPC@ 3 Phase U - lower C U_LOC@ 4 Phase V - lower C V_LOC@ 5 Phase W - lower C W_LOC@ 6 Power module C fault IPUC@ 7 GDI fault C GDIC@ 8 Bus charge time-out C CHGC%12 Overtemperature C OTC@13 Phase U current sharing C U_SHRC@14 Phase V current sharing C V_SHRC@15 Phase W current sharing C W_SHRC@

222/1222 Error codes

UDC MODULE TEST INPUTS

1000 SwitchesBit 0 UDC pushbutton UDC_PB@ 1 UDC switch UP position SWIT_UP@ 2 UDC switch DOWN position SWIT_DN@

LEDs 8 OS OK 9 Comm A OK10 Drive A fault11 Comm B OK12 Drive B fault

METER PORT SETUP

1001 Initiate change in setup (non-zero value)1002 Port 1 UDC register number (0-2047)1003 Port 1 bit number (100-115, 0 = all bits)1004 Port 1 maximum value1005 Port 1 minimum value1006 Port 2 UDC register number (0-2047)1007 Port 2 bit number (100-115, 0 = all bits)1008 Port 2 maximum value1009 Port 2 minimum value1010 Port 3 UDC register number (0-2047)1011 Port 3 bit number (100-115, 0 = all bits)1012 Port 3 maximum value1013 Port 3 minimum value1014 Port 4 UDC register number (0-2047)1015 Port 4 bit number (100-115, 0 = all bits)1016 Port 4 maximum value1017 Port 4 minimum value

APPLICATION REGISTERS

1300-1599Application registers updated every1599 Nth scan - A/B

INTERRUPT STATUS AND CONTROL (ISCR)

2000 Interrupt status and control UDC_ISCR%Bit 0 Interrupt line ID 2 Interrupt allocated 4 Interrupt generated this scan 5 CCLK counting 6 Enable CCLK to backplane* 7 Interrupt enabled15 Interrupt status

*Only bit 6 in register 2000 can be written to by the pro-grammer. All other bits in register 2000 are read only.

LOCAL TUNABLE VARIABLES

Capacitance (microfarads) C_E6%Ground current threshold (amps * 10) GIT_E1%Current sharing threshold (amps * 10) IST_E1%Inductance (microhenries) L_E6%Overvoltage threshold (volts) OVT_E0%Undervoltage threshold (volts) UVT_E0%Voltage loop damping VDC_A%Voltage loop feed forward VDC_FF%Voltage loop derivative gain VDC_KD%Voltage loop crossover frequency (rad/sec) VDC_WCO%

SB3000 Local Tunable Variables B-1

APPENDIX BSB3000 Local Tunable

Variables

C_E6% Capacitance

The value in this variable selects the capacitance connected to the bus. The value is scaled in microfarads.

Units: µFDefault Value: 32400Low Limit: 32400High Limit: 97200Step: 1

For a single power unit, assign a value of 32400. For two parallel power units, 64800. For three parallel power units, 97200.

GIT_E1% Ground Current Threshold

A drive warning is generated (register 203/1203, bit 2) if the ground current in the rectifier goes above the value stored in this variable. The value is scaled in amps times 10; i.e., 100 represents 10.0 amps.

Units: Amps * 10Default Value: 100Low Limit: 10High Limit: 2000Step: 1

This value should be set above the value in the ground current feedback register (208/1208) after the drive is operational.

IST_E1% Current Sharing Warning Threshold

A drive warning is generated (register 203/1203, bit 6) if the bus current is less than the value stored in this tunable variable. The value is scaled in amps times 10; i.e., 600 represents 60.0 amps.

Units: Amps * 10Default Value: 600Low Limit: 10High Limit: 2000Step: 1

This variable should be left at the default value if the rectifier has only a single power unit.

B-2 SB3000 Drive Configuration and Programming

L_E6% Inductance

The value stored in this variable sets the inductance of the Power Module. The value is scaled in microhenries.

Units: µHDefault Value: 500Low Limit: 167High Limit: 500Step: 1

For a single power unit, assign a value of 500. For two parallel power units, 250. For three parallel units, 167.

OVT_E0% Overvoltage Warning Threshold

A warning is generated (register 203/1203, bit 0) if the DC bus voltage exceeds the value stored in this variable. The value is scaled in volts.

Units: VoltsDefault Value: 850Low Limit: 600High Limit: 925Step: 1

This value should be set above the normal operating voltage (displayed in the DC Bus Voltage Feedback register, 206/1206).

UVT_E0% Undervoltage Warning Threshold

A drive warning is generated (register 203/1203, bit 1) if DC bus voltage is less than the value stored in this variable. The value is scaled in volts.

Units: VoltsDefault Value: 750Low Limit: 600High Limit: 925Step: 1

VDC_A% Voltage Loop Damping Factor

The value in this variable selects the desired response of the voltage loop. This value is used by the PMI Processor to determine the integral gain (Ki) of the voltage loop:Ki = VDC_WCO% ÷ VDC_A%

Units: NoneDefault Value: 120Low Limit: 40High Limit: 200Step: 1

The higher the value, the smaller the integral gain and the overshoot in the voltage loop. The lower the value, the larger the integral gain and the overshoot in the voltage loop. Ideally, the value should be set equal to 0.4 * VDC_WCO%.

VDC_FF% Voltage Loop Feed Forward

The value in this variable selects the feed forward gain in the voltage loop. This value should normally be set to 1000.


SB3000 Local Tunable Variables B-3

VDC_KD% Voltage Loop Derivative Gain

The value in this variable selects the voltage loop derivative gain. This value should normally be set to 0.


VDC_WCO% Voltage Loop Crossover Frequency

The value in this variable selects the desired response of the voltage loop. The higher the value, the more quickly the rectifier responds to a change in voltage reference. The value is entered in radians/second.

Units: rads/secDefault Value: 300Low Limit: 100High Limit: 500Step: 1

The factory default value of 300 rad/sec is the recommended value. System operation should be tested at this level before any adjustments are made. Note that if this value is adjusted too high, the voltage loop will become unstable.

B-4 SB3000 Drive Configuration and Programming

SB3000 Control Algorithm C-1

APPENDIX CSB3000 Control Algorithm

SB3000 Synchronous Rectifiers regulate DC bus voltage using a vector control algorithm. This algorithm, which is executed in the PMI processor, is also referred to as the minor loop. (The major control loop is executed in the AutoMax processor.)

The UDC application control task passes the desired DC bus voltage reference command to the PMI Processor in register 102/1102. The PMI Processor uses PID (proportional/integral/derivative) logic to calculate DC bus current (referred to as Iq) in response to the voltage reference and voltage error. In motoring quadrants, the Iq component of current is in phase with the AC line voltage. In regenerating quadrants, the Iq component is 180 degrees out of phase with the AC line.

The PMI Processor uses the AC line period to determine the frequency to command. The offset between the zero crossing of the AC line and the commanded zero crossing is used to determine the angle offset. The AC line frequency may change by up to 1 Hz per second.

If the UDC application task provides a leading power factor current reference in register 103/1103, the vector algorithm can compensate for a lagging power factor in the load inverter with the second component of the current vector, referred to as Id. Id is calculated from the value of Iq and the reference in register 103/1103. When Iq is near zero due to a small load on the DC bus, Id can approach the reference value. As Iq becomes larger, Id becomes smaller.

If capacity is left over after power has been supplied to the load, the vector algorithm can produce reactive power (VARS) with a leading power factor to compensate for other machines with lagging power factors on the same AC line. Id will be limited not to exceed the rectifier rating. The VARS produced will be reported in register 211/1211.

C-2 SB3000 Drive Configuration and Programming

Figure C.1 – Control Structure

Har

dwar

eS

oftw

are

Ki =

Vm

l - W

coV

ml -

A

Kp

= V

ml -

Wco

C

Gen

erat

eP

WM

Vu

Vv

Vw

2/3

Vq

PI

(Iq_

Fbk

)

(Iq_

Cm

d)

Cnf

I_Lm

t ∗ 1

.414

+ +

PI_

Lmt_

E1

+ +

PI_

Lmt_

E4

+ +

z-1

Ki

Kp

E1

Vd

PI

(Id_

Fbk

)

(Id_

Cm

d)Li

mit

Pow

erFa

ctor

Cur

rent

(Vdc

_Ref

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(Ipf

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+ +

Ram

p Filt

er25

%V

ml_

Kd

z-1+ –

+ –

if (!

drv_

on||r

esta

rt)

Vdc

_Ref

_E0

= V

dc_R

amp_

E1+

+/1

0

Min

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_Ref

_E0

= V

ac_R

ms_

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∗ 1.

414

∗ 1.

1

Ma

x_V

dc_R

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Max

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ts -

25

=87

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(Pi_

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1000

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(Vdc

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f(46

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71

5

Status of Data in the AutoMax Rack After a STOP_ALL Command or STOP_ALL Fault D-1

APPENDIX DStatus of Data in the AutoMax Rack

After a STOP_ALL Command orSTOP_ALL Fault

AutoMax Processor UDC Module PMI Processor

LOCAL tunable variables retained retained retained

LOCAL variables retained reset to 0 N/A

COMMON memory variables non-volatile are retained;others are reset to 0

N/A N/A

I/O variables(including UDC dual port memory

inputs retained and updated; outputs are reset to 0

inputs retained and updated; outputs are reset to 0

all I/O is reset to 0

Input values, including:Feedback registersUDC/PMI communication status registersUDC Error Log info

retained retained N/A

Output values, including:Command registersApplication registersISCR registersScan-per-interrupt registerScans-per-interrupt counter

reset to 0 reset to 0 N/A

Parameter configuration variables N/A retained N/A

UDC test switch information N/A retained N/A

D/A setup configuration N/A retained N/A

Operating system retained retained retained

D-2 SB3000 Drive Configuration and Programming

SB3000 Pre-Charge Sequencing E-1

APPENDIX ESB3000 Pre-Charge Sequencing

The SB3000 Synchronous Rectifier System is shown in figure E.1 on the following page.

The pre-charge is controlled via a pre-charge contactor, which is under the control of the PMI Processor in the SB3000’s PMI rack. The contactor is mounted separately in the power distribution cabinet. Any faults in contactor operation are reported in UDC registers 202/1202 and 205/1205.

Pre-charge Sequencing During Normal Operation

When AC power is applied to the SB3000 Rectifier, back diodes in the IGBT power devices will allow the capacitor bank to begin charging immediately through the fused pre-charge resistors and line filter reactor.

Close Threshold

When control power is first turned on, the pre-charge contactor will be open. This will allow the DC bus voltage to increase to near the peak of the AC line. The closing and opening of the pre-charge contactor is a function of the measured DC bus voltage. The close threshold is the peak of the configured AC line voltage minus 10 percent. This threshold allows the rectifier to turn off with the AC line up to 10% low. The contactor will stay open until the measured DC bus voltage reaches this threshold. When the contactor closes, the PMI Processor will indicate this by turning on register 201/1201, bit 12 (CHG_FB@).

Close Threshold = Peak AC line voltage - 10%

Open Threshold

The open threshold is the peak of the configured AC line voltage minus 100 volts. The contactor will open again if the measured DC bus voltage becomes less than this level. If this occurs, register 201/1201, bit 12 will be turned off. The contactor will remain open until bus voltage again reaches a steady state above the close threshold.

Open Threshold = Peak AC line voltage - 100V

E-2 SB3000 Drive Configuration and Programming

Figure E.1 – SB3000 Synchronous Rectifier System Diagram

UV

W

C EG

IGB

T

C EG

IGB

T

C EG

IGB

T

C EG

IGB

T

C EG

IGB

T

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SB3000 Pre-Charge Sequencing E-3

Load Inverter Pre-charge Contactor Requirements

The status of the SB3000 Rectifier pre-charge contactor (CHG_FB@) must be checked by the inverter application tasks. The load inverters must not operate with the rectifier pre-charge contactor open. Doing so may damage the pre-charge resistors. It is the responsibility of the application tasks to ensure that the Rectifier is in run before a load inverter is turned on.

If the rectifier is shut down on a fault condition, the application is responsible for a controlled shut down of the inverter.

Note that each load inverter must also be provided with its own pre-charge resistor and contactor to limit the current into its capacitors.

Pre-charge Contactor Sequencing During the Bridge Test

When the bridge test is commanded in register 100/1100, bit 2, the pre-charge contactor will close. After the results of the test have been displayed on the corresponding GDI module(s) LEDs, the pre-charge contactor will be opened.

!ATTENTION: The UDC application task must examine the pre-charge status bit (CHG_FB@) regularly. If the status bit turns off, the load inverters must be shut down. If the inverters are not shut down, the pre-charge resistor may be damaged. Failure to observe this precaution could result in damage to, or destruction of, the equipment.

E-4 SB3000 Drive Configuration and Programming

Figure E.2 – Pre-Charge Sequencing State Diagram

Control Power On

Pre-charge Contactor is Open

Pre-charge contactor is closedReport fault (FLT_CHG)

Wait for Pre-charge to Close

Pre-charge times outReport fault (FLT_CHG)

Pre-charge is closed& Vdc > Vdiode

Pre-charge Closed - RUN Pre-charge Closed - TEST

Pre-charge opensReport fault (FLT_CHG)

Wait to Open

Vdc < Power Loss ThresholdDisable gateReport fault (FLT_CHG)Command pre-chargeto open

Pre-charge does not openReport fault (FLT_CHG)

No charge faults & Vdc > Vdiodeor

Test mode active & Vdc < 5VCommand pre-charge to close

Pre-charge is closed

& Vdc < 5V& in test mode

Pre-charge opensReport fault (FLT_CHG)

Bridge test command is set falseCommand pre-charge to open

Pre-charge does not openReport fault (FLT_CHG)

Enabling the Voltage Loop F-1

APPENDIX FEnabling the Voltage Loop

The voltage loop in the PMI Processor is enabled using bit 0 of register 100/1100 (VDC_RUN@). The following conditions must be true before the loop can go into run and must remain true during the entire time that it stays in run:

• AC power must be on.

• The pre-charge contactor must be closed. This occurs after the DC bus voltage is stable. It does not require a command from the application task.

• The RPI input on the Resolver & Drive I/O module must be on. If it is not, bit 2 in the Interlock register (205/1205) will be set.

• All other interlock tests must be passed. If they are not, the corresponding bits in the Interlock register will be set. The interlocks tests are described in the section of this manual covering register 205/1205.

If all of the above conditions are true, the DC bus is ramped up to the voltage reference programmed into register 102/1102 (VDC_REF%). The ramp rate is approximately 100V per second. Bit 0 in register 200/1200 (VDC_ON@) will be set when the programmed value is reached.

Two tunable variables, UVT_E0% and OVT_E0%, determine the under and over voltage threshold values during the ramp phase. If the voltage goes outside of these limits, warnings will be reported in register 203/1203, bits 1 and 0, respectively.

If AC power is lost momentarily, the rectifier will go into standby (power dip ride through). It will turn back on when the PMI Processor is resynchronized with the AC line.

!ATTENTION: The pre-charge contactor for the SB3000 must be closed and the voltage loop must be on (register 200/1200, bit 0) before any load inverters can be put into run. If the SB3000 pre-charge contactor is not closed, running a load inverter will burn up the pre-charge resistors. Failure to observe this precaution could result in damage to, or destruction of, the equipment.

F-2 SB3000 Drive Configuration and Programming

Figure F.1 – Turning On VDC_RUN

PowerOn

Vac ∗ 1.414

OVT_E0%

UVT_E0%

VDC_RUN

VDC_ON

Performing the Bridge Test G-1

APPENDIX GPerforming the Bridge Test

Important: This test is normally performed at the factory. It should not be necessary to perform it again unless the power devices or fiber-optic cables are replaced.

The bridge test is used to verify gate cabling connections by test firing IGBTs one at a time, cycling through the power module that is enabled. As the IGBTs fire, the LEDs on the corresponding GDI module in the rectifier’s PMI rack will turn on and off in the following order:

1. U- Lower Power Device

2. U+ Upper Power Device

3. V- Lower Power Device

4. V+ Upper Power Device

5. W- Lower Power Device

6. W+ Upper Power Device

If the LEDs do not turn on and off in this order, the fiber-optic gate cables have been connected incorrectly and must be reconnected in accordance with the wiring diagrams. Three-phase AC Power must be off and the bus capacitors must be discharged before the cables can be re-connected.

Three-phase AC input power to the SB3000 Rectifier must be turned off and the load inverter must be disconnected before the bridge test can be enabled. The 115 VAC control power must be supplied to pick up the pre-charge contactor.

The bridge test will not be permitted to begin if DC bus voltage is greater than 10V. However, the PMI cannot stop three-phase power from being turned on after the test has been started. If three-phase AC power is turned on while the bridge test is in progress there will be a line-to-line short, which may damage the power module and cause injury to personnel.

!ATTENTION: Turn off three-phase AC power to the SB3000 Synchronous Rectifier before enabling the bridge test and ensure that three-phase AC power cannot be turned on while the bridge test is running. If three-phase AC power is turned on while the bridge test is running, a line-to-line short will occur. Failure to observe this precaution could result in bodily injury.

G-2 SB3000 Drive Configuration and Programming

Bridge Test Procedure

To perform the bridge test:

Step 1. Disconnect, lockout, and tag three-phase AC power to the Synchronous Rectifier.

Step 2. Ensure that the DC bus is fully discharged. Refer to Appendix H.

Step 3. Command the bridge test, using register 100/110, bit 2, and bit 10, 11, or 12, as applicable.

Step 4. Verify that the LEDs turn on and off in the order listed.

If the LEDs do not turn on and off in the proper order, reconnect the fiber-optic gate cables as shown on the wiring diagrams.

Discharging the DC Bus H-1

APPENDIX HDischarging the DC Bus

Observe the following precautions to safely discharge the SB3000 Rectifier’s DC bus capacitors before performing any service or maintenance on the rectifier. Refer to instruction manual S-30xx, Distributed Power System High Power SB3000 Power Modules, for information regarding test points, component locations, and troubleshooting and maintenance procedures.

• Disconnect, lock out, and tag three-phase AC input power.

• Wait five minutes to allow the DC bus voltage to dissipate.

• Look at the built-in DC Bus voltmeter. When the DC bus potential is down to approximately zero volts, open the Power Module cabinet doors and measure the DC bus potential across the DC bus bars, 1247 A (+ bus) and 1145A (- bus), with an external voltmeter before working on the unit.

!ATTENTION: DC bus capacitors retain hazardous voltages after input power has been disconnected. After disconnecting input power, wait ten (10) minutes for the DC bus capacitors to discharge. Open the cabinet doors and check the voltage across the DC bus bars, 347 A,B,C (+ bus) and 345 A,B,C (- bus), with an external voltmeter to ensure the DC bus capacitors are discharged before touching any internal components. Failure to observe this precaution could result in severe bodily injury or loss of life.

H-2 SB3000 Drive Configuration and Programming

Index Index-1

INDEX

A

Access level, 3-3Application programming, 4-1 to 4-10

AutoMax and UDC task coordination, 4-9AutoMax tasks, 4-1calculating local tunable values, 4-7data/time flow for UDC and PMI, 4-10local tunable variables, 4-6 to 4-7recommended run permissive logic, 4-9typical structure of a UDC task, 4-3 to 4-6UDC task scan, 4-2UDC tasks, 4-1 to 4-10UDC/PMI task communication, 4-7 to 4-10

Application registers, 3-48 to 3-49AutoMax rack

status of data, D-1

B

Bit Name, 3-3Bit Number, 3-3Bridge test, 3-17

procedure, G-1 to G-2

C

Command registers, 3-17 to 3-21drive control, 3-17 to 3-19I/O control, 3-20PMI D/A output, 3-21power factor current reference, 3-21test code, 3-21voltage reference, 3-21

Configuration views and registers, 3-4Configuring drive parameters, 2-1 to 2-8

adding a UDC module, 2-1 to 2-2entering drive parameters, 2-2 to 2-4generating drive parameter files, 2-8printing drive parameters, 2-8restricted drive type combinations, 2-2rules for configuring/selecting drives, 2-2

Configuring UDC registers, 3-1 to 3-61Control algorithm, C-1 to C-2Control structure, C-2

D

Discharging the DC bus, H-1Drive parameters. See Configuring drive

parametersDrive register reference, A-1 to A-2Dual port memory register organization, 3-5

F

Faults, 3-26 to 3-29charge fault, 3-28communication lost, 3-29DC bus overcurrent, 3-27DC bus overvoltage, 3-26gate driver interface fault, 3-27instantaneous overcurrent, 3-27local power interface fault, 3-27overtemperature, 3-28PMI power supply fault, 3-29PMI read/write fault, 3-29power loss, 3-28power technology fault, 3-28UDC run fault, 3-29

Feedback registers, 3-22 to 3-47AC current feedback (amps rms), 3-39DC bus current (amps), 3-39DC bus voltage (volts), 3-39diagnostic fault code, 3-46 to 3-47drive fault, 3-26 to 3-29drive status, 3-22 to 3-24drive warning, 3-30 to 3-33ground current feedback (amps), 3-39I/O status, 3-24 to 3-26Id feedback (amps), 3-40interlock, 3-37 to 3-39Iq feedback (amps), 3-40parallel power module B status, 3-41 to 3-43parallel power module C status, 3-43 to 3-45power device status, 3-34 to 3-36selected variable, 3-40user analog input, 3-40

Index-2 SB3000 Drive Configuration and Programming

VAR feedback (volts * amps), 3-40voltage feedback (volts rms), 3-39

G

Generating drive parameter files, 2-8

H

Hex Value, 3-3

I

Interrupt status and control registers, 3-59 to 3-61interrupt status control, 3-59 to 3-60scans per interrupt, 3-61

Interrupts, 4-3, 4-8Introduction, 1-1 to 1-2

L

LED indicator, 3-3Local tunable variables, 4-6 to 4-7, B-1 to B-3

calculating local tunable values, 4-7

M

Meter portsparameters, 2-7port 1 registers, 3-55port 2 registers, 3-56port 3 registers, 3-57port 4 registers, 3-58port selection, 2-6 to 2-7resolution of data, 3-54 to 3-58setup registers, 3-53 to 3-58

Motor data entry, 2-5

N

Nth scan interrupts, 3-50

O

On-line operation, 5-1 to 5-3deleting UDC tasks, 5-3loading drive parameters, 5-1 to 5-2loading the UDC operating system, 5-1loading UDC tasks, 5-1 to 5-2

running UDC tasks, 5-2stopping UDC tasks, 5-2UDC information and error logs, 5-3

P

Power module parameter entry, 2-4 to 2-5Power system configuration, 2-4 to 2-5Pre-charge sequencing, E-1 to E-4

state diagram, E-4Printing drive parameters, 2-8

R

Rail I/O port registers, 3-6 to 3-8check bit fault counter registers, 3-7 to 3-8fault registers, 3-7 to 3-8

Range, 3-3Register Name, 3-3Register Numbers, 3-3Register reference

see Drive Register ReferenceRegister/bit reference conventions, 3-3 to 3-5Related publications, 1-1Restricted drive type combinations, 2-2Run permissive logic, 4-9

S

Screens for parameter entrymeter port selection, 2-6power module data, 2-4

Sug. Var. Name, 3-3Supported SB3000 power modules, 2-5Synchronous rectifier system diagram, E-2

U

UDC Error Code, 3-3UDC module

adding a UDC module, 2-1 to 2-2initiate change in setup register, 3-54meter port setup registers, 3-53 to 3-58test I/O registers, 3-51 to 3-58test switch inputs register, 3-51 to 3-52

UDC task scan, 3-48, 4-2UDC/PMI communication status registers, 3-9 to

3-16PMI communication status, 3-12 to 3-15PMI CRC error count, 3-15PMI format error count, 3-15

Index Index-3

PMI receive count, 3-15UDC communication status, 3-9 to 3-11UDC CRC error count, 3-12UDC fiber-optic link status, 3-16UDC format error count, 3-12UDC receive count, 3-11UDC transmitted message count, 3-16

V

Variable configurator, 3-1Viewing registers, 3-1 to 3-2

application registers, 3-2command registers, 3-1feedback registers, 3-2interrupt status and control registers, 3-2Rail I/O, 3-1UDC module test I/O register, 3-2

Voltage loop, 3-17enabling, F-1 to F-2

turning on VDC_RUN, F-2

W

Warnings, 3-30 to 3-33bad gain data, 3-31CCLK not synchronized, 3-33DC bus overvoltage, 3-30DC bus undervoltage, 3-30ground current warning, 3-30load sharing warning, 3-31overtemperature, 3-31phase loss, 3-30PMI communication warning, 3-33PMI fan loss, 3-32power lost, 3-32power module overload, 3-32rail communication warning, 3-33reference in limit, 3-31

Index-4 SB3000 Drive Configuration and Programming

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Distributed Power System SB3000 ... - Rockwell Automation · Distributed Power System Overview S-3005 Distributed Power System Universal Drive Controller Module S-3007 Distributed