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Directional Couplers from 30 to 140GHz in Silicon
Benjamin Laemmle 1, Klaus Schmalz 2, Christoph Scheytt 2, Alexander Koelpin 1, and Robert Weigel 1
1 Institute for Electronics Engineering,
University of Erlangen-Nuremberg, Cauerstr. 9, 91058 Erlangen, Germany2 IHP Microelectronics GmbH,
Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
AbstractIn this paper directional couplers with reduced size,by lumped elements, inverted microstrip, and broadside coupledlines at 61, 110, and 122 GHz center frequency and up to 156-GHzbandwidth have been designed. The couplers show an isolation upto 40 dB. Different SiGe BiCMOS technologies with 250-nm and130-nm feature width and 5 to 7 metal layers have been used. Themeasurement results have been compared to simulation resultsand good agreement has been observed.
Index Termsmillimeter wave directional couplers, passivecircuits
I. INTRODUCTION
The increase of operating frequencies in silicon integrated
circuits enables the integration of passive microwave elements
with reasonable size on chip [1]. The wavelength of millimeter-
wave signals is smaller than the die size enabling the use of dis-
tributed elements in complex integrated circuits and systems.
Transmission lines, Wilkinson power dividers, or matching
networks are already standard elements in millimeter-wave sil-
icon designs. Even complex structures like bandpass filters [2],
ratrace couplers, or Lange Couplers have been integrated and
presented. While for III-V based millimeter-wave integrated
circuits (MMIC) an isolating microwave substrate is available,
this is not the case for silicon. Also silicon is often labeled as
substrate, although this refers to a semiconductor substrate for
fabrication of transistors. However, several metal layers exist
where a ground-plane and conductors for microwave structures
can be formed. With conductors on different metal layers even
3-D structures can be fabricated unlike to III-V based MMICs.
Integrated directional couplers have several applications
for integrated receivers, transmitters, or other circuits. The
couplers can be designed as quadrature hybrid couplers with
equal signal split and 90 phase difference. The application is
quadrature signal generation in the LO [3] or signal path [4]
of quadrature receivers, active IQ modulators [5], or reflection
type modulators [6]. The coupler has to feature low and equal
insertion loss and stable phase difference for the coupled and
direct port.
However, the use of the directive behavior of such couplers
in silicon technology has not been in focus for a while. The
design of reflectometers for different applications requires cou-
plers with high isolation and therefore directivity whereas the
properties listed above are of minor concern. Such directional
couplers are used to divide the incident and reflected wave and
are part of integrated vector network analyzers for readout of
integrated mm-wave sensors [7] or built-in test circuits [8].
In this paper different directional couplers have been de-
signed and presented in two different process technologies.
Several branchline couplers have been designed and measured
and a broadside coupled-line coupler with more than 150GHz
bandwidth is presented. The couplers are compared in area,
insertion loss, isolation, and susceptibility to process variation.
The passive structures have been simulated with SONNET
and very good agreement between simulation and measure-
ment is observed.
II. DIRECTIONAL COUPLERS
130fF130fF
130fF 130fF
135pH 135pH
92pH
92pH
85 85
85
85
0.275
0.275
0.4 0.4
110fF 110fF
110fF110fF
P1P1 P2P2
P3P3 P4P4
Fig. 1. Schematic of a lumped elements (left) and reduced size (right)branchline couplers at 61 GHz. The inductors and capacitors reactance (left)is equal to the characteristic impedance of the respective lines (35 or 50).
A. Reduced Size Branchline Couplers
Two reduced size branchline couplers at 61GHz and at
122GHz have been designed in different technologies. The
standard branchline coupler includes four quarterwave lines
(or branches) and therefore consumes a large chiparea. A
special technique enables the use of branches with shorter
physical length by the use of lines with a higher characteristic
impedance and capacitors at the junctions. According to [9]
the electrical length of a quarterwave line can be calculated
with sin = Z0/Z1,2 and the capacitors as C = cos /(Z0),where Z0 is the actual impedance (86) and Z1,2 is thedesired impedance (35 or 50) of the line. The schematic ofthe coupler is shown on the right side of Fig. 1, whereas the
layout of the coupler with the metal-insulator-metal (MIM)
capacitors is depicted in Fig. 2. The process variations of
these capacitors mainly determines the isolation of the cou-
pler. The effect on center frequency and phase difference
between coupled and direct port is low. The size of the
coupler depends on the physical length of the lines, which is
Proceedings of Asia-Pacific Microwave Conference 2010
Copyright 2010 IEICE
TH2F-5
806
inversely proportional to the characteristic impedance of the
lines. In order to increase the impedance of the line, the unit
capacitance has to be decreased by increasing the height h
(on the uppermost metal layer) and decreasing the conductor
width. However, most designers and simulators assume the
full embedding of the upper metal in the dielectric substrate.
In this process however, the lack of planarization after the
last deposition of SiO2 and the subsequent deposition of
the passivation layer results in a layer stack as shown in
Fig. 2. With smaller conductor width w the capacitance of
the sidewalls to the ground plane is increasing, but with this
topology the electric field is penetrating the passivation layer
and the air. A proper simulation setup is therefore required,
which has been setup by dielectric bricks in SONNET . The
characteristic impedance is decreasing from 86 to 82 withflat SiO2 layer in comparison to the actual layer stack.
MIM Capacitor
h
w
TopMetal2
Metal1
Passivation r=5
SiO2 r=4.1
Si epi r=11.9 =5 S/m
Si bulk r=11.9 =2 S/m
Fig. 2. Layer stack (left) and layout (right) of a reduced size branchlinecoupler with MIM-capacitors.
55 57 59 61 63 65 6740
30
20
10
0
Frequency (GHz)
Magnitude (
dB
)
S11
S21
S31
S41
Fig. 3. Deembedded S-Parameter measurements of the 61-GHz reducedsize branchline coupler. The measurement results of the coupler with thehighest isolation measured is shown, The variation of the capacitors result ina degradation of the isolation to 30 dB at the center frequency, but has nearlyno influence on insertion loss and the phase difference.
B. Lumped Elements Branchline Coupler
Another option to improve the area requirements of branch-
line couplers is the use of lumped elements. A quarterwave
line with characteristic impedance Z0 can be synthesizedby a Pi-network consisting of an inductor with L = Z0
and two capacitors with 1/C = Z0. The circuit and theirparameters are shown in Fig. 1. The inductors are designed
with SONNET and show a good agreement with simulation.
The use of a SiGe BiCMOS technology results in a layer
stack where am epitaxial-grown silicon layer (required for
bipolar transistor formation) with higher substrate resistivity
is introduced between he silicon and the isolating SiO2 layers.
The deembedded measurement results of the lumped ele-
ments coupler are depicted in Fig. 4. This coupler shows higher
losses compared to the reduced size coupler. A chipmicrograph
is shown in Fig. 5.
55 57 59 61 63 65 6725
20
15
10
5
0
Frequency (GHz)
Magnitude (
dB
)
S11
S21
S31
S41
Fig. 4. S-Parameter measurements of lumped elements branchline coupler.The isolation is high although all inductors couple into the same substrate.
C. Inverted Microstrip Branchline Coupler
Inverted microstrip lines have been presented in this tech-
nology for a low noise amplifier at 122GHz [10]. The ground
plane is formed on top of the silicon wafer and the conductor
placed directly below as shown in Fig. 6. This results in
lower ground losses due to the thicker ground metal, and
lower sensitivity to electromagnetic radiation fields due to the
Fig. 5. Chipmicrograph of 61-GHz reduced size (left) and lumped elements(right) branchline couplers. The size is nearly identical and both devicespossess the same pad-frame. Ground pads are shared between neighboringcouplers to reduce the footprint for a characterization. The branches of thereduced size coupler (left) are bent to save chip area. It has to be ensured,that the coupling between the bends and different branches is negligible. Theinductors and the MIM capacitors of the lumped elements couplers can beeasily identified. In the center of the coupler a dedicated ground return pathfor each inductor is drawn. The couplers are fabricated in a 250-nm SiGeBiCMOS technology with a 5-metal layer front-end from IHP.
807
shielding groundplane. However, the field of the line couples
to the conducting silicon substrate resulting in lower isolation.
An inverted microstrip coupler has been designed with
122GHz center frequency in a 7-metal 130-nm BiCMOS
process from IHP. The required area is four times the one
of a reduced size coupler at the same frequency.
h
w
TopMetal2
TopMetal1
SiO2 r=4.1
Si epi r=11.9 =5 S/m
Si bulk r=11.9 =2 S/m
Fig. 6. Layer stack of inverted microstrip branchline coupler showing thelarge ground plane on TopMetal2 and the conductor on TopMetal1. Theground plane is connected to a metal grid throughout the chip to ensureshielding of all structures. The distance h between conductor and groundplane is nearly four times smaller than the distance to the silicon substrate,therefore the unit capacitance to ground is much larger than to the substrate.
Deembedded measurement results from 90 to 140GHz are
shown in Fig. 8. The coupler shows better than 20 dB isolation
from 115 to 128GHz and a return loss below -40 dB at
131GHz. The coupler has better performance in measurement
than in simulation.
D. Broadside Coupled-Line Directional Coupler
Broadband directional couplers can be designed as coupled-
lines, in most cases drawn by parallel lines with a small
gap. However, higher coupling can be achieved by broadside
coupling in silicon technology. The vertical distance between
two conductors in the upper metal layers is in most cases
smaller than the permitted horizontal distance. Moreover, the
size w of both coupled-lines can be arbitrarily chosen. The
width of the lower conductor should be made smaller than
the upper one, as the distance to the substrate is lower. The
coupler can be further optimized for special applications by
introducing more asymmetries, e.g. a displacement of the
lower conductor. The structure has been placed three times
to enable 4-Port S-Parameters with a 2-Port measurement
setup. On each structure different ports are connected to
the pads and the remaining ports are terminated on-chip.
The micrograph of the three connected structures is shown
Fig. 7. Chipmicrograph of the inverted microstrip (left) and reduced size(right) branchline coupler at 122 GHz center frequency. The conductor of theinverted microstrip coupler can not be seen as the ground plane is formed ontop of the metal stack. The structures have been fabricated in a 130-nm SiGeBiCMOS process with 7-metal aluminum front-end from IHP.
90 100 110 120 130 14050
40
30
20
10
0
Frequency (GHz)
Magnitude (
dB
)
S21
meas
S31
meas
S41
meas
S11
meas
Fig. 8. Deembedded S-Parameter measurements of the inverted microstripbranchline coupler from 90 to 140GHz showing an isolation better than 20 dBand equal signal split from 115 to 128GHz. The optimum return loss is betterthan -40 dB at 131GHz.
Metal5
TopMetal1SiO2 r=4.1
Si epi r=11.9 =5 S/m
Si bulk r=11.9 =2 S/m
s
Fig. 9. Layer stack (left) and layout (right) of broadside coupled-linedirectional couplers. The lower metal layer is directly below the upperconductor and is not seen in the layout. The slit in the ground plane increasesthe coupling of the structure.
in Fig. 10. All S-Parameters can be measured in this way
except the transmission coefficient of the lower line. A THRU
deembedding structure has also been placed on the chip.
The connections on all three structures should be identical
(but attached to different ports). This is unfortunately not
possible, as two ports lie on lower metal layers. This requires
a via and a connection on the lower layer (with nonidentical
characteristic impedance). The magnitude of the transmission
of this connection is nearly identical but the phase is slightly
different. Simulations however show a difference in magnitude
and phase of only 0.028dB and up to 0.35 from 20 to
200GHz. The measurements, which are shown in Fig. 11, have
Fig. 10. Chipmicrograph of a broadside coupled directional coupler. Thecoupler has been placed three times to measure 4-Port S-Parameters with a2-Port VNA. The connections should be identical to simplify deembedding,but attached to different ports. The coupler has been fabricated in a 130-nm7-metal layer SiGe BiCMOS process from IHP.
808
been performed from 20 to 115GHz with an Agilent 8510XF
VNA and from 90 to 140GHz with a Rohde & Schwarz
ZVB. The transmission coefficients at 110GHz are 4.15 dB.
The coupler has a 3-dB bandwidth of 156GHz with corner
frequencies at 32GHz (measured) and 188GHz (simulated).
The isolation is above 12 dB over the measured frequency
range even without optimizing the structure. The measured
phase difference between direct and coupled port is between
81 and 90 from 20GHz to 140GHz. Simulation results
of the S-parameters are also shown in Fig. 11. A very good
agreement can be observed in the total frequency range with
only a small step in the change of the measurement setup.
The return loss, however, shows a major step at 90GHz,
presumably due to calibration. The broadside coupled-line di-
20 60 100 140 18025
20
15
10
5
0
Frequency (GHz)
Magnitude (
dB
)
S21
meas
S31
meas
S41
meas
S11
meas
S21
sim
S31
sim
S41
sim
S11
sim
Fig. 11. S-Parameter measurements and simulated values of transmission pa-rameters for the broadside coupled-line directional coupler. The S-Parametershave been measured from 20 to 115GHz and from 90 to 140GHz withtwo different frequency extenders and setups. The measurements are in goodagreement with the simulation results.
rectional coupler can be further optimized for either broadband
quadrature generation or for improved isolation. The coupling
ratio of the broadside coupled-line can be arbitrarily chosen.
III. COUPLER COMPARISON
A comparison of the designed couplers can be found in
Table I with the center frequency, the size, the transmission
parameters of the direct and coupled port and the isolation at
the center frequency.
The reduced size coupler possesses the highest isolation,
but only in a small frequency range. It has good insertion
loss, low area and is therefore the best choice for narrowband
applications. The broadside coupled-line topology shows lower
insertion loss, lower sensitivity to process parameters, higher
bandwidth, and lower area requirements compared to the other
presented couplers. The isolation and therefore the directivity
is lower than the reduced size coupler. The remaining couplers
show lower performance in terms of insertion loss and area
requirement.
TABLE ICOMPARISON OF DIFFERENT COUPLERS
Coupler Type f0 size S21 S31 Iso
(GHz) (m2) (dB) (dB) (dB)
Reduced Size 62 180 x 205 -4.39 -4.52 39
Reduced Size 122 125 x 115 -4.8 -4.8 21
Lumped Elements 61 180 x 205 -5.23 -5.38 23
Inverted Microstrip 123 225 x 250 -4.8 -4.8 27
Broadside 110 95 x 160 -3.8 -3.8 13
IV. CONCLUSION
In this paper five different couplers have been presented and
compared with different center frequencies and bandwidths
in different technologies. A reduced size branchline coupler
at 61 and 122GHz, a lumped elements branchline coupler
at 61GHz, a normal size branchline coupler realized with
inverted microstrip lines at 122GHz, and a broadside coupled-
lines directional coupler have been designed and measured.
Further studies will concentrate on the optimization and the
behavior of broadside coupled directional couplers up to
325GHz with improved directivity.
ACKNOWLEDGMENT
The authors would like to thank Falk Korndorfer, Johannes
Borngraber, and Christian Wipf for measurement and chipmi-
crographs of the structures and IHP Microelectronics GmbH
for fabricating the chips.
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