PEDS 2007

Diode-Assisted Buck-Boost Current Source

Inverters

F. Gaol, C. Liang1, P. C. Loh' and F. Blaabjerg2

School of Electrical and Electronic EngineeringNanyang Technological UniversityNanyang Avenue, Singapore 639798

Email: aofOOO I r tue

Abstract--This paper presents a couple of novel currentsource inverters (CSIs) with the enhanced current buck-boost capability. With the unique diode-inductor networkadded between current source inverter circuitry andcurrent boost elements, the proposed buck-boost currentsource inverters demonstrate a double current boostcapability when comparing with the recently reported buck-boost CSIs. For modulating the presented CSIs, twomodulation schemes are proposed for achieving eitheroptimized harmonic performance or minimal commutationcount, meanwhile keeping the important current buck-boostoperation uninfluenced. Lastly, all theoretical findings wereverified experimentally using constructed laboratoryprototypes.

Index Terms--Buck-boost; current source inverter; pulse-width modulation.

I. INTRODUCTION

To date, current source inverters (CSIs) have been welldeveloped with some attractive advantages, for instance,the better load voltage and current shape, inherent shortcircuit protection and regeneration capability when theline commutated thyristor rectifier is used in front, whichare the main reasons why CSIs can be good alternativesin several applications from low to medium power range.In particular, CSIs can either be used in programmable acsources (PACSs) and uninterruptible power supplies(UPSs) or serve as ac drives and reactive powercompensators. So far, the CSIs have already beenappreciated in medium voltage large power inductiondrives [1], and are currently being investigated even inthe low-power applications [2].

Undoubtedly, conventional CSIs would suffer theirdisadvantages with one particular constraint being its"only voltage-boost" functionality, which limit theirapplications not suitable for low voltage operation.Actually, an additional controlled front-end buck rectifiercan be used to step down the dc link voltage in order toachieve both buck and boost conversion. Butunfortunately, having a controlled rectifier woulddefinitely increase the complication of the invertercontrol and synchronization needed between the addedrectifier and the rear-end inverter, and might not functionwell under severely distorted supply conditions. Inaddition, this method significantly increases the totalsystem cost and reduces the final conversion efficiency.

2Institute of Energy TechnologyAalborg University

DK-9220 Aalborg East, DenmarkEmail: fbl(iet.aau.dk

Alternatively, referring to [3, 4], Cuk and SEPIC dc-dcpower conversion concepts can be added into CSItopologies to realize current buck-boost operation whosefront-end circuit consist of at least one inductor and onecapacitor to store inductive energy. And the dc currentboost ratio is firmly related to the duty ratio of additionalswitch located in the front-end current boost circuitry.Developing from the newly proposed dc-dc converter [5],this paper then presents an alternative solution based onthe Cuk- and SEPIC-derived theories in CSI operation tofurther achieve double current boost capability by usingan additional X-shape diode-inductor network, in whichthe inherent operational principle of the unique passivenetwork allows the inductor currents to be regulated toflow either in series or in parallel with the help ofunidirectional diodes, therefore, the effectively boosteddc-link current can be enhanced with the careful controltechniques using specifically designed modulationschemes. For properly modulating the proposed buck-boost CSIs, two modulation schemes are introduced witheither optimized harmonic performance or reduced totalcommutation count achieved, respectively. Finally, alltheoretical findings were verified experimentally usingthe constructed laboratory prototypes.

YVL Cufret Sofurce Inverter1dC L

Ja)

Fig. 1. Topologies of (a) conventional CSI and (b) SEPIC-derived buck-boost CSI.

1-4244-0645-5/07/$20.00©2007 IEEE 1187

II. REVIEW OF BUCK-BOOST CURRENT SOURCEINVERTERS

Referring to [4], the buck-boost current source inverterwith extra active and passive components added has beendeveloped from the conventional CSI to SEPIC-derivedtopology as illustrated in Fig. 1, where besides thecommon circuit appeared in the shaded area whichconsists of a CSI circuitry, a 2nd order LC filter and an acload, the rest front-end circuit performs the dc currentboost capability. For conventional CSI shown in Fig. l(a),the input dc current id, can be kept as constant asexpected when large inductor L is used, resulting that thepeak value of current ix (x = a, b or c) after the LC filtercannot exceed idc theoretically. To overcome the currentbuck limitation, Fig. 1(b) shows a possible solution usingcapacitor C1 as energy storage intermediate in the front-end circuit which can be derived from the SEPIC dc-dcconverter. When SWO is switched OFF, current idccharges capacitor C1 and flows through CSI circuitry,meanwhile the inductor current of iL also flows throughthe CSI circuitry resulting in the dc link current being thesummation of idc and iL, which of course is larger than theoriginal input dc current idc. When SWO is turned ON,capacitor C1 is discharged, where the discharging currentflows through SWO and L implying that the CSI shouldbe in the null states because the inductor currents iL is notintentionally regulated to flow through the rear-end CSIcircuitry. Assuming the conductive duty ratio of SWO is1-k, the peak value of dc-link current ii and ac outputcurrent i can be derived as:

1 . ^ MIi = Idc ;I = *'d1-k ~ (1-k) (1)

Where, M refers to the modulation ratio normally usedin the inverter control. Due to the limitation of k, M, withrespect to the vertical span defined by the three-phasesinusoidal references, must be numerically equal to orless than k in practice in order to maintain the normalizedvolt-sec average unchanged, otherwise CSI circuitrywould suffer alternating dc-link currents between ii andzero during active intervals.

Besides the buck-boost topology shown in Fig. 1 (b),another buck-boost topology derived from Cuk converteris illustrated in Fig. 2, whose two distinct operatingmodes with respect to the charging and dischargingprocess of capacitor C are also determined by theswitching status of dc side switch SWO. By analyzing itsoperational principle like above analysis, it is noted thatthe boosted dc-link current and ac output current can stillbe expressed as (1).

It is noted that the reviewed current buck-boosttopologies assume minimal passive components in the dccurrent boost circuitry in front of the conventional CSIbridge, mainly because the added capacitor and inductorare the basic elements for performing current boostoperation. Although the buck-boost CSIs can achieve anydesired value for the boosted currents theoretically asindicated in (1), where 11(l-k) can be tuned to be infinite,their practical outputs are limited by the parasiticcomponents and the rating of all front-end passive and

Fig. 2. Topology of Cuk-derived buck-boost CSI.

swo

l Cl --vc

Fig. 3. Topology of Cuk-derived buck-boost CSI with a diode-inductornetwork.

active components, hence the desired high current is hardto achieve, implying the need to design new buck-boostCSIs with enhanced current buck-boost capability.

III. TOPOLOGIES AND OPERATIONAL PRINCIPLES OFBUCK-BOOST CURRENT SOURCE INVERTERS

WITH A DIODE-INDUCTOR NETWORK

The above reviewed buck-boost CSIs with boost ratio11(l-k) can theoretically boost dc input current to anydesired value, however in practice, A large boost ratiowould cause the inductor L suffering a huge boostedcurrent, which definitely increases the requirement for L.In this section, a diode-inductor network is assumed toshare the boosted dc-link current so that the current stressacross inductor can be significantly decreased andmeanwhile the dc-link current could achieve double boostcapability comparatively if the same modulationcondition is assumed. The detailed topologies andoperational principles for the two proposed CSIs wouldbe presented in the following subsections, respectively.

A. Cuk-Derived Buck-Boost CSI with a Diode-Inductor Network

In [5], a Diode-Capacitor Network was introduced intoa DC-DC boost converter to increase the boost ratio ofoutput voltage by regulating the capacitor chargingcurrent properly, which to some extent, can be extendedto DC-AC inversion for achieving enhanced voltageboost capability beyond the traditional voltage sourceinverters with only the inherent voltage-buck operation.For current source inverters, a diode-inductor networkcan further be introduced accordingly, as shown in Fig. 3,where an X-shape network comprised of two inductorsand two diodes is inserted between the front-end circuitand inverter circuitry. Compared with the topology in Fig.

1188

Ijtic

Fric

(b)

Fig. 4. Equivalent circuits of Cuk-derived buck-boost inverter with adiode-inductor network when (a) SWO is switched OFF and (b) SWO is

switched ON.

2, two diodes and one inductor are added intentionally inorder to realize the expected performance. When the dcside switch SWO is turned OFF, the dc current id, flowsthrough the capacitor C1 to boost electrical energy storedin capacitor C1. At the same time, the diode DI and D2are now forward-biased to connect L1 and L2 in parallel,whose equivalent circuit is shown in Fig. 4(a), whereSWO effectively disconnects the diode-inductor networkfrom the input dc source making the current of capacitorC1 equal to input dc current. When SWO is turned ON,the capacitor discharging current of ic with input current

idc together would flow through diode-inductor networkand inverter circuitry to charge the inductive energystored in L1 and L2. Because diodes DI and D2 arenaturally reverse-biased in this case, the inductors L1 andL2 are forced to be connected in series as the current flowpath indicated in Fig. 4(b). Note that the inductor currentsneed to flow through CSI bridge served as the free-wheeling path, hence the null state should be commandedduring this period in order to not influence thenormalized volt-sec average, which implies the switchingstate of SWO = ON must be strictly commanded duringonly null intervals. Properly controlling the front-endactive switch and inverter bridge, an alternative seriescharging and parallel discharging operation of inductorcurrents therefore can be achieved whose chargingcurrent is the same as illustrated in Fig. 2, but dischargingcurrent released to ac load is the summation of twoinductor currents resulting in the double current boostseen from ac load when compared with the operationimplied in Fig. 2.

To derive the relationship between dc input and acoutput correctly, the capacitor current should be

Fig. 5. Topology of SEPIC-derived buck-boost CSI with a diode-inductor network.

calculated first. Assuming the switching period is T andthe conductive duty ratio of SWO is 1-k (O < k < 1).During SWO = OFF interval, the capacitor voltageincreases with a constant slope of id/C. During SWO =ON interval, the capacitor voltage falls with a constantslope of (iL-idc)iC. Because the average value of capacitorcurrent is expected to be zero in a switching period, theinductor current iL = iLl = iL2 can be derived as:

dC.kT = (I(k)T ; iL = iLl= iL2 ldc (2)C C 1-k<To fully utilize the boosted current, it is preferred to

use the summation of inductor currents as the effectivedc-link current with reference to the analyzed SWO =OFF state, therefore, the ac output peak current can beexpressed as:

i=M(iLl+iL2) =2Midc (3)MUL +L) =1-kIf a triplen harmonic offset is added to the modulationreferences, the modulation ratio M would increase with afactor of 1.15. Obviously, the output ac current is doubleboosted compared with (1) with the help of an X-shapediode-inductor network and can be stepped up or downby controlling M and k properly. Note that the six activeintervals in CSI switching should appear in the SWO =OFF interval if the current buck-boost operation isdesired to use the doubled inductor current as dc-linkcurrent. When active intervals locate in both SWO = ONand SWO = OFF intervals, the dc-link current wouldalternate between iL and 2iL causing the distorted outputbecause only iL not iLl + iL2 flows through invertercircuitry during SWO = ON interval.

B. SEPIC-Derived Buck-Boost CSI with a Diode-Inductor Network

Alternatively, the SEPIC-derived buck-boost CSI inFig. 1(b) can also be developed to couple a diode-inductor network between inverter circuitry and the front-end boost circuit to realize the enhanced current boostcapability as shown in Fig. 5. Analyzing the charging anddischarging process of capacitor current, it is observedthat the SEPIC-derived topology shows differentperformance features which would be illustrated below.Again, when the dc side switch SWO turns OFF, theconstant dc input current begins to charge capacitor C1,meanwhile, diodes DI and D2 are forward biased

1189

vc

Cl

ic

Iid

(b)

Fig. 6. Equivalent circuits of SEPIC-derived buck-boost inverter with adiode-inductor network when (a) SWO is switched OFF and (b) SWO is

switched ON.naturally making iLl and iL2 flow in parallel, as shown inthe equivalent circuit of Fig. 6(a). Therefore, the dc-linkcurrent can then be expressed as:

ii = iLl + iL2 + idc (4)During SWO = ON interval, dc current idc flows

through SWO and its series diode for free-wheelingwithout charging any passive component, and thedischarging capacitor current ic flows through twoinductors and inverter circuitry in series, as shown in Fig.6(b), which means the inductor current equals tocapacitor discharging current. Assuming the conductiveduty ratio of SWO is 1-k again, the capacitor dischargingcurrent can be expressed as:

k.ic=(1-k).ic .ic=iL= kic=k idc (5)c c c L ~1-k -1-kTherefore, the maximum dc-link current and peak ac

output current can be derived from (4) as:

=2k.idc 1+k. ,(I+k)

iik= ldc = *idc ; = ( )Midc (6)k I-k (1-k)Compared to Cuk-derived topology, both the inductor

current iL and the peak ac output current in SEPIC-derived topology are comparatively lesser if the samemodulation conditions are assumed for equations (2), (3)and (5), (6), since k < 1 and consequently, 1 + k < 2 in (6).

IV. MODULATION SCHEMES OF BUCK-BOOST CSISWITH A DIODE-INDUCTOR NETWORK

Because the gating signals of CSI can be mapped fromVSI switching states by using proper logic mappingtechnique [6], therefore, the intentional operation of

buck-boost CSI for unique output performance can becarried out by first controlling the corresponding VSImodulator. Depending on the different modulation targets,the gating signals of both SWO and rear-end inverter canbe generated for achieving either optimized harmonicperformance or minimal commutation count, meanwhilemaintaining the basic characteristic of current buck-boostoperation.

A. PWM Switching Scheme with Optimized HarmonicPerformance

To achieve optimized harmonic performance in two-level inverters, the null intervals in each switchingsequence must be kept equal, which is easy to beimplemented by adding a triplen harmonic offset (Voff =-0.5(max(VA, VB, Vc)+min(VA, VB, Vc))) to the sinusoidalreferences. Because the dc-link current is alternatingbetween idcI(l-k) and 2idcl(l-k) for Cuk-derived topologyand kidc /(I-k) and (l+k)idcl(I -k) for SEPIC-derivedtopology, respectively, according to the switching statusof SWO, therefore, the large value of dc-link current ispreferred to be used in the proposed buck-boost CSIs soas to demonstrate the advantage of enhanced currentboost capability. During SWO = OFF interval, the largedc-link current appears in both topologies, the traditionalactive states, therefore, should be restricted in thisinterval to keep normalized volt-sec average unchanged.Fig. 7 shows the exampled switching sequence designedfor achieving optimized harmonic performance in buck-boost VSI [7], which can be mapped to CSI modulationeasily, where SA, SB, SC represent the upper switches offull bridge VSI and SW refers to the dc side switch usedin buck-boost VSI whose switching signal is thecomplement of SWO in CSI modulation.Obviously, !SWO = SW = OFF states always locate innull intervals to maintain the normalized volt-sec averageunchanged. Following this modulation criteria, themodulation references suitable for buck-boost VSIoperation are derived as:

Va = M cos(") + VoffVb=Mcos(a-120')+VoffVc =Mcos(t + 1200) + Voffv = -Vd = k

ON OFF GATE SW= SWOOFF ON GATE SC

'OFF ON GATE SB

|FF i I IAdiinlLe.V l

SfON

~~~OFF ~ W=F

Fig. 7. Exampled switching sequence for buck-boost VSI withoptimized harmonic performance.

1190

IOK~ OFF ON i GATE SW !SWOOFF O GATE SC

'OFF GATE SB I

\ X?l SW=~ON *

OFF ONCATEASW=OFF

Fig. 8. Exampled switching sequence for buck-boost VSI with minimalcommutation count.

Where, Vu and Vd are the designed simple linearreferences for defining the conductive duty ratio of bothdc side switch SW for buck-boost VSIs and SW0 forbuck-boost CSIs by comparing with the specifictriangular carrier. In order to avoid the alternating dc-linkcurrent after the signal mapping in the proposed buck-boost CSIs, k should be restricted to be equal to or largerthan the amplitude of sinusoidal references.

B. PWM Switching Scheme with MinimallCommutation Count

Observing Fig. 7, it is found that SW0 switches twicein each switching cycle, which is due to the centralizedarrangement of active states forces the SW0 = ONinterval distributes in two null intervals. Although SW0 =ON state can locate only in either the first null interval rO,0, 0} or the last null interval ti, 1,1v (e.g.) of thedemonstrated switching period to reduce its commutationcount from two to one, the additional current stress wouldimpose on components because of the additionallyunnecessary duty ratio of SW0, which causes the actualconductive duty ratio of SW0 being samller than l-k.However, the modulation ratio M is still restricted by k,therefore, the modulation index is not fully utilized,especially when needing high boosted current, resultingin the unnecessary current stress crossing components. Inorder to reduce commutation count and current stresssimultaneously, this subsection presents an improvedmodulation method whose exampled switching sequenceis shown in Fig. 8. Being different from Fig. 7, only anadditional linear reference Vt, instead of V eand Vd, isused to compare with the specific triangular carrier.Three sinusoidal references are then consequently moved

= I1,1,0,0,0,1ISV3 = {0,1,0,1,0,1} jSV4= {0,1,1,1,0,0}SV5= {0,0,1,1,1,0}SV6= {1,0,1,0,1,0I

downwards in vertical to reduce null interval 1, 1, 1

without changing the normalized volt-sec average,

therefore, two null states are no longer locatesymmetrically in each switching sequence resulting in theinferior harmonic performance consequently. Now theconductive duty ratio k' of SW = ISWO is equal to(1 +k)12 when the same boosted dc current is desired. Theinductor current iL in equation (2) and (5) can then bechanged to the following equations, respectively, forclearly distinguishing the difference between these twomodulation schemes.

IL= L1 =L2 tL LI L2 1-k,1dc

, l+k 2.2k =2 1-k ldc

IL L1 L2 1 k ' ldc

1 l+k . +kk' 2 > 'L1 L2 = k 1dc

2 1-k

(8)

(9)

In (8) and (9), k' refers to the conductive duty ratio ofSW (=!SWO). Besides the triplen harmonic added forincreasing modulation ratio, another offset for shiftingsinusoidal references should also be introduced to reducecurrent stress. To summarize, the resulted modulationreferences are expressed as:

Va =M cos(t) +V --(I-k) / 2

Vb = Mcos(")t-120')+VVff -(l-k)/2 (10)

V, =Mcos(")t+1200)+VVff -(l -k)/2

u= -Vd = k

Since SWO = ON states and null states are the same

when seen from ac load, therefore, it's preferred toreplace null interval with SWO = ON interval as much as

possible to reduce unnecessary current stress, implyingthe redundancy of null interval is significantly decreased.

After the generation of VSI gating signals, a digitallogic mapping for CSI commands can be implementedusing one-to-one mapping and many-to-many mapping as

listed in Table I so that the diode-assisted buck-boostCSIs can be controlled properly.

V. EXPERIMENTAL RESULTS

For verifying the operational principles of proposeddiode-assisted buck-boost CSIs and modulation schemespresented, laboratory prototypes for Cuk- and SEPIC-

SC2 = {0,1,0,0,0,1 } {0}

SC3= {0,1,0,1,0,0} {0}SC4= {0,0,1,1,0,0} {0}SC5= {0,0,1,0,1,0} {0}SC6= {1,0,0,0,1,0I {0}

Active(One-to-OneMapping)

1191

SV7 = I 1'O',1 1, I I 0}SC7 = {I1,0,0,1,0,0} {0}or 1 } Null,V7= II,1,1,0,0,0 I SC8 {=,0,1,0,0,1,0} {0}or{1}I(ManyptoiManySV7 ~~~~~~I SC9 ={0,0,1,0,0,1}I {0}or{1}I Mapping)

Fig. 9. Experimental waveforms of Cuk-derived diode-assisted buck-boost CSI with optimized harmonic performance when M=k=0.3. TOPto BOTTOM: capacitor voltage, 20V/div; switched current, 5A/div;input current, 1.5A/div; filtered phase current, 2A/div. Time scale:

5ms/div.

-a fftX

TT

Tt+X................................. ...... - - t++ .

Fig. 10. Experimental waveforms of Cuk-derived diode-assisted buck-boost CSI with optimized harmonic performance when M=k=0.7. TOPto BOTTOM: capacitor voltage, 100V/div; switched current, 10A/div;input current, 1.5A/div; filtered phase current, 1OA/div. Time scale:

5ms/div.

derived diode-assisted buck-boost current sourceinverters were constructed using the passive componentsLI = L2= 20 mH and C = 15 tF and powered with theconstant dc input current id, = 1.5A. When the laboratoryprototype was configured as Cuk-derived diode-assistedbuck-boost CSI, the captured experimental waveformswith 1.15*M = 1.15*0.3 and k = 0.3 for optimizedharmonic performance are shown in Fig. 9, where theswitched current was effectively boosted to 2*1.5/(1-0.3)z 4.3A, and the peak filtered ac current was also inaccordance with the theoretical calculation from equation(3). To verify its corresponding current boost capability,Fig. 10 shows the captured experimental waveforms with1.15*M = 1.15*0.7 and k = 0.7, where the switchedcurrent was boosted around 2*1.5/(1-0.7) = IOA and thefiltered phase current exhibited the enhanced currentboost capability with the significant increase of currentamplitude achieved. Since the resistance of inductors canperturb the steady state operation point [8], the ac outputcurrents in both figures therefore have a slightdegradation of amplitude unlike the value acquired fromthe theoretical calculations. Next, to illustrate theoperational validity of SEPIC-derived diode-assistedbuck-boost CSI, Fig. 11 and Fig. 12 show the capturedwaveforms under the same modulation condition used forFig. 9 and 10, respectively. Both Fig. 11 and 12demonstrate the little inferior current boost capability

Fig. 11. Experimental waveforms of SEPIC-derived diode-assistedbuck-boost CSI with optimized harmonic performance when M=k=0.3.TOP to BOTTOM: capacitor voltage, 20V/div; switched current, 5A/div;

input current, 1.5A/div; filtered phase current, 2A/div. Time scale:5ms/div.

Fig. 12. Experimental waveforms of SEPIC-derived diode-assistedbuck-boost CSI with optimized harmonic performance when M=k=0.7.TOP to BOTTOM: capacitor voltage, 100V/div; switched current,

10A/div; input current, 1.5A/div; filtered phase current, 10A/div. Timescale: 5ms/div.

when compared with Fig. 9 and 10, because the inherentoperational principles of SEPIC-derived diode-assistedtopology limit its current boost capability according toequation (5) and (6). The current stress across inductor L1and L2, however, is significantly reduced, which impliesthat the rating of inductors of diode-inductor network inSEPIC-derived diode-assisted topology can be chosenless than those used in Cuk-derived diode-assistedtopology in practice.

Comparatively, the verifications of modulation schemewith minimal commutation count are shown in Fig. 13and Fig. 14 for Cuk-derived diode-assisted topology andFig. 15 and Fig. 16 for SEPIC-derived diode-assistedtopology, respectively, under the same modulationconditions as those used for the modulation scheme withoptimized harmonic performance. Clearly, the similaroutput performances are achieved as expected, except ofthe inferior harmonic performance obviously observedfrom the waveforms of capacitor voltage (top waveformin all experimental results).

VI. CONCLUSIONThis paper proposes a set of enhanced current buck-

boost CSIs using a special designed diode-inductornetwork coupled between inverter circuitry and front-endcircuit to perform series charging and parallel dischargingprocesses between inductors, which is simply achieved

1192

;k; ii:Ik1wm6da"O."

...... ...... , ---- -'. -, -.1

ON

Fig. 13. Experimental waveforms of Cuk-derived diode-assisted buck-boost CSI with minimal commutation count when M=k'=0.3. TOP toBOTTOM: capacitor voltage, 20V/div; switched current, 5A/div; inputcurrent, 1.5A/div; filtered phase current, 2A/div. Time scale: 5ms/div.

Fig. 14. Experimental waveforms of Cuk-derived diode-assisted buck-boost CSI with minimal commutation count when M=k'=0.7. TOP toBOTTOM: capacitor voltage, 100V/div; switched current, 1OA/div;input current, 1.5A/div; filtered phase current, 1OA/div. Time scale:

5ms/div.

by the block property of unidirectional diodes in the X-shape network. Modulation wise, the proposed invertercan be controlled with the designed modulation schemesfor achieving either optimized harmonic performance orminimal commutation count, meanwhile keeping thecurrent stress across components as little as possible.Although the SEPIC-derived diode-assisted topologycannot acquire the same boosted capability as Cuk-derived diode-assisted topology when the samemodulation condition is assumed, it exhibits therequirement for the current rating of inductors iscomparatively less. All theoretical findings were verifiedexperimentally using the constructed laboratoryprototypes with captured results for visual confirmation.

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Fig. 15. Experimental waveforms of SEPIC-derived diode-assistedbuck-boost CSI with minimal commutation count when M=k'=0.3. TOP

to BOTTOM: capacitor voltage, 20V/div; switched current, 5A/div;input current, 1.5A/div; filtered phase current, 2A/div. Time scale:

5ms/div.

Fig. 16. Experimental waveforms of SEPIC-derived diode-assistedbuck-boost CSI with minimal commutation count when M=k'=0.7. TOPto BOTTOM: capacitor voltage, 100V/div; switched current, 1OA/div;input current, 1.5A/div; filtered phase current, 10A/div. Time scale:

5ms/div.

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1193

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