21
Digital to Analog Converter for High Fidelity Audio Applications Matt Smith Alfred Wanga CSE598A

Digital to Analog Converter for High Fidelity Audio Applications Matt Smith Alfred Wanga CSE598A

Embed Size (px)

Citation preview

Digital to Analog Converter for High Fidelity Audio Applications

Matt SmithAlfred Wanga

CSE598A

Project Summary

• High Quality Audio Applications– Accurate Reproduction [16 bit]– Low Noise

• Versatile– Support for Standard Sampling Rates– Specifications that allow use in Various Audio

Applications

R-2R Ladder Architecture

* Buffer inserted on output for low output impedance

D Flip Flop Schematic

D Flip-Flop Simulation Results

CLK

DIN

Q

QNOT

Pass Switch

• NMOS pass transistor only

• CMOS Transmission gate not needed because we don’t go near VDD

• Sized to allow proper operation

Voltage Reference

Voltage Reference Results

• Circuit modified from Homework #3 provides 2.5V and 1.1V voltage reference

• Reference output stable down to ~3.3V supply voltage

• 2.5V reference varies by 400mV over -40C to 85C (3.2 mV/˚C)

• 1.1V reference varies by 150mV over -40C to 85C (1.2 mV/˚C)

Voltage Reference Results

• Power supply rejection ratio is 48dB

• LSB accuracy corresponds with 7mV p-p supply noise

Resistor

• 400K resistor takes ~13,700 um2

• We used values of 400.010K, 200.005K, 16.146K, and 8.073K

• Resistors are a large part of area, but there is room to spare in the pad frame

• Using large resistors decreased power and tx_gate size

Output Buffer

• Unity gain opamp• Open loop gain = 2560

Output BufferThe high end wasn’t a problem – we wouldn’t go that high

But what to do about the low end?

Output Filter

Noise peaks are up to 12LSB

* Noise also decreased significantly by the addition of a 10uF capacitor from Vref to ground

Complete Design Schematic

0 7

815

Source-follower and

output buffer

200K resistors

D - Flip Flops

Bias

Final Layout

400K resistors

Transistor Switches

Heavy-duty unity-gain buffer

Simulation Results - Overall

Schematic simulation of the entire circuit

Simulation Results – Zoom-In

• Full-circuit simulation with all 16 bits operating.

• LSB increments are 28uV

• Noise on the vast majority of transitions is < 0.05 LSB

Simulation Results - Noise

MSB transition point – momentary noise: 3.56mV (128LSB)

• Noise and non-linearity occur at significant bit transitions

• Trade-off between noise and non-linearity

• Tx_gates too small gives large non-linearity

• Tx_gates too large give large noise spikes

• Placing a huge capacitor (10uF) on the Vbias power line to the array helps transient noise

• Noise and non-linearity are worst for MSB and decrease by powers of 2 for less-significant bits

Simulation Results - Speed

Fall time: 6.5us Rise time: 80ns

• Absolute maximum frequency where the circuit can achieve full amplitude is 1/(6.58us) = 152kHz

• Little distortion of full-amplitude square wave at the limit of human hearing (20kHz)

• No distortion of full-amplitude sine wave at 20kHz

Design Assessment

• Maximum output voltage: 3.441V

• Minimum output voltage: 1.604V

• Voltage swing: 1.836V

• LSB voltage change: 28uV

• Maximum Differential Non-linearity: 1LSB

• Integral Non-linearity: Approximately 16LSB

• Power consumption: 23.5mW

Future Work / Improvements

• Temperature stability (reference)

• Wide swing output

• Better low-pass filter would allow larger tx_gate and less integral non-linearity